Dear all,
My name is Jacob Bernstein. I work for News Digital System (Israel) at the
Failure Analysis Lab.
I would appreciate very much your advice on the following practical
problems that I face.
For failure analysis of individual VLSI chips (5x5mm size) I need to create
interconnections over
the oxide/nitride passivation layer and underlying Al signal lines to
facilitate electrical probing.
To prevent the damage to the chip due to etching I use the lift-off process
for contact lines deposition,
followed by FIB technique with Pt or W for via.
I am currently using the lift-off procedure described in the web site
(Appendix A, chap6.3 at
www-microlab.eecs.berkeley.edu) with NRC evaporation system in an external
laboratory for deposition
of the contact lines (300 nm Au, with 30 nm Cr adhesion layer);
I had reasonable results, the only problem being that the high temperature
of evaporation causes heat damage to the photoresist.
Now, I am interested in purchasing a coater of my own.
Because of the above problem , I am considering to buy an inexpensive
sputter coater for contact lines deposition.
Can you please recommend on an appropriate model for my application?
Do you suggest perhaps the use of other metals? or other techniques?
Please take into consideration, that the chip I am analyzing consist of
EEPROM with written data, so any method of deposition must not affect this
data.
Thanks in advance,
Jacob Bernstein
This archive was generated by hypermail 2b29 : Tue Mar 09 2004 - 07:49:01 EST