As chair of the Advanced Techniques session, I'd like to invite you to
submit an abstract for consideration at this year's International Symposium for Testing and Failure Analysis (ISTFA), the premiere industry conference for failure analysis of
integrated circuits, electronic components, and systems.
We are specifically seeking research and application summaries of
leading-edge methods for locating, isolating, characterizing, imaging, and
modeling faulty circuits and defects in sub-130nm ULSI CMOS, SOI,
mixed-signal, analog, SiGe, and MEMS devices, and associated packaging.
Also of interest are emerging electrical and physical analytical methods
for nanotechnology that may be applicable. A list of relevant categories
and topics appears below.
* General symposium details and call-for-papers: http://www.asminternational.org/istfa/home.htm
* Abstract submission deadline: March, 3, 2003
At your discretion, please forward this note to colleagues or departments
working in related fields or disciplines.
Do not hesitate to contact me for further information, reference
literature and problem statements, or to assess the applicability of your
work to this field.
Selected Specific Topics of Interest:
Diagnostic electrical testing
Defect-based testing, scan-chain diagnosis, or bit-fail mapping for fault
isolation and characterization
Design-for-diagnosability architecture, self-diagnosis, fault-tolerant
design, etc.
Contact or contactless probing and measurement for signal injection and
characterization on nanometer scale conductors
Electronic packaging characterization and failure analysis (e.g., TDR,
thermography, SQUID, or other approaches for locating open or short
circuits)
Sensing and/or perturbation of physical or electrical effects on operating
ICs for fault isolation
Photon emission microscopy and related sensors (e.g., Si CCD, InGaAs,
InSb, MCT, other NIR imagers)
Magnetic field imaging (SQUID, MR, MTJ, other magnetometers) for
current-density mapping
Microwave imaging
Laser-scanning microscopy for photon injection, thermally-induced
resistance change, OBIC, etc.
Scanning electron beam analysis (e.g., EBIC, voltage contrast,
absorbed-current imaging)
Thermography by infrared imaging, reflectance, Schlieren, other dn/dT
sensing, etc.
Active circuit timing measurement by electro-optic sampling, time-resolved
photon emission, electric field sensing, or other methods
Scanning-probe microscopy (capacitance, magnetic force, thermal, etc.)
Scanning tunnelling microscopy
Any new sensors or probes for detecting or localizing nanoscale short
circuits, voids, and open conductors
Any new probes for perturbing nanoscale short circuits, voids, and open
conductors for purposes of localization
Signal analysis, enhancement, and noise reduction techniques applicable to
the above
Microscopy and Imaging
X-ray, fluorescence, acoustic, laser, proton/neutron/electron/ion beam
microscopy (SEM, TEM, BEEM, etc.)
Image post-processing by tomography, holography, etc.
Near-infrared microscopy for sub-surface imaging through heavily doped
silicon
Scanning-probe microscopy (atomic force, Kelvin, NSOM, etc.)
Scanning tunneling microscopy
Other advanced semiconductor materials imaging methods
Related image processing, filtering, and analysis techniques
Sample preparation, structural modification, chemical and materials
analysis
Focused ion beam or other high-precision techniques for micro/nano milling
of silicon, SiO2, lo-k dielectrics, polymers, copper, and related
materials
Focused ion beam or other methods for locally depositing thin-film
insulators and conductors for chip rewiring or repair
Machining, polishing, cutting, ion milling and thinning of silicon and
high-Tc electronic packaging materials (ceramic, carbides, epoxies, etc.)
Mechanical and chemical depackaging, deprocessing, and delayering
(polishing, milling, plasma and wet-chemical etching, ion milling, etc.),
especially related to low-k dielectric materials
Chemical and materials analysis for nanoscale films and defects
(microcalorimetry, EELS, SIMS, AES, etc.)
Nanomanipulation, deposition, and removal of silicon, SiO2, polymers,
metals, and related semiconductor materials for modifying or
characterizing as-built structures
Failure or yield analysis methods and business processes
Signature analysis and sampling
Correlation of in-line defect analysis to tested defects
Cost/benefit modelling and analysis
Thank you.
David Vallett
IBM Microelectronics Division - Essex Junction, Vermont, USA
Analytical Services Failure Analysis - Strategic Development
dvallett@us.ibm.com
Office: 802 769-2232
Lab: 802 769-3527
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