Kevin:
I didn't see any other responses to this, so let me take a stab ...
[1] I suspect that there probably is a certain level of Ga and I'd guess
that the amount is probably related to how volatile the fluorides and
chlorides of Ga are. A quick look at the Handbook of Chemistry an Physics,
however, makes me guess that it hangs around in the system compared to SiF4
and SiCl4, for example. However, I don't profess to be an expert. You
might check with Jim McVittie in our lab (mcvittie@snf.stanford.edu) ...
[2] I would think that TXRF would be a more sensitive tool for detecting
this type of contamination after an etch step where, I think, you'd expect
the contamination to either be on the surface or very close to it.
[3] Since Ga is a P-type dopant, I think that this should allow you to
determine what level that you can tolerate in a device. Of course, you also
have to factor in, I think, the fact that Ga has an exceedingly high
diffusion coefficient in SiO2 ... which explains why it is rarely used for
silicon device applications.
[4] Another quick experiment, I think would be to put the most lightly doped
n-type wafer in your ICP system and etch it following etch of a
Ga-containing alloy. Then clean the wafer as you would normally when coming
out of the system and anneal it for some reasonable time: without knowing
your specific process I'd suggest the window of 30 min at 900 degC to 30 min
at 1000 degC. Then, ship it out for spreading resistance or do a careful
sheet-rho measurement to see if you have a P-type layer or not. If you
don't, then I'd think that this would be reasonably conclusive proof that it
couldn't affect your CMOS devices ... even if you assume that the Ga would
penetrate all SiO2 layers at will.
At least that's my opinion ... for what it's worth.
John
----- Original Message -----
From: "Kevin Martin" <kevin.martin@mirc.gatech.edu>
To: <labnetwork@mtl.mit.edu>
Sent: Friday, February 20, 2004 12:07 PM
Subject: Questions on detecting Ga contamination
> Dear Labnet Users:
>
> The left hand chamber on our Unaxis ICP system is used to etch SiOx,
> compound semiconductors (including Ga-containing alloys) polymers, BCB,
and
> other materials. One of our CMOS customers is using that same chamber for
> etching vias through SiOx down to Si for source and drain contacts. He is
> concerned that there might be Ga contamination that would ruin his
> devices. Perhaps one of you could help answer these questions:
>
> [1] Is it likely that there could be some Ga contamination from residual
Ga
> in the chamber?
>
> [2] If so, would it be detectable by SIMS?
>
> [3] Is there an upper limit to acceptable Ga contamination in a CMOS
device?
>
> [4] If so, is SIMS capable of detecting this level of Ga in Si? If not,
is
> there another suggested method to detect Ga?
>
> Thanks
>
> kpm
>
>
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