MTL Annual Research Report 2007

Circuits & Systems

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Test Structures and Optimization Methodologies for Electrical Variation in IC Manufacturing
A Micropower DSP Architecture for Self-powered Microsensor Applications
A Sub-threshold Cell Library and Methodology
Minimum Energy Tracking Loop with Embedded DC-DC Converter in 65-nm CMOS
A 65-nm 8T Sub-threshold SRAM Employing Sense-amplifier Redundancy
A 65-nm, Ultra-dynamic Voltage, Scalable SRAM with Operating Range from 300mV to 1.2V for Optimal Performance and Energy
Algorithms and Architectures for Ultra-low-power Video Compression
An All-digital UWB Transmitter in 90-nm CMOS
A 3- to 5-GHz Sub-banded UWB Receiver in 90-nm CMOS
Pulsed UWB Transceiver for Small Lightweight Flying Vehicles
Reaching the Optimal Mixed-signal Energy Point
18Gb/s Optical IO: VCSEL Driver and TIA in 90-nm CMOS
Reconfigurable Zero-crossing-cased Analog Circuits
Design and Characterization of CNT-CMOS Hybrid Systems
A Piecewise-linear Moment-matching Approach to Parameterized Model Order Reduction for Highly Nonlinear Systems
A Quasi-convex Optimization Approach to Parameterized Model-order Reduction
Open-loop Digital Predistortion Using Cartesian Feedback for Adaptive RF Power Amplifier Linearization
Wideband Two-point Modulators for Multi-standard Transceivers
An Ultra-low Power CMOS RF Transceiver for Medical Implants
An Integrated Circuit Capable of Rapid Multi-frequency Measurements and a Reconfigurable Electrode Array for Use in Anisotropic Electrical Impedance Myography
Equation-based Hierarchical Optimization of a Pipelined ADC
A Hierarchical Bottom-up, Equation-based Optimization Design Methodology for RF Transceivers
Comparator-based Switched Capacitor Circuits (CBSC)
A Zero-crossing Based, 8b, 200MS/s Pipelined ADC
Ultra-high Speed A/D Converters Using Zero-crossing-based Circuits
High-accuracy Pipelined A/D Converter Based on Zero-crossing Switched Capacitor Circuits
Low-voltage Comparator-based Switched-capacitor Sigma-delta ADC
Zero-crossing-based ADC for mm-Wave Applications
Comparator-based Circuits for HBTs
Massively Parallel ADC with Self-calibration
Prediction of Time-to-contact for Intelligent Vehicles
Very High-frequency DC-DC Boost Conversion
Techniques for Low-jitter Clock Multiplication
A Digitally-enhanced Delta-sigma Fractional-N Synthesizer
Voltage-controlled Oscillator-based A/D Conversion
A ΣΔ ADC with Noise-shaping VCO Quantizer and DEM Circuit
A Sub Picosecond Time-to-digital Converter for On-chip Jitter Measurement
Techniques for Highly-digital Implementation of Clock and Data Recovery Circuits
Low-power CMOS Rectifier Design for RFID Applications
Low-power Circuits for Brain-machine Interfaces
A 77-GHz Receiver Front-end for Passive Imaging
Power Amplifier Design for Millimeter-Wave Imaging
A 77-GHz System for Millimeter-Wave Active Imaging
Coding in Wideband OFDM Wireless Communications with Adaptive Modulation
An Organic Imager for Flexible Large Area Electronics
Channel- and Circuits-aware, Energy-efficient Coding for High-speed Links
Design and Optimization of Equalized Interconnects for Energy-efficient On-chip Networks
System-to-circuit Framework for High-speed Link Design-space Exploration
System Architecture Implications of CNT Interconnects

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