"Well-Tempered" Bulk-Si NMOSFET Device Home Page

Rev. 11/1/01

Dimitri A. Antoniadis, Ihsan J. Djomehri, Keith M. Jackson, Stephanie Miller

Microsystems Technology Laboratory, MIT

90-nm-Device

25-nm-Device

50-nm-Device

13-nm-Device

9-nm-Device

Statement of Purpose:

This page grew out of an SRC/NSF Workshop on future challenges in computational electronics that was held on February 1999 at NIST. One recommendation was that we should compare existing simulation tools against real data for a well- characterized MOSFET, so that we (as a community) understand what our current tools are telling us and how they compare. At the same time, we'd look at a hypothetical, well-designed MOSFET of the future (which we may not even know how to build) to push the tools to their limits and to study which physical phenomena are essential for simulating the operation of MOSFETs at very small dimensions. This page was designed to provide in the public domain the device design and measurement data that can serve as a common basis for simulation studies in a follow up workshop (NASA Ames Device Modeling Workshop August 26/27, 1999) and other informal exercises.