About

Multimedia applications, such as video playback, are becoming increasingly pervasive on battery-operated handheld devices such as camera phones, digital still cameras, personal media players, etc. As a result, it is increasingly important that video compression-decompression (CODEC) become power efficient since the battery life is limited by the size, weight and cost of the portable devices.

The MIT Portable Multimedia Group (PMMG) is exploring power reduction techniques at various design stages (algorithms, architectures and circuits) of the video CODEC. An effective method of reducing power involves the combination of aggressive voltage scaling and increased parallelism and pipelining to maintain performance. Additional architectural optimizations for power reduction such as reducing memory accesses and multiple frequency/voltage domains are also investigated.

Transistor mismatches are becoming more and more prominent in deep-sub-micron processes requiring larger design margins for high yield. Moreover, the effect of mismatches are exacerbated at lower voltages making low-voltage designs very challenging to implement due to functionality problems in SRAMs and due to timing violations in critical paths. Different circuit techniques and timing analysis methods are investigated in our group to address these issues with minimum power, performance and area overhead.

High coding efficiency often comes at a cost of increased complexity which translates to increased energy consumption. For instance, H.264/AVC, the latest video coding standard, provides a 50% improvement in compression efficiency over previous standards at the cost of increased decoder complexity of 4X over MPEG-2 and 2X over MPEG-4 Visual Simple Profile.

Accordingly, the PMMG is developing algorithms for next generation video coding standard 'H.265'. These algorithms will have enhanced parallelism such that the low power approach can be more easily applied in the future and to improve the coding-efficiency - power trade-off.

In addition to video, PMMG is looking at audio playback, which is another highly used feature in handheld devices. Because of the different audio playback settings (e.g. equalization) and formats, the workload on the processor can vary significantly. Voltage-scaling can provide the necessary adaptation to the workload changes and provide significant power savings.

Video

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  1. High definition 720p mobcal sequence playback at 30 frames per second.
  2. PCB with H.264/AVC decoder test chip (black square socket in center).
    Decoded video goes through ribbon cables to VGA socket to LCD display.
  3. Clock signals on scope: top (yellow) is the core 14 MHz clock.
    Bottom (blue) is the memory controller 50 MHz clock.
  4. Core domain consumes <1mW from a 0.73 V power supply.
  5. Real-time 720p 30fps, H.264/AVC video playback system.

 

 

Latest News

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  • Daniel FinchelsteinMIT students receive Outstanding Design Award
    at 2008 A-SSCC Student Design Contest
    for ultra-low power video decoder     Fukuoka, Japan; November 3-5, 2008 http://www.a-sscc.org/program.html
  • Mahmut“A Low-Power 0.7-V H.264 720p Video Decoder”
    highlighted as one of 9 “Noteworthy Technical Papers”
    at A-SSCC 2008     Fukuoka, Japan; November 3-5, 2008 http://www.a-sscc.org/program.html
  • Vivienne SzeVivienne Sze wins Presentation Award at 2008 MTL Annual Research Conference for“Algorithms and Architectures
    for Ultra-Low-Power Video Compression”     Waterville Valley, NH; January 29-30, 2008 http://mtlweb.mit.edu/marc2008/