Substrate Noise Analysis: Digital Integrated Circuits and Systems Group

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Mixed-signal circuit design has historically been a challenge for several reasons.  Parasitic interactions between analog and digital systems on a single die are one such challenge.  Switching transients induced by digital circuits inject noise into the common substrate.  Analog circuits lack the large noise margins of digital circuits, thus making them susceptible to substrate voltage variations.  This problem is exacerbated at higher frequencies as the effectiveness of standard isolation technique diminishes considerably.

The effect of substrate noise on the circuits within an IC is typically observed during the testing phase only after the chip has been fabricated. Determination of the substrate noise coupling during the design phase would be extremely beneficial to circuit designers who can see the effect of the coupling on the circuits and re-design accordingly before fabrication. This would reduce the turn around time for circuits and increase the yield of working chips.

We developed a substrate noise analysis tool (SNAT) that can be used at any point in the design flow. The tool requires information on the circuit as well as the technology. The circuit information can be as descriptive as the circuit netlist complete with extracted parasitics or as coarse as a verilog netlist. The technology information can be as descriptive as a full substrate doping profile with layout or as coarse as knowing only the substrate resistivity and die size.

The tool generates equivalent noise macromodels to describe the digital system.  These macromodels are then coupled with a model for the substrate to yield noise information such as the time domain profile or spectrum at different points on the substrate. The noise as a result of shaping by different isolation techniques can also be determined. The resulting substrate noise data can then be used to simulate its effect on various analog circuits.

We have verified the results of SNAT with measurements on a digital PLL designed in TI’s 90 nm technology.   SNAT yields 12% error in the RMS voltage of the substrate noise when compared to measurements.

SNAT

SNAT is a substrate noise analysis CAD tool to generate substrate noise profiles of large digital systems.

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Above: Diagram of Substrate Noise Analysis Tool (SNAT)

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Substrate Noise Group
Massachusetts Institute of Technology
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Cambridge, MA 02139-4307

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