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Pulse-based UWB Architectures

In February, 2002, FCC approved the use of UWB for communications. It allows then the reuse of highly crowded frequency bandwidth for other services. Ultra-Wideband radio trasmits the information using very narrow pulses (in the order of a fraction of a nanosecond) with very small duty cycle. The signal, in this way, extends over a large bandwidth (several gigahertzs) and can be buried in the environment noise in a way that does not interfere with other services. Figure 1 shows this situation.

Figure 1 Figure 1:
Spectrum of a
UWB signal

(click for larger image)

The use of narrow pulses implies several advantages:

  • An almost digital implementation is feasible, avoiding otherwise expensive and power hungry analog components.
  • The bandwidth available is from 3.1 GHz to 10 GHz, so, even with other non-UWB signals presents, it is still possible to achieve data rates in the order of hundreds of megabits per second.
  • Multipath is more easily detected as the different echoes from the same signal can be distinguished. RAKE architectures and other ways to take advantage of it come naturally.

A History of UWB Projects at MIT

3.1-10.6GHz Antenna
Johnna Powell

This work focused on differential and single ended antenna designs for Ultra Wideband 3.1-10.6GHz communication. The primary design is an ultra thin, low profile differential antenna with an incorporated ground plane for use with a UWB IC receiver. The differential capability eases the design complexity of the RF Front-End, and the incorporation of a ground plane enables conformability with small electronic UWB devices. Both designs result in excellent bandwidth, efficiency, and nearly omnidirectional radiation patterns. Viability of these antennas is tested with a UWB pulse transmitter.

Version 0: Baseband UWB Transceiver
Raul Blazquez, Fred Lee, Puneet Newaskar

A complete system-on-a-chip transceiver supporting BPSK ultra-wideband pulsed-based signals was implemented using 0.18um CMOS in this chip. The receiver uses a mainly digital architecture that is feasible because only four bits are required in the analog to digital converter (ADC). A 2GSPs FLASH interleaved ADC at 4 bits is used. Synchronization and signal demodulation are implemented entirely in the digital domain that exploits extensive parallelization to analyze the data coming from the ADC and to reduce the average time to achieve coarse acquisition to 70us. The transmitter is comparatively simple, occupying only 2% of the die area. A wireless link with a data rate of 193kbps was demonstrated with this transceiver.

Version 1.1: Flexible Prototyping Platform
Raul Blazquez, Fred Lee, Johnna Powell, David Wentzloff

This discrete prototype is built using off-the-shelf components and commercially available test and measurement equipment. It can be divided into three distinct sections: the transmitter, the receiver, and the baseband processing. The transmitter and receiver communicate using wideband horn antenna.

The transmitted UWB signal is synthesized using a programmable 4GS/s arbitrary waveform generator (AWG) to generate a baseband modulated signal, and a vector signal generator (VSG) to up-convert the signal to a center frequency of 5.355GHz. The analog bandwidth is 500MHz, therefore virtually modulation scheme or pulse shape can be synthesized.

The RF front-end (pictured) is built entirely using discrete components. The received signal is amplified by two cascaded LNAs, then split and applied to two identical passive mixers performing I/Q direct conversion. The baseband signal is filtered and amplified with an adjustable gain.

The baseband I and Q signals from the front-end are sampled by a dual-channel, 8-bit, 1GS/s ADC board that interfaces to a PC directly through the PCI bus. The received samples are buffered and captured to a file, later to be processed by Matlab. Once the samples are read into Matlab, virtually any baseband algorithm not requiring real-time control of the system may be tested. This includes acquisition and fine tracking, channel estimation, interferer rejection, and demodulation.

Version 1.2: 50Mb/s FPGA Prototype Transceiver
Nathan Ackerman, Raul Blazquez, Kyle Gilpin, Brian Ginsburg, Fred Lee, Vivienne Sze, David Wentzloff

This prototype transceiver is built using discrete components. It communicates in a 500MHz band centered at 5.355GHz using BPSK pulses with a pulse repetition frequency of 50MHz. The received signal is down-converted to I/Q baseband signals which are digitized by dual Atmel ADCs. Synchronization and demodulation are implemented in a Xilinx Virtex II FPGA enabling real-time communication at 50Mb/s. The transceiver communicates with a PC over USB2.0.

Real-time one-way transmission of a video stream over the air has been demonstrated at 50Mb/s raw data rate using this transceiver.

Version 2: 100Mb/s 3.1-10.6GHz Transceiver Chipset
Raul blazquez, Brian Ginsburg, Fred Lee, Johnna Powell, David Wentzloff

The RF front-end IC was fabricated in a 0.18um SiGe BiCMOS process. This chip performs pulsed-UWB communication in 14 channels spaced 528MHz apart in the 3.1-10.6GHz band. It features an FCC compliant BPSK pulse-shaping transmitter, a direct-conversion receiver with 802.11a notch filtering, and a cross-coupled quadrature VCO for channel selection.

Dual 500MS/s, 5b ADCs were implemented in a 0.18um CMOS process. Each ADC has a 6-way time-interleaved successive approximation register topology featuring self-timed bit-cycling, full custom digital logic, and duty-cycled preamplifiers for low static current consumption. The ADCs can also scale resolution from 1 to 5 bits for further energy savings.

The digital baseband is being designed in a CMOS technology. In order to reliably transmit 100Mb/s at 10m it is necessary to address the multipath that may affect communication in the UWB channel. This is performed in the digital baseband that includes both a RAKE receiver with a variable number of fingers and a Viterbi MLSE.

The baseband characterizes the channel quality in terms of the channel impulse response and the SNR. It also exposes several knobs that allow the complexity of some of its blocks to be controlled (i.e., number of bits of the channel estimation, length of the channel impulse response, number of states of the Viterbi MLSE). Based on the channel quality, higher levels of the communication hierarchy may use these knobs to trade off quality of service with power consumption and complexity for any given channel quality conditions. The core of this baseband is a set of parallel correlators. By adjusting the number of parallel correlations performed with this core it is possible to trade off preamble duration with probability of packet acquisition.

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The UWB Project @ MIT is sponsored by:
The HP-MIT Alliance and the NSF
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