The Problem and Goal:

MIMD (Multi-Instruction Multi-Data) array processors have high performance for image processing, radar signal processing, and other signal processing because of their high parallelism and flexibility. Conventional MIMD processors are too large and expensive for intelligent transportation applications. The goal was to develop a compact-size inexpensive array processor with a MIMD capability.

Approach:

Each processing element consists of an ALU (Arithmetic/Logic Unit), a data flow control unit, instruction memory, and data memory. The size of the processing element was reduced by replacing a conventional digital ALU with a mixed-signal ALU. The mixed-signal ALU utilizes both analog and digital circuits. Its feature is a small silicon area to achieve limited accuracy. The small size helped to implement the MIMD capability with low cost. The size of each processing element of our prototype, fabricated in a 5V 0.8um triple metal CMOS process, is 700um by 270um, and therefore 529 processing elements could be implemented within 1 cm² silicon area. The accuracy is comparable to a 7-bit digital processor.

Prototype:

A prototype chip was fabricated and evaluated (See Figure 1). The chip consists of a 5x5 array of processing elements.

Each processing element can communicate with its North, South, East, and West neighbors over an analog voltage line as shown in Figure 2.

Functions of the ALU include multiplication, division, addition, and subtraction. Figure 3 shows how multiplication and division are carried out by using a combination of analog-to-digital and digital-to-analog converters.

Addition operations use two capacitors and one operational amplifier as shown in Figure 4, and subtraction is handled in a similar way.

Current Status and Future Work:

The prototype chip was applied to a stereo vision algorithm successfully in an off-line mode. The algorithm includes gradient calculations, correlations, and sub-pixel interpolations. A real-time operation is under development.