Permitting Guidance for Semiconductor Manufacturing Facilities

From:
James F. Pendergast, Acting Director, Permits Division
Sheila E. Frace, Acting Director Engineering & Analysis Division

To: Regional Water management Division Directors

Subject: Permitting Guidance for Semiconductor Manufacturing Facilities

Introduction

Clarification has been requested by semiconductor manufacturing facilities regarding the scope of 40 C.F.R. Part 469, Electrical and Electronic Components Point Source Category, and 40 C.F.R. Part 433, Metal Finishing Point Source Category. Currently, semiconductor manufacturing facilities are regulated by Subpart A of Part 469, and may also have certain unit operations regulated by Part 433. Apparently there have been inconsistent approaches used by permitting authorities with regard to when to apply 469 and 433 requirements to the semiconductor manufacturing process. There have also been concerns raised about the applicability of the guidelines considering the pace of advancements and the introduction of new technologies in the semiconductor industry. This guidance is intended to provide an overview of the semiconductor manufacturing process, discuss the overlap between Parts 469 and 433, and examine new and emerging manufacturing technologies and how these processes fit into the regulatory framework of Parts 469 and 433. A more complete discussion of these issues can be found in Attachment 1.

Semiconductor Manufacturing Processes

Semiconductor manufacturing, for the purposes of this guidance, can be grouped into three categories: (1) crystal wafer growth and preparation; (2) semiconductor fabrication (also referred to as wafer fabrication); and (3) final assembly. The semiconductor fabrication processes are typically performed in a clean room and include the following steps: oxidation, lithography, etching, doping (through processes such as vapor phase deposition and ion implantation), and layering (through processes such as metallization). During the fabrication process, wafers may be cycled through several of these steps and some of the steps may be repeated for various purposes at different points in the process.

The final step in the manufacture of semiconductors consists of assembly and packaging of the semiconductor for final product. In assembly and packaging, the chips proceed from one operation to the next, undergoing each operation only once, though the order of processes depends on the package type and other factors. Semiconductor assembly and packaging processes include wafer separation and sorting, mounting and bonding of the semiconductor to the appropriate mount media, electrically interconnecting the semiconductor in the package, and final package preparation.

Emerging Technologies

Certain semiconductor manufactures have recently begun performing a Controlled Collapse Chip Connection (C4) electroplating process to add selective thin metal deposits to the surface of the wafer to act as connection points during wafer fabrication. According to industry personnel, this process is required to allow for increased connection points caused by decreased circuit size (hence an increase in the number of devices per semiconductor).

Several semiconductor manufacturers recently began performing a new process for using copper to replace aluminum in microprocessors during wafer fabrication, enhancing electron migration and reducing the width of the circuitry. These sites use a copper metallization process, in which copper is applied with an electroplating operation followed by a rinse. The process deposits a microscopic layer of copper on selected (i.e. circuitry) portions of the wafer.

Both of these processes are part of a sequence of photolithography, etching, and copper deposition processes performed in a clean room environment.

Conclusion

There are new, emerging technologies involved in semiconductor wafer fabrication which involve electroplating type operations. In these operations, metal is applied with an electroplating operation followed by a rinse which may lead permitting authorities to believe the 40 CFR Part 433 regulations should apply. However, as described above, due to emerging wafer fabrication technologies the electroplating operations in wafer fabrication and electroplating operations regulated by 40 CFR Part 433 can be distinguished:

In the wafer fabrication process, electroplating type operations add microscopic amounts of metal to selective portions of the wafer to enhance the circuitry and decrease wafer size.
In the final assembly and packaging process, metal layers are applied electrolytically through an electroplating process in which the packages are mounted on racks. Each lead connects to an electric potential to provide contact points for final assembly. The racks are placed in the electroplating solution, where the metal is applied. This process is followed by a rinse. This is typical of the electroplating process considered in the development of the Part 433 regulation.

After carefully reviewing both the Part 469 and 433 regulations and their associated background documents, examining past regulatory interpretations, visiting semiconductor manufacturing facilities, speaking with the industry, and reviewing current articles and books on the processes, the Agency believes that semiconductor manufacturing can be broken into two sections for the purposes of applying the requirements of 40 CFR Parts 469 and 433. The first section is the wafer fabrication process and the second section is the final assembly and packaging process. The Agency believes that the metal finishing requirements contained in part 433 only cover the process after wafer fabrication which is used to deposit a layer of metal onto the surface of the wafer to provide contact points for final assembly.