NAS Semiconductor Device Modeling Workshop



Description:    Advanced semiconductor technology is the base technology
                for all high performance computing, including the
                workstations and highly parallel supercomputers that NASA
                relies on for aeronautics, environmental modeling, and
                space science applications. Because of the exponentially
                increasing complexity of these devices, computational
                modeling and simulation is now an essential part of their
                design, analysis, and validation. Even now, some of these
                simulations press the limits of available engineering
                workstations. As we look to the future, 3D simulation of
                physical effects that have been ignored in the past, will
                increase computational costs.

                Highly parallel computers provide an attractive alternative
                for such simulations, but progress in this area has been
                hampered due to lack of access to highly parallel systems,
                lack of expertise in parallel computing, and the reliance
                on software from small third-party vendors.

                In order to promote progress in this arena, the Numerical
                Aerodynamic Simulation (NAS) Program at NASA Ames Research
                Center is hosting this workshop on high performance
                computing in semiconductor device modeling. Topics to be
                covered will include:

                Simulation of fundamental physical effects
                Device and process simulation (TCAD)
                Circuit simulation
                CPU logic modeling and validation
                Parallel computing techniques
                Future computational requirements

                Participants will include scientists from academia,
                semiconductor manufacturers, and software vendors.
                Discussion sessions will explore possibilities for
                joint research work in this area involving NASA
                scientists and computing facilities.

                Please direct technical questions to:
                Subhash Saini, saini@nas.nasa.gov, (415) 604-4343.

                All other questions, contact:
                Marcia Redmond, redmond@nas.nasa.gov, (415) 604-4373.

Dates/Time:     Dates: March 28-29, 1996           Time: 8:30am - 5:30pm

Location:       NASA Ames Research Center
                (Subject to change to an off-site location near Ames;
                See the WWW for updates)

Registration:   Advance registration is required. There is no fee for
                this workshop. Registration deadline for non-U.S. citizens
                (without Green Card) is Tuesday, March 5.

                Registration deadline for U.S. citizens and non-U.S.
                citizens (with Green Card) is Friday, March 15.

                Contact: Marcia Redmond, (415) 604-4373, redmond@nas.nasa.gov

                Note:  Check the World Wide Web at
                http://www.nas.nasa.gov/NAS/Training
                for updates on speakers, possible location
                change, local hotel information, agenda
                (when available), etc.


                Confirmed Invited Speakers and Talk Titles (as of 2/29)

                Anirudh Devgan, IBM
                "Fast Circuit Simulation Techniques: Theory and Practice"

                Tomas Diaz de la Rubia, Lawrence Livermore National Lab
                "Atomic Scale Modeling of Ion Implantation and
                Dopant Diffusion in Silicon"

                Robert Dutton, Stanford University
                "Challenges in Computational Prototyping of Deep
                Sub-micron Integrated Circuit Technology"

                David Ferry, Arizona State University
                "Modeling in the Sub-0.07 Micron Gate Length Regime"

                Ronald Goossens, National Semiconductor
                "Parallelization of Large-scale Semiconductor
                Device Simulator"

                Bruce Kim, Sun Microelectronics
                "Power and Clock Distribution for the UltraSPARC-II
                Processor"

                Francisco Leon, Intel Supercomputers
                "Modeling and Simulation Issues in Next Generation
                IC Development"

                Anupam Madhukar, University of California (Berkeley)
                (TBD)

                Dev Malladi, Sun Microelectronics
                "Design and Productization of a High Performance
                PBGA Package for UltraSPARC-I Processor"

                Vladimir Mitin, Wayne State University
                "Heat Dissipation from Quantum Structures"

                Vijay Naik, IBM
                "Scalability of Sparse Solvers in the Context
                of Semiconductor Device Simulation Applications"

                Andrew Neureuther, University of California (Berkeley)
                (TBD)

                Mark Pinto, AT&T
                (TBD)

                L.R. Ram-Mohan, Worcester Polytechnic Institute
                "Computational Issues in the Design of Wavefunction-
                engineered Quantum Semiconductor Devices"

                Umberto Ravailoi, University of Illinois (Urbana)
                "Large-scale Application Issues for Full Band
                Monte Carlo Simulation of Semiconductor Devices"

                James Sethian, Lawrence Berkeley National Laboratory
                "Level Set Methods for Etching, Deposition,
                and Photolithography Development"

                Harsh Sharangpani, Intel Microprocessor Products
                (TBD)

                Henry Sheng, University of California (Berkeley)
                "Parallel and Distributed Computing for Monte
                Carlo Device Simulation"

                Ting-wei Tang, Massachusetts/Amherst University
                "General Hydrodynamic Equation Solver and its
                Computational Challenges"

                Zhiping Yu, Hewlett-Packard/Stanford University
                "Device Characterization and Simulation of
                Sub-quarter Micron MOSFETs Including Quantum
                Mechanical Correction"


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Registration for Semiconductor Device Modeling Workshop March 28-29, 1996.

Name_________________________________________________________________

Organization____________________________________________________________

Street Address___________________________________________________________

City______________________State_____

Zip/Mail Code________Country____________

Phone_______________Fax Number_______________

___U.S. Citizen ___Permanent Resident with Green Card

******************************************************************

___Foreign National
(non-United States Citizen). Must complete the following information:

Passport number______________

Name as it appears on passport______________________________

Date issued_______Date expires________Place issued__________

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Registration deadline for non-U.S. citizens without Green Card is
March 5.

Registration deadline for U.S. citizens and non-U.S. citizens with
Green Card is March 15, 1996.