Optically transparent, wide band gap metal oxide semiconductors are a promising candidate for large area flexible electronics. Because most commercially available flexible substrates, particularly polymer substrates, cannot withstand the high temperature processing (>400°C) required for traditional silicon device fabrication, the development of new materials and devices that can be processed at low temperatures in a scalable manner is needed. Metal oxide semiconductors have been demonstrated to retain high carrier mobilities even in the disordered, amorphous state obtained when processed at near-room temperatures ^{[1] [2]} . Compared to amorphous silicon field effect transistors (FETs), which are the dominant technology used in display backplanes, metal-oxide-based FETs have been demonstrated with higher charge carrier mobilities, higher current densities, and faster response performance ^{[3] [4]} .

It has been shown both in simulation and by experiment that FET threshold voltage (V_T) can be modified simply by changing the channel layer thickness, without requiring the additional complexity of multiple channel materials or different dopings. In this project we have developed a low temperature (~100°C), scalable lithographic process for top-gate, bottom-contact amorphous metal oxide-based FETs using parylene, a room temperature-deposited CVD polymer, as gate dielectric. Figure 1 shows a micrograph of an array of FETs fabricated with different channel lengths. The baseline process was extended to enable the integration of FETs with different threshold voltages on the same substrate. The availability of FETs with different threshold voltages enables the implementation of enhancement/depletion (E/D) logic circuits that have faster speeds and smaller device areas than single-V_T topologies. Using the two-V_T lithographic process, we fabricated and characterized integrated E/D inverters and ring oscillators that operate rail-to-rail at supply voltages as low as V_DD = 3V. An example inverter characteristic is plotted in Figure 2. These results demonstrate the potential for low V_DD metal oxide-based integrated circuits fabricated in a low temperature budget, fully lithographic process for large area electronics.

1. K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, “Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors,” Nature, vol. 432, pp. 488-492, Nov. 2004.
2. J. Robertson, “Disorder and instability processes in amorphous conducting oxides,” Physica Status Solidi B-Basic Solid State Physics, vol. 245, pp. 1026-1032, June 2008.
3. R. L. Hoffman, B. J. Norris, and J. F. Wager, “ZnO-based transparent thin-film transistors,” Applied Physics Letters, vol. 82, pp. 733-735, Feb. 2003.
4. E. Fortunato, P. Barquinha, G. Goncalves, L. Pereira, and R. Martins, “High mobility and low threshold voltage transparent thin film transistors based on amorphous indium zinc oxide semiconductors,” Solid-State Electronics, vol. 52, pp. 443-448, Mar. 2008.

Organic semiconductor-based devices can easily be scaled to large areas and fabricated on flexible, elastic, and non-planar surfaces at low temperatures. These properties give rise to a myriad of applications from printable and flexible circuits, displays, and solar cells to artificial skin, neurons, and other biosensors; unattainable with traditional silicon electronics technologies ^[1] .

To enable new, exciting applications, a low voltage circuit technology is being developed. The device of interest is the pentacene-based organic thin-film transistor (OTFT). Currently, pentacene shows the most promise as an organic semiconductor given its relatively high carrier mobility and chemical stability. Delocalized π-bonded electrons enable p-type semiconducting behavior in pentacene ^[1] . To realize organic semiconductor-based devices as a pervasive complement to Si CMOS devices, the electrical performance of organic semiconductor devices must improve. This requirement demands that the operating voltage must reduce and carrier mobility increase while the device maintains a high current and on-current to off-current ratio, all of which must be reproducible. Ultimately, these device parameters are related to the semiconductor, the insulator, and the semiconductor/insulator interface quality (grain size, growth modes, material phases, interface states, trapped charges, roughness, etc.).

Insulator and semiconductor engineering are being explored as a means to improve performance and illustrate the potential of this technology for large area nanoelectronics. Conventional methods of device fabrication have been used to address performance issues with limited success. In this work, initial efforts will concentrate on engineering the gate insulator by using a high dielectric constant material. Specifically, BZN (Bi_1.5Zn₁ Nb_1.5O₇) is a paraelectric pyrochlore system that boasts a high dielectric constant, low dielectric loss, and low co-firing temperature, making it a viable insulator for improving OTFT performance and enabling advanced circuit design ^[2] . The performance of this BZN compared to parylene as an insulator is illustrated in Figures 1 and 2. Later phases of this work will focus on engineering the semiconductor deposition. Enhancements to standard evaporative deposition techniques will be explored by in situ coupling of new forms of energy to control pentacene thin-film morphology and defects.

1. M. Kitamura and Y. Arakawa, “Pentacene-based organic field-effect transistors,” Journal of Physics-Condensed Matter, vol. 20, May 2008.
2. Y. Choi, I. D. Kim, H. L. Tuller, and A. I. Akinwande, “Low-voltage organic transistors and depletion-load inverters with high-K pyrochlore BZN gate dielectric on polymer substrate,” IEEE Transactions on Electron Devices, vol. 52, pp. 2819-2824, Dec. 2005.

In today’s large systems-on-a-chip, communication infrastructure such as high-speed I/Os consumes a significant portion of power, limiting the amount left for useful computation ^[1] . The conflicting bandwidth and power scaling requirements have stimulated vigorous research activities resulting in significant improvements in link energy-efficiency ^{[2] [3]} . These improvements in energy-efficiency have focused on the most dominant sub-systems, such as the clocking and signaling transmit‑receive chain. To that end, voltage-mode (VM) drivers have been introduced instead of current-mode (CM) drivers to improve the energy-efficiency of the transmitter ^{[2] [3]} . However, these VM drivers suffer from a power penalty when used to implement a transmit pre-emphasis filter ^[2] , which is particularly well suited for asymmetric-complexity link channel applications such as memory interfaces ^[4] and lossy channels with long intersymbol-interference (ISI) tails such as cables or silicon carriers ^[5] .

In this work, we show that the power penalty incurred by the traditional driver topologies can be tied to the channel impedance matching constraints. Analysis reveals that power-efficiency improvements over the VM transmit-equalization scheme must come from the controlled relaxation of impedance matching constraints on common‑mode and/or differential‑mode matching. One design that makes such a tradeoff, with frequency-selective common‑mode matching for improved power efficiency, appears in ^[6] . Going a step further, we re-examine the benefits of the static differential impedance matching, and analyze the possible tradeoffs if this constraint is removed, showing that the most efficient driver topology is based on dynamic resistance-modulation (RM) of transmitter impedance.

A test chip fabricated in a 90-nm CMOS process shows relatively small signal degradation from dynamic modulation of driver output impedance over a variety of 20” backplanes at 4 Gb/s, with energy-efficiency of  2pJ/bit at 100 mV of receiver eye, in Figure 1. Despite the signal degradation due to impedance mismatch in its operation, the RM driver compares favorably with the traditional driver topologies (CM and different forms of VM driver) in terms of power efficiency, Figure 2, while allowing for a very compact, fully-digital, implementation.

1. J. L. Shin, K. Tam, D. Huang, B. Petrick, H. Pham, C. Hwang, H. Li, A. Smith, T. Johnson, and F. Schumacher, “A 40nm 16-core 128-thread CMT SPARC SoC processor,” IEEE Journal of Solid State Circuits, vol. 46, p. 131–144, 2011.
2. H. Hatamkhani and R. Drost, “A 10-mW 3.6-Gbps I/O transmitter,” 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408), 2003, pp. 97-98.
3. J. Poulton, R. Palmer, A. Fuller, T. Greer, J. Eyles, W. Dally, M. Horowitz, I. Rambus, and C. Hill, “A 14-mW 6.25-Gb/s transceiver in 90-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 42, p. 2745–2757, 2007.
4. K. Chang, H. Lee, J.-H. Chun, T. Wu, T. J. Chin, K. Kaviani, J. Shen, X. Shi, W. Beyene, Y. Frans, B. Leibowitz, N. Nguyen, F. Quan, J. Zerbe, R. Perego, F. Assaderaghi, E. C. Real, and L. Altos, “A 16Gb/s/link, 64GB/s bidirectional asymmetric memory interface cell,” 2008 IEEE Symposium on VLSI Circuits, June 2008, pp. 126-127.
5. B. Kim, Y. Liu, T. O. Dickson, J. F. Bulzacchelli, and D. J. Friedman, “A 10-Gb/s compact low-power serial I/O with DFE-IIR equalization in 65-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3526–3538, Dec. 2009.
6. W. D. Dettloff, J C. Eble, L. Luo, P. Kumar, F. Heaton, T. Stone, and B. Daly, “A 32mW 7.4 Gb/s protocol-agile source-series-terminated transmitter in 45nm CMOS SOI,” Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, IEEE, pp. 370–371.

Power gating has become ubiquitous in ICs to reduce the power consumed by inactive CMOS logic circuits. However, the finite I_on/I_off ratio of MOSFET power gates limits their ability to reduce off-state leakage. In contrast, as described in ^{[1] [2]} , micro-electro-mechanical- (MEMS-) based power gates that mechanically make or break electrical contact can completely eliminate off-state leakage (Figure 1). The leakage benefits of MEMS-based power gates may be outweighed by increased switching energy and voltage droop due to relatively large device dimensions and/or operating voltages and on-state resistance. A simple analysis is presented to predict the conditions under which electrostatically-actuated MEM relays can achieve energy savings over MOSFETs for power gates ^[3] . This analysis shows that even in their current state of technology  (~100-μm device pitch), MEM relays can provide energy-reduction benefits over MOSFET power gates for off-periods > 500 μs. With relays scaled to current mass-produced MEMS device dimensions (~ 20 μm), the minimum off-period for energy-reduction benefit reduces to 10 µs.

Relay reliability is improved by the use of hard metals, which results in relatively high contact resistance. For a given relay size, this resistance limits the current density that an array of relay power gates can deliver while maintaining the optimal voltage drop. Current relays can deliver up to ~1 mA/mm² current density. However, power gates built from moderately scaled relays would support > 10-100 mA/mm² and would still fit into the same area as the CMOS chip they are driving. The relays could therefore be post-fabricated on top of the chip or integrated into the backend metallization layers with no penalty in the overall die area.

To experimentally demonstrate the feasibility of power-gating with current relay technology, we applied MEM relay power gating to a 90-nm CMOS chip operating at VDD = 0.6-1 V (Ion = 10-25 µA). Figure 2 illustrates the waveforms of the MEM relay power-gating this chip with MEM gate voltages V_G swinging between 5 and 7 V, with the inset indicating the chip’s correct I/O activity during T_on.

1. H. Kam, T.K. Liu, E. Alon, M. Horowitz “Circuit level requirements for MOSFET replacement devices,” in IEDM Tech. Dig. 2008.
2. F. Chen, M. Spencer, R. Nathanael, C. Wang, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J. Jeon, T.K. Liu, D. Markovic, V. Stojanovic, E. Alon “Demonstration of integrated micro-electro-mechanical switch circuits for VLSI applications,” in International Solid-State Circuits Conference (ISSCC Tech. Dig.), pp. 150-151, Feb. 2010.
3. H. Fariborzi, M. Spencer, V. Karkare, J. Jeon, R. Nathanael, C. Wang, F. Chen, H. Kam, V. Pott, T.K. Liu, E. Alon, V. Stojanovic, D. Markovic,  “Analysis and demonstration of MEM-relay power gating,” in IEEE Custom Integrated Circuits Conference (CICC), 2010

Implantable medical sensors are an emerging application area that exemplifies the stringent energy constraints imposed on wireless sensor circuits. In typical circuit blocks used for medical monitoring, the cost to wirelessly transmit data is orders of magnitude greater than for any other function. State-of-the-art radio transmitters exhibit energy-efficiencies in the nJ/bit range while every other component consumes at most only 10’s of pJ/bit. This cost disparity suggests that some data reduction strategy at the sensor node should be employed to minimize the energy cost of the system. Existing strategies for implementing integrated data compression or filtering solutions under these constraints largely revolve around detecting and extracting specific signal data ^{[1] [2] [3]} . However, the filtered data often contains limited information. For these signal processing strategies, there is a tradeoff between data reduction, robustness, implementation cost, and the granularity of information captured. In each case, the goal is to minimize the number of bits transmitted (to minimize the average radio power) while reliably preserving the signal information at a minimum implementation cost.

In this work, we introduce the design and implementation of a sensor compression architecture (Figure 1) based on the theory of compressed sensing (CS) ^[4] that offers an improved set of tradeoffs toward achieving this goal. A CS-based sensor system combines the positive qualities of existing data acquisition and compression systems: it provides a flexible and general interface like an analog-to-digital converter (ADC) yet still enables data compression proportional to the signal information content, which is consistent with the performance of source coding. For wireless sensor applications, this combination of characteristics is particularly attractive as it would enable a single hardware interface across many applications while simultaneously addressing the energy cost of the wireless telemetry. This approach reduces the average radio power by exploiting signal sparseness to encode the data at a high compression factor (>10x) while enabling a faithful reconstruction of the entire original signal. An efficient implementation of the CS encoder and encoder matrix generation (Figure 2) is realized and demonstrated in a 90-nm CMOS process and consumes 1.9 µW at 0.6 V and 20 kS/s ^[5] .

1. R. Harrison, P. Watkins, R. Kier, R. Lovejoy, D. Black, B. Greger, and F. Solzbacher, “A low-power integrated circuit for a wireless 100-electrode neural recording system,” IEEE Journal of Solid-State Circuits, vol. 42, pp. 123-133, 2007.
2. R. Olsson and K. Wise, “A three-dimensional neural recording microsystem with implantable data compression circuitry,” IEEE Journal of Solid-State Circuits, vol. 40, pp. 2796-2804, 2005.
3. N. Verma, A. Shoeb, J. Bohorquez, J. Dawson, J. Guttag, and A.P. Chandrakasan, “A micro-power EEG acquisition SoC with integrated feature extraction processor for a chronic seizure detection system,” IEEE Journal of Solid-State Circuits, vol. 45, pp. 804-816, 2010.
4. D. Donoho, “Compressed sensing,” IEEE Transactions on Information Theory, vol. 52, pp. 1289–1306, 2006.
5. F. Chen, A.P. Chandrakasan, and V. Stojanovic, “A Signal-agnostic compressed sensing acquisition system for wireless and implantable sensors,” presented at IEEE Custom Integrated Circuits Conference, San Jose, CA, 2010.

With the escalating costs of hospital visits, clinicians are opting to use at-home monitoring devices to diagnose patients.  Current ECG Holter monitoring devices typically have 24-48 hour memory and battery capacity ^[1] .  With many patients experiencing intermittent heart problems that can occur once every week or month, the Holter monitor is not a good solution; an event recorder or loop recorder is required ^[2] .  However, each of these recorders can save only up to a few minutes of ECG recordings.  This constraint leads to the loss of most of the data, which could be very important in alerting the user to the onset of future episodes.  Therefore, we have developed a Holter monitor prototype with the goal of battery and memory capacity of two weeks.  Figure 1 shows a block diagram of the system.

We based the long-term monitor prototype around a Texas Instruments MSP430 low-power microcontroller that enables high computing power with very low power consumption.  The prototype monitor is mounted on standard 3M 2560 Red Dot electrodes and fabricated on a flexible PCB substrate.  Mounting the PCB directly on the electrodes improves the SNR by an estimated 40 dB compared to using wired leads ^[3] .  The monitor is “L”-shaped with rounded corners and placed on the patient’s chest (Figure 2).  The “L” shape enables several different ECG vectors to be recorded, depending on what the cardiologist wants to observe.  The monitor has 1 GBit of FLASH memory, which is enough to store 6 days of data sampled at 250 Hz continuously without compression.  Total power consumption of the system is approximately 2 mW.

1. D. Jabaudon, J. Sztajzel, K. Sievert, T. Landis, and R. Sztajzel, “Usefulness of ambulatory 7-day ECG monitoring for the detection of atrial fibrillation and flutter after acute stroke and transient ischemic attack,” Stroke, J. Amer. Heart Assoc., vol. 35, pp. 1647–1651, May 2004.
2. M. A. Rockx, J. S. Hoch, G. J. Klein, R. Yee, A. C. Skanes, L. J. Gula, and A. D. Krahn, “Is ambulatory monitoring for “Community-acquired” syncope economically attractive? A cost-effective analysis of a randomized trial of external loop recorders versus Holter monitoring,” AHJ 150(5), pp. e1.1065 – e5.1075, Nov. 2005.
3. A. Searle and L. Kirkup, “A direct comparison of wet, dry and insulating bioelectric recording electrodes,” Physiol. Meas., vol. 21, pp. 271-283, 2000.

Intracranial pressure (ICP) is a key factor in monitoring a patient’s cerebrovascular state.  However, current ICP measurement modalities are highly invasive, relying on surgical penetration of the skull.  Recent developments in model-based physiology allow ICP to be estimated using arterial blood pressure and cerebral blood flow velocity (CBFV) measurements ^[1] .  CBFV can be obtained non-invasively using transcranial Doppler (TCD) ultrasonography, but requires bulky capital equipment and an expert operator to manually focus the ultrasound beam on a particular intracranial blood vessel.  Therefore, TCD measurements of CBFV are currently restricted to clinical environments in which such technology and expertise are available (typically neurocritical care units).

This project seeks to develop a low-power, miniaturized TCD ultrasonography system for measuring CBFV in the middle cerebral artery (MCA) in support of continuous monitoring of ICP.  The MCA is typically about 3 mm in diameter and is insonated through the temporal bony window at a distance of 40 to 60 mm from the ultrasonic transducer array.  These anatomic considerations place significant constraints on the focal length and spatial resolution requirements of the transducer array.  Adjusting the transmit amplitude and phase of each element in the 2D transducer array via a digital beamformer and high voltage (HV) pulser achieves electronic beam steering in three spatial dimensions.  Figure 1 shows relative acoustic power density for a 15° off-axis focus using a 2D transducer array with electronic beam steering.

Development of a beam steering algorithm will allow for autonomous location of the MCA, eliminating the need for a skilled operator. TCD ultrasonography focusing is further complicated by the highly non-homogenous acoustic propagating medium (i.e., presence of high-density cranium).   This issue can be mitigated, however, using calibration methods ^[2] . An HV multiplexer (MUX) is utilized so that a single transmit/receive (T/R) channel can connect to multiple transducer elements and thus greatly reduce the necessary electronics and power requirements.  This system architecture, as illustrated in Figure 2, will allow for a self-contained system for continuous CBFV measurement in a low-power and wearable form-factor.

1. F. M. Kashif, T. Heldt, and G. C. Verghese. “Model-based estimation of intracranial pressure and cerebrovascular autoregulation,” Computers in Cardiology, vol. 35, pp. 369-372, Sep. 2008.
2. G.T. Clement and K. Hynynen, “A non-invasive method for focusing ultrasound through the human skull,” Physics in Medicine and Biology, vol. 47, pp. 1219-1236, Apr. 2002.

Vital signs such as heart rate, blood pressure, blood oxygenation, cardiac output, and respiratory rate are necessary in determining the overall health of a patient.  Continuous monitoring of these vital signs can help assess the wearer’s overall state of health and identify risks for cardiovascular diseases ^[1] .

We propose the site behind the ear as a location for an integrated wearable vital signs monitor ^[2] . This location offers physiological signals such as the electrocardiogram (ECG), the photoplethysmogram (PPG), and the head ballistocardiogram (hBCG). The ECG measures the electrical activity from the heart and offers information such as continuous heart rate, blood pressure (when coupled with PPG or hBCG), and respiratory rate. The PPG measures the blood volume and color under the skin using optical illumination. The PPG offers information such as continuous heart rate and blood oxygenation. The hBCG measures the head’s mechanical reaction to the blood expelled by the heart and offers information about continuous heart rate, cardiac output, and respiratory rate.

A simultaneous measurement of ECG, PPG, and hBCG is shown in Figure 1. Using the peak timing data from ECG, PPG, and hBCG, blood pressure can be estimated. Figure 2 compares the estimated blood pressure with a commercial blood pressure measurement during a Valsalva breath-hold maneuver.

To make the monitor wearable, the electrodes must be small, comfortable, and gel-less to avoid skin irritation. We use 1-cm² capacitive and dry electrodes made of wearable fabric materials. The device is designed to use the ear as a discreet and a natural anchor that reduces device visibility and the need for skin adhesives.

1. S. D. Pierdomenico, M. Di Nicola, A. L. Esposito, R. Di Mascio, E. Ballone, D. Lapenna, F. Cuccurullo, “Prognostic value of different indices of blood pressure variability in hypertensive patients,” American Journal of Hypertension, vol. 22(8), pp. 842-847, June 2009.
2. D. He, E. S. Winokur, T. Heldt, C. G. Sodini, “The ear as a location for wearable vital signs monitoring,” Proc. of the IEEE Engineering in Medicine and Biology Conference, Sept. 2010, pp. 6389-6392.

Figure 1: Simplified system block diagram.

Epilepsy is a common chronic neurological disorder that affects about 1% of the world population ^[1] . It is characterized by repeated seizures, which are caused by an abnormal neuronal firing rate of the affected brain area. One way to detect a seizure is through an electroencephalogram (EEG), which is the recording of the electrical activity produced by the firing of neurons in the brain. Continuous EEG recording is extremely important for patients with epilepsy because doctors cannot only track the number of seizures the patient has, but also have access to the recordings during the attacks which allows doctors to determine the efficacy of the treatment.

The most common EEG recording place is at the scalp; however, it can also be obtained at the skull (subdermal) or at the brain (subdural). Continuous EEG recordings through measurements at the scalp require that the patient wears an external medical device at all times, which can be extremely inconvenient. One way to solve this problem is to implant the medical device. A subdural EEG implant would require a very complex surgery, so we have decided to do a subdermal EEG and avoid such complications. Our minimally invasive implant will be placed between the scalp and the skull behind the right ear, and the electrodes will run to the front part of the skull.

Our system consists of 2 EEG channels sampled at approximately 250 Hz with a 12-bit resolution. Figure 1 shows the simplified system block diagram.

1. W. C. Stacey and B. Litt, “Technology insight: neuroengineering and epilepsy – designing devices for seizure control,” Nature Clinical Practice Neurology, vol. 4, pp. 190-201, 2008.

The Capacitive Micromachined Ultrasound Transducer (CMUT) is an alternative to traditional piezoelectric transducers. The CMUT technology provides an opportunity for highly integrated ultrasound-imaging system solutions because of its CMOS compatibility, ease of large array fabrication, and improved bandwidth and sensitivity performance ^[1] .

This project aims to provide a highly flexible platform for 3D ultrasound imaging. Figure 1 presents the system architecture. The CMUT device is flip-chip bonded to the supporting electronic circuits, which eliminates the cables that are usually required by traditional systems between the piezoelectric transducers and circuits. As a result, the channel count of the imaging system is increased and the capacitive loading due to cables is greatly reduced.

The first prototype chip of the transmitter and receiver analog front-end for a 1D CMUT array is fabricated and is under testing. The block diagram of the implemented chip is shown in Figure 2. It contains four channels of independent transmitters and receiver chains. External control can be implemented for beamforming and Time-Gain Compensation (TGC). In each channel, the transmitter generates high voltage electric pulses to drive the CMUT device. A 3-level pulse shaping transmitter is designed to increase the transmitted signal power within the transducer bandwidth. The design uses MOS high voltage transistors for a pulse magnitude as large as 32 Vpp. The pulse frequency is programmable between 1~10 MHz and the pulse duration is programmable between about 0.5~20 us.

On the receiver side, a Low Noise Amplifier (LNA) implemented with a trans-impedance amplifier interfaces to the CMUT. The LNA is optimized for noise, power, and bandwidth trade-offs. The LNA can also be switched from “on” and “off” within 5 us. This switching saves system power when LNA is not needed. A Variable Gain Amplifier (VGA) follows the LNA to realize the Time-Gain Compensation function. Instead of a linear TGC profile, this VGA implements the TGC in a low power way, with discrete gain steps to compensate signal attenuation with coarse resolution. The VGA consumes 300 uA, and the gain setting can be changed in 6 dB per step with a tunable range of about 54 dB.

The prototyped chip is 3 mm X 3 mm in size. The simulated performance shows that each receive channel consumes 18.1 mW in normal mode and 1.7 mW in sleep mode. The programmable Rx gain range is from 152 dB to 99 dB at 3 MHz, with gain steps of 6 dB per step. The Rx Bandwidth is 6.0 MHz and the Rx Noise Figure is 11.3 dB within the signal bandwidth. The Tx pulsing energy efficiency is 38.2 nJ / pulse for an assumed 60 pF load from one CMUT element.

1. O. Oralkan, “Acoustical imaging using capacitive micromachined ultrasonic transducer arrays: Devices, circuits, and systems,” Ph.D. dissertation, Stanford, Palo Alto, 2004.