GaN-based high electron mobility transistors (HEMTs) have great potential for high power/frequency applications due to their outstanding combination of large breakdown voltage and high electron velocity. Among the different possible nitride structures, InAlN/GaN heterostructures have attracted much attention recently because they enable an extremely high charge density with a thin barrier thickness ^[1] . With the use of these advantages, outstanding progress in the frequency performance of InAlN/GaN transistors has been recently achieved. Sun et al. reported a 55-nm gate length device with f_T of 205 GHz (f_max = 191 GHz) ^[2] and Lee et al. demonstrated a 30-nm gate length device with f_T of 245 GHz ^[3] .

In this study, we used an AlGaN back-barrier in InAlN/GaN HEMT structures for the first time and studied its impact on the DC and RF characteristics of these devices ^[4] . A maximum drain current of 1.49 A/mm is obtained at V_gs=2 V in the device with the back-barrier, about 27 % lower than that of the standard device (2.05 A/mm at V_gs=2 V). The smaller drain current in the device with the back-barrier mainly results from the lower sheet charge density and subsequent higher threshold voltage. However, the output conductance is significantly smaller in the device with the back-barrier, which shows an effective suppression of the  short-channel effects. In addition, in sub-100-nm-gate-length transistors, the back-barrier makes it possible to maintain a drain-induced barrier lowering (DIBL) near 50-60 mV/V while preventing the degradation of the subthreshold swing (SS). Thanks to the reduced short-channel effects, 65-nm-gate-length devices with a back-barrier showed an f_T of 210 GHz, which is higher than that of the standard device with the same gate length (195 GHz). Moreover, in a sub-30-nm-gate-length device with AlGaN back-barrier, an f_T of 270 GHz, the highest f_T ever reported in GaN transistors, was achieved.

1. J. Kuzmik, “Power electronics on InAlN/(In)GaN: Prospect for a record performance,” IEEE Electron Device Lett. vol. 22, no. 11, pp. 510-512, Nov. 2001.
2. H. Sun, A. R. Alt, H. Benedickter, E. Feltin, J.-F. Carlin, M. Gonschorek, N. Grandjean, and C. R. Bolognesi, “205-GHz (Al, In)N/GaN HEMTs,” IEEE Electron Device Lett., vol. 31, no. 9, pp. 957-959, Sep. 2010.
3. D. S. Lee, J. W. Chung, H. Wang, X. Gao, S. Guo, P. Fay, and T. Palacios, “245 GHz InAlN/GaN HEMTs with oxygen plasma treatment,”  IEEE Electron Device Lett., vol. 32, no.6, pp.755-757, Jun. 2011.
4. D. Lee, X. Gao, S. Guo, and T. Palacios, “InAlN/GaN HEMTs with AlGaN back-barriers,” IEEE Electron Device Lett., vol. 32, no. 5, pp.-617-619, May 2011.

Compact models describing the voltage-dependent terminal current and charges (or equivalently, capacitances) are essential for small-signal and transient circuit simulation.  In this work, we extend the virtual-source (VS)-based transport model ^[1] with a self-consistent channel charge model for quasi-ballistic or fully ballistic devices, when the gradual channel approximation (GCA) and the drift transport theory are no longer valid. From a parabolic channel potential profile approximation and current continuity boundary condition, we derive a voltage-dependent charge model that is self-consistent with the transport model in the ballistic regime. The extended VS model has been implemented in Verilog-A language. ^[2]

Devices operating in the ballistic regime in saturation have less channel charge than predicted by the drift-diffusion theories, which is in principle advantageous from the performance point of view.  The quasi-ballistic (QB) model predicts 61% and 58% fewer intrinsic channel charges than the saturation velocity model (Vsat) and non-saturation drift velocity model (NVsat), respectively (Figure 1).  The difference diminishes in the linear region or because the device essentially operates with low carrier velocity and a lot of scattering with low V_gs or V_ds.   It is also shown that the benefits of fast carrier transport in tight-pitch logic circuits diminish due to the presence of extrinsic charges, particularly at higher fan-outs. As shown in Figure 2, the stage delay of a 5-stage ring oscillator predicted by QB model is only 5% and 3% less than that by Vsat and Nsat models, respectively. However, for RF applications the benefit of quasi-ballisticity in Si or near-full ballisticity in III-V HEMTs calculated by the model can be significant.

1. A. Khakifirooz, O. Nayfeh, and D. Antoniadis, “A simple semiempirical short-channel MOSFET current-voltage model continuous across all regions of operation and employing only physical parameters,” IEEE Transactions on Electron Devices,, vol. 56, pp. 1674-1680, 2009.
2. L. Wei, O. Mysore, and D. Antoniadis, “Virtual-source based self-consistent charge and transport models for near-ballistic FETs,” to be submitted to 2011 International Electron Devices Meeting.

Superconducting nanowire single-photon detectors (SNSPDs) ^[1] perform single-photon counting in the near‑infrared with outstanding performance. The main limitations of standard SNSPDs, based on ~ 4-nm-thick, 100-nm-wide NbN nanowires, are: (1) fragility with respect to constrictions; and (2) substantially reduced sensitivity beyond 2 µm wavelength (λ). We developed SNSPDs based on ultra-narrow (30- to 10-nm-wide) superconducting nanowires ^[2] , which showed improved robustness to constrictions and higher sensitivity to near-infrared photons with respect to standard SNSPDs.

As shown in Figure 1, at λ = 1550 nm our 30 nm nanowire‑width SNSPDs could be biased far from the device critical current (I_C) with minimal loss in detection efficiency (η), so even heavily‑constricted devices could reach the same efficiency as constriction‑free ones.

As shown in Figure 2 a, varying λ from 700 to 2100 nm, the η vs bias current (I_B) curves of 30 nm nanowire‑width SNSPDs kept a sigmoidal shape, with the cut-off current (I_co, taken to be at the inflection point of the η vs I_B curves) increasing from 0.31 I_C to 0.41 I_C. For 90 nm nanowire‑width detectors (shown in Figure 2 b), I_co increased from 0.64 I_C at λ = 500 nm to 0.89 I_C at λ = 1400 nm. This behavior indicates that ultra-narrow-nanowire SNSPDs are more sensitive to low-energy photons than standard devices and suggests that their sensitivity may extend to mid-infrared wavelengths.

The MIT Lincoln Laboratory portion was sponsored by the Department of the Air Force under Air Force Contract #FA8721-05-C-0002. Opinions, interpretations, recommendations and conclusions are those of the authors and are not necessarily endorsed by the United States Government.

1. G. N. Gol’tsman, O. Okunev, G. Chulkova, A. Lipatov, A. Semenov, K. Smirnov, B. Voronov, A. Dzardanov, C. Williams, and R. Sobolewski, “Picosecond superconducting single-photon optical detector,” Applied Physics Letters, vol. 79, no. 6, pp. 705-707, 2001.
2. F. Marsili, F. Najafi, E. Dauler, X. Hu, M. Csete, R. Molnar, and K. Berggren, “Single-photon detectors based on ultra-narrow superconducting nanowires,” Nano Letters, vol. 11, no. 9, pp. 2048-2053, 2011.

The most common substrate for processing chemical vapor deposition (CVD) graphene and highly oriented pyrolytic graphite (HOPG) has been thermally grown silicon dioxide on top of silicon. Due to optical interference, monolayer and bilayers of graphene can be easily identified using a standard optical microscope ^[1] . Furthermore, graphene is capacitively coupled to the underlying silicon, allowing for rapid electrical characterization through substrate biasing. While this substrate has proven useful for probing carrier transport in graphene as well as for developing graphene processing technology, the parasitic capacitances associated with the underlying silicon limit high-frequency performance. In this work, we have explored fabrication of graphene on purely insulating substrates, specifically sapphire. Sapphire is a common substrate used for radio frequency (RF) applications due to its low conductivity. Furthermore, it is much cheaper than other insulating substrates such as SiC or diamond.

Through recent advances in improved ohmic processing using an oxidized aluminum capping layer, we are able to fabricate high-speed field effect transistors on both silicon dioxide and sapphire ^[2] . Figure 1 shows measured RF data for a device with gate length (L_g) = 2 µm and width (W) = 25 µm on each substrate. While RF performance of graphene on silicon is slightly better after de-embedding than that of the sample on sapphire, we attribute this discrepancy to non-optimized processing conditions, possibly due to the transfer anneal or fabrication problems on transparent substrates. Fortunately, we are still able to achieve an extrinsic f_t-L_g product of 14 GHz-µm on sapphire, which to our best knowledge is the highest reported extrinsic value on CVD graphene (Figure 2 ^{[3] [4] [5] [6] [7] [8]} ). In parallel, scanning photocurrent measurements of graphene on silicon dioxide show optical sensitivities of 0.4 mA/W for large-area devices (>375 µm²). Therefore, combining our results on sapphire with optical measurements should hopefully allow for large-area arrays of high-speed graphene photodetectors.

1. X. Wang, M. Zhao, and D. D. Nolte, “Optical contrast and clarity of graphene on an arbitrary substrate,” Applied Physics Letters, vol. 95, p. 081102, 2009.
2. A. Hsu, H. Wang, K. K. Kim, J. Kong, and T. Palacios, “Impact of graphene interface quality on contact resistance and RF device performance,” submitted for publication.
3. J. S. Moon, D. Curtis, M. Hu, D. Wong, C. McGuire, P. M. Campbell, G. Jernigan, J. L. Tedesco, B. VanMil, R. Myers-Ward, C. Eddy, Jr., and D. K. Gaskill, “Epitaxial-graphene RF field-effect transistors on Si-face 6H-SiC substrates,” Electron Device Letters, vol. 30, pp. 650, 2009.
4. Y. Wu, Y. Lin, A. A. Bol, K. A. Jenkins, F. Xia, D. B. Farmer, Y. Zhu, and P. Avouris, “High-frequency, scaled graphene transistors on diamond-like carbon,” Nature, vol. 472, p. 74, 2011.
5. Y. Lin, C. Dimitrakopoulos, K.A. Jenkins, D. B. Farmer, H.Y. Chiu, A. Grill and P. Avouris, “100-GHz Transistors from wafer-scale epitaxial graphene,” Science vol. 327, p. 662, 2010.
6. Y. Lin, K. A. Jenkins, A. Valdes-Garcia, J. P. Small, D. B. Farmer and P. Avouris, “Operation of graphene transistors at gigahertz frequencies,” Nano Lett., vol. 9, p. 422, 2009.
7. L. Liao, Y. C. Lin, M. Bao, R. Cheng, J. Bai, Y. Liu, Y. Qu, K. L. Wang, Y. Huang, and X. Duan, “High-speed graphene transistors with a self-aligned nanowire gate,” Nature, vol. 467, p. 305, 2010.
8. J. Plouchart, J. Kim, J. Gross, R. Trzcinski, and K. Wu, “Scalability of SOI CMOS technology and circuit to millimeter-wave performance,” presented at CSIC Symposium 2005.

Optically transparent, wide band gap metal oxide semiconductors are a promising candidate for large area flexible electronics. Because most commercially available flexible substrates, particularly polymer substrates, cannot withstand the high temperature processing (>400°C) required for traditional silicon device fabrication, the development of new materials and devices that can be processed at low temperatures in a scalable manner is needed. Metal oxide semiconductors have been demonstrated to retain high carrier mobilities even in the disordered, amorphous state obtained when processed at near-room temperatures ^{[1] [2]} . Compared to amorphous silicon field effect transistors (FETs), which are the dominant technology used in display backplanes, metal-oxide-based FETs have been demonstrated with higher charge carrier mobilities, higher current densities, and faster response performance ^{[3] [4]} .

It has been shown both in simulation and by experiment that FET threshold voltage (V_T) can be modified simply by changing the channel layer thickness, without requiring the additional complexity of multiple channel materials or different dopings. In this project we have developed a low temperature (~100°C), scalable lithographic process for top-gate, bottom-contact amorphous metal oxide-based FETs using parylene, a room temperature-deposited CVD polymer, as gate dielectric. Figure 1 shows a micrograph of an array of FETs fabricated with different channel lengths. The baseline process was extended to enable the integration of FETs with different threshold voltages on the same substrate. The availability of FETs with different threshold voltages enables the implementation of enhancement/depletion (E/D) logic circuits that have faster speeds and smaller device areas than single-V_T topologies. Using the two-V_T lithographic process, we fabricated and characterized integrated E/D inverters and ring oscillators that operate rail-to-rail at supply voltages as low as V_DD = 3V. An example inverter characteristic is plotted in Figure 2. These results demonstrate the potential for low V_DD metal oxide-based integrated circuits fabricated in a low temperature budget, fully lithographic process for large area electronics.

1. K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, “Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors,” Nature, vol. 432, pp. 488-492, Nov. 2004.
2. J. Robertson, “Disorder and instability processes in amorphous conducting oxides,” Physica Status Solidi B-Basic Solid State Physics, vol. 245, pp. 1026-1032, June 2008.
3. R. L. Hoffman, B. J. Norris, and J. F. Wager, “ZnO-based transparent thin-film transistors,” Applied Physics Letters, vol. 82, pp. 733-735, Feb. 2003.
4. E. Fortunato, P. Barquinha, G. Goncalves, L. Pereira, and R. Martins, “High mobility and low threshold voltage transparent thin film transistors based on amorphous indium zinc oxide semiconductors,” Solid-State Electronics, vol. 52, pp. 443-448, Mar. 2008.

A near-ultraviolet (UV) sensor based on zinc oxide (ZnO) nanowires (NWs) that is sensitive to photo excitation at or below 400-nm wavelength has been fabricated and characterized. The device uses a single optical lithography step, and the NWs are grown at a low temperature from solution. ZnO is a wide direct band gap (3.37 eV) semiconductor whose absorption edge is in the near-UV range, making it an ideal near-UV photodetector. This is the first reported ZnO NW near-UV sensor that is insensitive to visible light (visible blind) and fabricated using a low temperature solution process ^[1] . At a voltage bias of 1V across the device, a 29-fold increase in current is observed in comparison to dark current when the NWs are photo excited by 400-nm light-emitting diode (LED), 8.91 µA (photo excitation current) vs. 311 nA (dark current).

The fabrication of the near-UV sensor device is based on a single optical lithography step with no processing steps that exceed 100°C. The devices are compressed of a thin ZnO film with a metal cap. The sidewall of the ZnO film within the material stack acts as a seed for lateral growth of ZnO NWs. The metal cap restricts vertical growth of the NWs and doubles as the device electrodes. The symmetric devices have multiple electrode shapes and gaps between the electrodes ranging from 1-20 µm. The horizontally grown ZnO NWs bridge the gap between the two electrodes. The wires vary in length from 0.8 to 8.4 µm and diameter from 80 to 300 nm, depending on growth time. The result is a self-aligned ZnO NW ‘visible blind’ near-UV sensor that utilizes a low temperature process and a simple one-mask optical lithography step that can be integrated on a flexible substrate.

1. M. E. Swanwick, S. M.-L. Pfaendler, A. I. Akinwande, and A. J. Flewitt, “Near-ultraviolet sensor based on horizontal low temperature solution grown zinc oxide nanowires,” presented at 2010 MRS Fall Meeting, Boston, MA, Nov. 2010.

Organic semiconductor-based devices can easily be scaled to large areas and fabricated on flexible, elastic, and non-planar surfaces at low temperatures. These properties give rise to a myriad of applications from printable and flexible circuits, displays, and solar cells to artificial skin, neurons, and other biosensors; unattainable with traditional silicon electronics technologies ^[1] .

To enable new, exciting applications, a low voltage circuit technology is being developed. The device of interest is the pentacene-based organic thin-film transistor (OTFT). Currently, pentacene shows the most promise as an organic semiconductor given its relatively high carrier mobility and chemical stability. Delocalized π-bonded electrons enable p-type semiconducting behavior in pentacene ^[1] . To realize organic semiconductor-based devices as a pervasive complement to Si CMOS devices, the electrical performance of organic semiconductor devices must improve. This requirement demands that the operating voltage must reduce and carrier mobility increase while the device maintains a high current and on-current to off-current ratio, all of which must be reproducible. Ultimately, these device parameters are related to the semiconductor, the insulator, and the semiconductor/insulator interface quality (grain size, growth modes, material phases, interface states, trapped charges, roughness, etc.).

Insulator and semiconductor engineering are being explored as a means to improve performance and illustrate the potential of this technology for large area nanoelectronics. Conventional methods of device fabrication have been used to address performance issues with limited success. In this work, initial efforts will concentrate on engineering the gate insulator by using a high dielectric constant material. Specifically, BZN (Bi_1.5Zn₁ Nb_1.5O₇) is a paraelectric pyrochlore system that boasts a high dielectric constant, low dielectric loss, and low co-firing temperature, making it a viable insulator for improving OTFT performance and enabling advanced circuit design ^[2] . The performance of this BZN compared to parylene as an insulator is illustrated in Figures 1 and 2. Later phases of this work will focus on engineering the semiconductor deposition. Enhancements to standard evaporative deposition techniques will be explored by in situ coupling of new forms of energy to control pentacene thin-film morphology and defects.

1. M. Kitamura and Y. Arakawa, “Pentacene-based organic field-effect transistors,” Journal of Physics-Condensed Matter, vol. 20, May 2008.
2. Y. Choi, I. D. Kim, H. L. Tuller, and A. I. Akinwande, “Low-voltage organic transistors and depletion-load inverters with high-K pyrochlore BZN gate dielectric on polymer substrate,” IEEE Transactions on Electron Devices, vol. 52, pp. 2819-2824, Dec. 2005.

Field Emitter Arrays (FEAs) are excellent cold cathodes, but they have not found widespread adoption in demanding device applications because of several major challenges, including spatial/temporal current variations emanating from emitter tip radius distribution and the work function fluctuation. A consequence of tip radius variation is that the sharper emitters burn out from Joule heating before duller emitters turn on, reducing the current attainable from FEAs.

Addressing these challenges, groups have incorporated current limiting (ballasting) elements including large resistors ^[1] , diodes ^[2] , and MOSFETs ^[3] into FEAs, but none of these simultaneously provide high current, high emitter density, and high current density. Velasquez-Garcia et al. demonstrated silicon vertical ungated FETs integrated with FEAs, resulting in a Si tip on Si pillar structure ^[4] . The ungated FET has a current-source-like I-V characteristic, providing effective individual ballasting of emitters while allowing uniform and high current emission without thermal runaway ^[4] . To limit emission current, the device uses pinch-off and velocity saturation of carriers in a Si high aspect ratio channel. Their pillars have a diameter of 1 µm, height of 100 µm, and 10-µm pitch, resulting in a density of 10⁶ emitters/cm². However, a consequence of tip radius variation and ballasting is that the energy distribution of emitted electrons is larger when compared to un-ballasted FEAs.

To obtain FEAs with higher current densities, lower operating voltages, and reduced energy spread while retaining current uniformity, we expanded on previous work by scaling their tip on Si pillar structure. We developed vertical ungated FET current limiters 100 nm in diameter, 8 µm tall, and with 1-µm pitch, increasing the density to 10⁸ emitters/cm² (Figure 1). These devices demonstrate excellent current saturation of 15 pA / pillar with a linear conductance of 2.6×10^-10 S/pillar and an output conductance under 10^-13 S/pillar. The current saturates at a drain to source voltage under 0.2 V. These are the highest density, smallest diameter, and lowest operating voltage Si vertical ungated FETs ever reported.

1. P. Vaudaine and R. Meyer, “’Microtips’ fluorescent display,” IEDM Tech. Dig., 1991, pp. 197-200.
2. Y. Kobori and M. Tanaka, “Field emission cathode,” U.S. Patent 5 162 704, Feb. 5, 1992.
3. J. Itoh, T. Hirano, and S. Kanemaru, “Ultrastable emission from a metal–oxide–semiconductor field-effect transistor-structured Si emitter tip,” Applied Physics Letters, vol. 69, no. 11, pp. 1577–1578, 1996.
4. L. F. Velasquez-Garcia, S. A. Guerrera, Y. Niu, and A. I. Akinwande, “Uniform high-current cathodes using massive arrays of Si field emitters individually controlled by vertical Si ungated FETs – Part 1: Device design and simulation & Part 2: Device fabrication and characterization.” IEEE Trans. Electron Devices, vol. 58, no. 6, pp. 1775-1791, June 2011.

Figure 1: SEM, TEM, HR-TEM and SAED images of microsphere template InGaZnO3, illustrating a short range order of the spheres and amorphous phase of the sensor film.

Gas sensors are essential in the monitoring, control, and reduction of harmful emissions in the environment ^[1] .  Conductometric gas sensors based on semiconducting metal oxides are advantageous in many applications due to high sensitivity, manufacturability, and small size.  However, there are a number of drawbacks, including difficulty in control over the semiconductor/substrate interface, high power consumption, and reduced selectivity at high temperatures (300-400˚C) required for operation ^{[2] [3]} .  To address these challenges, chemical sensors comprising a wide array of material composition and morphology have been fabricated and investigated via high-throughput combinatorial test procedures.  A microsphere templating technique is employed in all device structures; it reduces the area of contact with underlying substrate and enhances interaction with the surrounding gases ^[4] .  Sensor performance has been characterized and optimized through controlled variation in the volume fraction of Pt nanoparticles that are co-deposited on the surface of SnO₂ and ZnO thin films.  In addition, novel sensors based on amorphous InGaZnO₄ have been investigated under a wide range of operating conditions and show promise for heightened sensitivity at reduced operating temperatures.  With a combination of rapid testing procedures and physical models of chemical and electronic processes involved in gas sensing, further advancements are anticipated in device sensitivity, selectivity, and response time.

1. F. Rock, N. Barsan, and U. Weimar ., “Electronic nose: Current status and future trends,” Chemical Reviews, vol. 108, no. 2, pp. 705-725, Jan. 2008.
2. K. J. Albert, N. S. Lewis, C.L. Schauer, G. A. Sotzing, S. E. Stitzel, T. P. Vaid, and D. R. Walt., “Cross-reactive chemical sensor arrays,” Chemical Reviews, vol. 100, no. 7, pp. 2595-2626, June 2000.
3. K. Wiesner, H. Knozinger,   M. Fleischer, H. Meixner, “Working mechanism of an ethanol filter for selective high-temperature methane gas sensors,” IEEE Sensors Journal, vol. 2, no. 4, pp. 354-359, Aug. 2002.
4. I. D. Kim, A. Rothschild, T.Hyodo, and H. L. Tuller,, “Microsphere templating as means of enhancing surface activity and gas sensitivity of CaCu₃Ti₄O₁₂ thin films,” Nano Letters, vol. 6, no. 2, pp. 193-198, Jan. 2006.

Capacitors have attracted considerable attention due to their potential as an energy buffer in a hybrid energy system.  Improvement of the capacitor performance has been achieved by various approaches, one of which is introducing high surface-to-volume ratio structures to increase the effective electrode area.  Therefore, fabrication of Si nanowire arrays and construction of capacitors based on these nanowires have been widely studied.  Metal-catalyzed etching (MCE) is a new process to fabricate silicon nanowire arrays by the combination of film patterning techniques and the wet chemical etching step. The MCE technique is more appreciable than others because of its room temperature processing condition, which makes it compatible with current standard silicon integrated circuit fabrication technology. In this process, patterned metal films are used to catalyze the etching of silicon at the metal-silicon interface in a mixed etching of hydrofluoric acid and hydrogen peroxide.

We have recently demonstrated the feasibility of using the MCE to fabricate Si nanowires to make nanocapacitors ^[1] . The fabrication process is described schematically in Figure 1. Interference lithography is used to make the anti-dot array pattern on the metal film, and the MCE process finally creates silicon wire arrays. Gold is then removed, and an oxide dielectric layer is grown in a tube furnace. Finally, electrodeposited nickel serves as the other electrode of the capacitor. We have demonstrated a factor of approximately 10 times improvement in the capacitance density over planar devices for nanocapacitors with a 200-nm period and 1.5-µm height.  Figure 2 shows the results of capacitance measurements for different period and height pillar height capacitors.  Further improvement of silicon nanowire capacitors can be achieved using wires with higher aspect ratios and smaller diameters and spacings.

1. S. W. Chang, J. Oh, S. T. Boles, and C. V. Thompson, “Fabrication of silicon nanopillar-based nanocapacitor arrays,” Applied Physics Letters, vol. 96, p. 153108, 2010.