MTL Annual Research Report 2011

1] at the same bias. When the penalty of static leakage power, which is proportional to Ioff, increases to assure the driving speed, i.e., Edyn/Etot decreases to be much less than 80%, the size of the weaker transistor should be increased to suppress the penalty." />

Figure 1: (a) Minimum energy per switch and the corresponding (b) Edyn/Etot for a circuit application, assuming static-CMOS logic, with a logic depth of 20 and activity factor of 0.01, at selected P/N ratios. The pMOS and nMOS transporting 10x and 1x current of the 11-nm projection device in [1] at the same bias. When the penalty of static leakage power, which is proportional to Ioff, increases to assure the driving speed, i.e., Edyn/Etot decreases to be much less than 80%, the size of the weaker transistor should be increased to suppress the penalty.

1. ref:1 [↩]