Figure 1

Figure 1: An array of metal oxide FETs with varying channel lengths fabricated in a low-temperature-budget (~100°C) process. The lithographic process enables integration of these FETs into large-area electronic circuits.

  • Contents

  • Faculty Profiles, Research Abstracts, and Research Centers

  • Tags

    Akintunde Akinwande Anantha Chandrakasan Brian Wardle Carlijn Mulder Carl Thompson Caroline Ross Charles Sodini Chih-Hao Chang CICS Clifton Fonstad Dana Weinstein Dimitri Antoniadis Duane Boning Eugene Fitzgerald Faraz Najafi Francesco Marsili George Barbastathis Hae-Seung Lee Harry Tuller Ichiro Masaki Jason Sussman Jeffrey Lang Jesus del Alamo Jing Kong Joel Dawson Joel Voldman Jongyoon Han Judy Hoyt Karen Gleason Karl Berggren Lan Wei Luca Daniel Luis Velásquez-García Marc Baldo Omar Mysore Philip Reusswig Rajeev Ram Sang-Gook Kim Sangeeta Bhatia Scott Manalis Sean Bishop Tomas Palacios Vitor Manfrinato Vladimir Bulovic Vladimir Stojanovic