Graduate Students

• G. Angelopoulos, Res. Asst., EECS (co-supervised with Prof. M. Medard)
• S. Bandyopadhyay, Res. Asst., EECS
• F. Chen, Res. Asst., EECS (co-supervised with Prof. V. Stojanovic)
• K. Chen, Res. Asst., EECS (co-supervised with Prof. C. Sodini)
• N. Desai, Res. Asst., EECS
• D. El-Damak, Res. Asst., EECS
• S. Ha, Res. Asst., EECS
• B. Lam, Res. Asst., EECS
• K-J. Lee, Res. Asst., EECS (co-supervised with Prof. J. Kong)
• S. Lee, Res. Asst., EECS (co-supervised with Prof. H. Lee)
• P. Mercier, Res. Asst., EECS
• P. Nadeau, Res. Asst., EECS
• A. Paidimarri, Res. Asst., EECS
• S. Park, Res. Asst., EECS (co-supervised with Prof. L. Peh)
• M. Qazi, Res. Asst., EECS
• R. Rithe, Res. Asst., EECS
• M. Sinangil, Res. Asst., EECS
• Y. Sinangil, Res. Asst., EECS
• M. Tikekar, Res. Asst., EECS
• M. Yip, Res. Asst., EECS

Postdoctoral Associates

• C-T Huang
• N. Ickes
• L. Wei

Visiting Scientists

• D. Buss (Texas Instruments)
• F.  Pappalardo (ST Microelectronics)
• Z. Ru (University of Twente)
• Prof. H-J Yoo (KAIST)
• Prof. J. Yoo (Masdar Institute)

Visiting and Undergraduate Students

• L. Yan (KAIST)
• R. Jin
• W. Zheng

Support Staff

• M. Flaherty, Senior Administrative Assistant

Publications

J.L. Bohorquez, M. Yip, A. P. Chandrakasan, J. L. Dawson, “A Biomedical Sensor Interface with a sinc Filter and Interference Cancellation,” IEEE Journal of Solid-State Circuits, vol. 46, no. 4, pp 746-756, April 2011.

M. Qazi,  M. E. Sinangil, A. P. Chandrakasan, “Challenges and Directions for Low-Voltage SRAM,” Design & Test of Computers, IEEE , vol.28, no.1, pp.32-43, Jan.-Feb. 2011.

M. Qazi, K. Stawiasz, L. Chang, A. P. Chandrakasan, “A 512kb 8T SRAM Macro Operating Down to 0.57V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45nm SOI CMOS,” IEEE Journal of Solid-State Circuits, vol. 46, no. 1, pp 85-96, Jan 2011.

Y.K. Ramadass, A. P. Chandrakasan, “A Battery-Less Thermoelectric Energy Harvesting Interface Circuit With 35mV Startup Voltage,” IEEE Journal of Solid-State Circuits, vol. 46, no. 1, pp 333-341, Jan 2011.

V. Sze, A. Chandrakasan, “A Highly Parallel and Scalable CABAC Decoder for Next Generation Video Coding,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 126-127, Feb 2011.

G. Gammie, N. Ickes, M. Sinangil, R. Rithe, J. Gu, A. Wang, H. Mair, S. Datla, B. Rong, S. Honnavara-Prasad, L. Ho, G. Baldwin, D. Buss, A. Chandrakasan, U. Ko, “A 28nm 0.6V Low-Power DSP for Mobile Applications,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 132-133, Feb 2011.

M. Yip, A. Chandrakasan, “A Resolution-Reconfigurable 5-to-10b 0.4V-to-1V Power Scalable SAR ADC,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 190-191, Feb 2011.

M. Qazi, M. Clinton, S. Bartling, A. Chandrakasan, “A Low-Voltage 1Mb FeRAM in 0.13um CMOS Featuring Time-to-Digital Sensing for Expanded Operating Margin in Scaled CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 208-209, Feb 2011.

M. Sinangil, H. Mair, A. Chandrakasan, “A 28nm High-Density 6T SRAM wth Optimized Peripheral-Assst Circuits for Operation Down to 0.6V,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 260-261, Feb 2011.

S. Bandyopadhyay, Y. K. Ramadass, A. Chandrakasan, “20uA to 100mA DC-DC Converter with 2.8 to 4.2V Battery Supply for Portable Applications in 45nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 386-387, Feb 2011.

R. Rithe, S. Chou, J. Gu, A. Wang, S. Datla, G. Gammie, D. Buss, A. Chandrakasan, “Cell Library Characterization at Low Voltage using Non-linear Operating Point Analysis of Local Variations,” International Conference on VLSI Design, Jan 2011.

Implantable medical sensors are an emerging application area that exemplifies the stringent energy constraints imposed on wireless sensor circuits. In typical circuit blocks used for medical monitoring, the cost to wirelessly transmit data is orders of magnitude greater than for any other function. State-of-the-art radio transmitters exhibit energy-efficiencies in the nJ/bit range while every other component consumes at most only 10’s of pJ/bit. This cost disparity suggests that some data reduction strategy at the sensor node should be employed to minimize the energy cost of the system. Existing strategies for implementing integrated data compression or filtering solutions under these constraints largely revolve around detecting and extracting specific signal data ^{[1] [2] [3]} . However, the filtered data often contains limited information. For these signal processing strategies, there is a tradeoff between data reduction, robustness, implementation cost, and the granularity of information captured. In each case, the goal is to minimize the number of bits transmitted (to minimize the average radio power) while reliably preserving the signal information at a minimum implementation cost.

In this work, we introduce the design and implementation of a sensor compression architecture (Figure 1) based on the theory of compressed sensing (CS) ^[4] that offers an improved set of tradeoffs toward achieving this goal. A CS-based sensor system combines the positive qualities of existing data acquisition and compression systems: it provides a flexible and general interface like an analog-to-digital converter (ADC) yet still enables data compression proportional to the signal information content, which is consistent with the performance of source coding. For wireless sensor applications, this combination of characteristics is particularly attractive as it would enable a single hardware interface across many applications while simultaneously addressing the energy cost of the wireless telemetry. This approach reduces the average radio power by exploiting signal sparseness to encode the data at a high compression factor (>10x) while enabling a faithful reconstruction of the entire original signal. An efficient implementation of the CS encoder and encoder matrix generation (Figure 2) is realized and demonstrated in a 90-nm CMOS process and consumes 1.9 µW at 0.6 V and 20 kS/s ^[5] .

1. R. Harrison, P. Watkins, R. Kier, R. Lovejoy, D. Black, B. Greger, and F. Solzbacher, “A low-power integrated circuit for a wireless 100-electrode neural recording system,” IEEE Journal of Solid-State Circuits, vol. 42, pp. 123-133, 2007.
2. R. Olsson and K. Wise, “A three-dimensional neural recording microsystem with implantable data compression circuitry,” IEEE Journal of Solid-State Circuits, vol. 40, pp. 2796-2804, 2005.
3. N. Verma, A. Shoeb, J. Bohorquez, J. Dawson, J. Guttag, and A.P. Chandrakasan, “A micro-power EEG acquisition SoC with integrated feature extraction processor for a chronic seizure detection system,” IEEE Journal of Solid-State Circuits, vol. 45, pp. 804-816, 2010.
4. D. Donoho, “Compressed sensing,” IEEE Transactions on Information Theory, vol. 52, pp. 1289–1306, 2006.
5. F. Chen, A.P. Chandrakasan, and V. Stojanovic, “A Signal-agnostic compressed sensing acquisition system for wireless and implantable sensors,” presented at IEEE Custom Integrated Circuits Conference, San Jose, CA, 2010.

The Capacitive Micromachined Ultrasound Transducer (CMUT) is an alternative to traditional piezoelectric transducers. The CMUT technology provides an opportunity for highly integrated ultrasound-imaging system solutions because of its CMOS compatibility, ease of large array fabrication, and improved bandwidth and sensitivity performance ^[1] .

This project aims to provide a highly flexible platform for 3D ultrasound imaging. Figure 1 presents the system architecture. The CMUT device is flip-chip bonded to the supporting electronic circuits, which eliminates the cables that are usually required by traditional systems between the piezoelectric transducers and circuits. As a result, the channel count of the imaging system is increased and the capacitive loading due to cables is greatly reduced.

The first prototype chip of the transmitter and receiver analog front-end for a 1D CMUT array is fabricated and is under testing. The block diagram of the implemented chip is shown in Figure 2. It contains four channels of independent transmitters and receiver chains. External control can be implemented for beamforming and Time-Gain Compensation (TGC). In each channel, the transmitter generates high voltage electric pulses to drive the CMUT device. A 3-level pulse shaping transmitter is designed to increase the transmitted signal power within the transducer bandwidth. The design uses MOS high voltage transistors for a pulse magnitude as large as 32 Vpp. The pulse frequency is programmable between 1~10 MHz and the pulse duration is programmable between about 0.5~20 us.

On the receiver side, a Low Noise Amplifier (LNA) implemented with a trans-impedance amplifier interfaces to the CMUT. The LNA is optimized for noise, power, and bandwidth trade-offs. The LNA can also be switched from “on” and “off” within 5 us. This switching saves system power when LNA is not needed. A Variable Gain Amplifier (VGA) follows the LNA to realize the Time-Gain Compensation function. Instead of a linear TGC profile, this VGA implements the TGC in a low power way, with discrete gain steps to compensate signal attenuation with coarse resolution. The VGA consumes 300 uA, and the gain setting can be changed in 6 dB per step with a tunable range of about 54 dB.

The prototyped chip is 3 mm X 3 mm in size. The simulated performance shows that each receive channel consumes 18.1 mW in normal mode and 1.7 mW in sleep mode. The programmable Rx gain range is from 152 dB to 99 dB at 3 MHz, with gain steps of 6 dB per step. The Rx Bandwidth is 6.0 MHz and the Rx Noise Figure is 11.3 dB within the signal bandwidth. The Tx pulsing energy efficiency is 38.2 nJ / pulse for an assumed 60 pF load from one CMUT element.

1. O. Oralkan, “Acoustical imaging using capacitive micromachined ultrasonic transducer arrays: Devices, circuits, and systems,” Ph.D. dissertation, Stanford, Palo Alto, 2004.

Designing on-chip networks optimized for a cache coherence protocol is critical for many-core processors to achieve peak efficiency in energy, latency, and throughput performance. Considering that advanced cache coherence protocols ^{[1] [2] [3]} count on a combination of multicasts, broadcasts, and direct requests, it is essential to optimize on-chip networks for one-to-many multicasts and broadcasts. In addition, since such bandwidth-hungry on-chip networks consume substantial energy in their data path, energy-efficient crossbar switches and links are required.

This work presents broadcast-optimized, low-swing signaling-based on-chip networks. The proposed on-chip networks feature (1) multicast buffer bypassing flow control, (2) a broadcast-optimized crossbar switch, and (3) low-swing signaling in the data path. The multicast bypassing scheme generates multiple lookahead signals, one corresponding to each output port out of which the flit forks. To maximize bypassing efficiency, output port requests of the incoming lookahead signals are prioritized over the requests of other flits buffered at the same input port. When the lookahead wins all of its output ports, the intermediate router sets up the bypass control signals that allow the flit to connect directly to the crossbar and link, instead of getting buffered. For the broadcast-optimized crossbar switch and low-swing signaling in the data path, a tri-state RSD-based crossbar is presented. The proposed low-swing crossbar features (1) an inherent power gating circuit, (2) higher bandwidth driven by linear-mode RSD, (3) a longer low-swing signaling data path from cross points to link RXs, (4) SOI-friendly circuit design, and (5) potential to be integrated into the CAD synthesis flow.

1. N. Agarwal, L.-S. Peh, and N. K. Jha, “In-network coherence filtering: snoopy coherence without broadcast,” IEEE/ACM International Symposium on Microarchitecture (MICRO), no. 42, pp.232-243, 2009.
2. P. Conway, N. Kalyanasundharam, G. Donley, K. Lepak, and B. Hughes, “Cache hierarchy and memory subsystem of the AMD Opteron processor,” IEEE/ACM International Symposium on Microarchitecture (MICRO), no. 30, pp. 16-29, 2010.
3. E. E. Bilir, R. M. Dickson, Y. Hu, M. Plakal, D. J. Sorin, M. D. Hill, and D. A. Wood, “Multicast snooping: A coherence method using a multicast address network,” IEEE/ACM International Symposium on Computer Architecture (ISCA), pp. 294-304, 1999.

Figure 1

Most current ultrasound imaging systems use piezoelectric materials for the ultrasound transducer. The recent development of micro-electromechanical systems (MEMS) allowed fabrication of capacitive micromachined ultrasound transducers (CMUTs).  A CMUT is a micromachined capacitor whose value changes according to the DC bias voltage or external pressure due to the physical deformation of the top plate by electrostatic force or external pressure. The major advantages of this transducer technology are the potential for integration with supporting electronic circuits, ease of fabrication, higher resolution due to small transducer size, and improved bandwidth and sensitivity ^[1] .

This project focuses on the front-end design of portable ultrasound systems using CMUTs. Figure 1 presents a conceptual block diagram of the system. Implementing an ADC at each channel input makes possible digital beam-forming in the receive (Rx) path, which enhances ultrasound image quality. To implement as many ADCs as the number of transducer channels, each ADC must consume as little power as possible, and each should be implemented in a small area. Considering the required performance, a zero-crossing-based (ZCB) pipelined ADC is a suitable architecture ^[2] .  For the first part of this project, a 50-MHz 12-bit ZCB pipelined ADC is designed. The highly digital implementation characteristic of the zero-crossing detection technique enables energy-efficient operation and voltage scaling. Supply voltage scaling based on the required sampling frequency and resolution provides constant energy efficiency over a wide range of sampling frequencies and resolutions.

Recently, a few 2D imaging systems using CMUT as ultrasound transducers have been reported, but they do not use real-time imaging ^[1] . The digital image processing block will be considered in the system level for real-time imaging.  After completing the 2D ultrasound image system using a 1D transducer, we will examine the feasibility of the 3D ultrasound image system using 2D transducers.

1. O. Oralkan, “Acoustical imaging using capacitive micromachined ultrasonic transducer arrays: Devices, circuits, and systems,” Ph.D. thesis, Stanford University, Palo Alto, CA, 2004.
2. L. Brooks and H.-S. Lee, “A zero-crossing-based 8b 200MS/s pipelined ADC,” IEEE International Solid-State Circuits Conference, 2007. Digest of Technical Papers, pp. 460-615.

As process technology scales, the importance of material and architectural innovation for interconnect performance will continue to increase. Graphene has attracted much interest as a replacement for copper interconnects due to its high conductivity and high current-carrying capacity ^{[1] [2] [3]} . Graphene sheets are also an attractive alternative to carbon nanotube-based interconnects as they are more compatible with conventional lithography methods. The purpose of this project is to integrate graphene devices as redundant interconnects for a low-power field-programmable gate array (FPGA). Interconnect delay is a significant portion of the delay due to multiple routing segments in an FPGA. Furthermore, global interconnects have been shown to dominate the total power consumption in FPGAs ^[4] .

In this work, we monolithically integrate graphene interconnects on a prototype CMOS chip. Large-area graphene sheets are first grown by chemical vapor deposition ^[5] and transferred onto the CMOS chip. The large graphene sheet is then lithographically patterned and etched into interconnect wires. Each end of the graphene wire is electrically connected to the underlying transmitter/receiver pair. The test chip includes an FPGA with 5×5 array of logic blocks and 10-bit unidirectional buses. Most of the wire segments in between the core logic blocks and switch matrices are implemented in the CMOS metal layers. A total of 16 double-length wires use graphene, which interfaces to the switch matrices. Each segment has 4 redundant wires and a tester unit. The tester unit uses a coarse time-to-digital converter (TDC) to measure and convert the RC delay of the graphene wire into a 3-bit digital code. The TDCs have tunable resolution with a delay range between 1 ns and 20 µs.

1. X. Du, I. Skachko, A. Barker, and E. Y. Andrei, ”Approaching ballistic transport in suspended graphene,” Nature Nanotech., vol. 3, no. 8, pp. 491–495, 2008.
2. R. Murali, Y. Yang, K. Brenner, T. Beck, and J. D. Meindl, “Breakdown current density of graphene nanoribbons,” Appl. Phys. Lett., vol. 94, no. 24, p. 243114, 2009.
3. A. Naeemi and J. Meindl, “Conductance modeling for graphene nanoribbon (gnr) interconnects,” IEEE Electron Device Lett., vol. 28, no. 5, pp. 428–431, May 2007.
4. F. Li, Y. Lin, and L. He, “Vdd programmability to reduce FPGA interconnect power,” in Proc. IEEE/ACM International Conference on Computer Aided Design, 2004, pp. 760–765.
5. A. Reina, X. Jia, J. Ho, D. Nezich, H. Son, V. Bulovic, M. S. Dresselhaus, and J. Kong, “Large area, few-layer graphene films on arbitrary substrates by chemical vapor deposition,” Nano Lett., vol. 9, no. 1, pp. 30–35, 2009.

Figure 1: System block diagram of the fully-integrated low-voltage AFE. The mixed-signal feedback loop comprises the analog circuits shown in white and digital processing shown with the shaded blocks.

Circuits for wearable vital sign monitors have very stringent requirements on power dissipation due to limited energy storage capacity.  Extending the time between battery recharge or device replacement requires low-power circuits.  This work focuses on the design of a fully-integrated, low-voltage, digitally-assisted analog front-end (AFE) for ambulatory ECG monitoring, and it builds on work described in ^[1] .  The power consumption of an AFE is often determined by dynamic range (DR) requirements.  For bio-potential acquisition, the high end of the DR requirement is often set by interference such as 50/60-Hz power-line interference (PLI) ^[2] .  Here, a mixed-signal interference cancellation loop is used to cancel PLI right at the input of the system, thus reducing the DR requirement to enable low-voltage operation.  The fully-integrated AFE shown in Figure 1 leverages techniques such as oversampling, digital processing, and delta-sigma noise shaping to reduce the system area and power.  A target supply voltage of 0.6V provides power savings from voltage scaling and ensures compatibility with state-of-the-art digital signal processors ^[3] to reduce system complexity.

1. J. L. Bohorquez, M. Yip, A. P. Chandrakasan and J. L. Dawson, “A digitally-assisted sensor interface for biomedical applications,” in Proc. IEEE Symp. on VLSI Circuits, Jun. 2010, pp. 217-218.
2. E. M. Spinelli and M. A. Mayosky, “Two-electrode biopotential measurements: Power line interference analysis,” IEEE Trans. Biomedical Engineering, vol. 52, no. 8, pp. 1436-1442, Aug. 2005.
3. J. Kwong and A. P. Chandrakasan, “An energy-efficient biomedical signal processing platform,” in Proc. IEEE European Solid-State Circuits Conference, Sep. 2010, pp. 526-529.

The use of video is becoming an important part of today’s world, and consumers are constantly demanding high-definition performance. In today’s market, different video standards featuring different techniques exist (Figure 1), and supporting multiple standards is a necessity. However, video encoding is a computationally intensive process, and battery operated devices such as mobile phones suffer from short battery lives during video encoding. Hence, low-power techniques such as voltage scaling and parallelism need to be applied to video coding ^[1] to support very high resolution levels for different standards.

In this work, a reconfigurable video encoder supporting both H.264/AVC High Profile Level 5.1 ^[2] and VC-1 Advanced Profile Level 4.0 ^[3] standards is designed. The target resolution and frame rate are Quad Full HD (4Kx2K) and 30 fps, respectively. To minimize energy consumption, 0.5 V operation enabled through highly parallel architecture is implemented.

A block diagram of a video encoder is shown in Figure 2. All functional blocks are designed with circuit reconfigurability to support both H.264/AVC and VC-1 standards. Frame and macro-block level parallelism concepts are investigated and implemented to achieve a high throughput constraint at low-voltage levels. The motion estimation block uses data reuse to minimize off-chip data accesses and shares the searching range across multiple macro-blocks. An intra prediction block exploits data dependency to minimize switching activity and matrix factorization to achieve low-power operation. An early mode decision scheme is also implemented to avoid using the motion estimation procedure that is costly in terms of power consumption. Entropy coding block is designed to support the high-levels of parallelism. Overall, a 10X reduction in power consumption is estimated with the proposed techniques.

1. D. F. Finchelstein, V. Sze, M. E. Sinangil, Y. Koken, and A. P. Chandrakasan, “A low-power 0.7-V H.264 720p video decoder,” IEEE Asian Solid-State Circuits Conference, pp. 173-176, Nov. 2008.
2. “Advanced Video Coding for Generic Audio Visual Services,” ITU-T H.264, Mar. 2009.
3. “VC-1 Compressed Video Bitstream Format and Decoding Process,” SMPTE 421M-2006, Feb. 2006.

On-chip memories are responsible for a large portion (40% by many estimates) of the total energy consumption and area of modern processor designs. Therefore, memory optimization for density, power, and frequency trade-offs is crucial to meet the aggressive power goals for the exascale processors. Today’s cache bit-cells in 65-nm CMOS consume 1 pJ per access at 1.0 V. Our goal is to reduce this amount by a factor of 18 to Angstrom Project’s target at 11-nm technology. This gives us a clear target of 50 fJ energy per operation (E/Op) per bit-cell at 11-nm.

We are designing the first version of Angstrom microprocessor’s L1-cache using 65-nm CMOS. To decrease E/Op from ~1 pJ to ~200 fF per bit-cell, we designed our L1-cache bit-cells to work down to 0.5 V. SRAM bit-cells suffer from decreased stability at low-voltages. In Figure 1, read and write margins of a bit-cell are simulated by 1000-point Monte Carlo analyses at 0.5 V, and negative values indicate failures. To combat margin problems, the work in ^[1] uses an 8-transistor (8T) bit-cell. This bit-cell’s read port is de-coupled from the storage nodes as it is given in Figure 1, so it is immune to read-upsets. The remaining 6 transistors can be sized to favor writes.

For the 8T bit-cell, a single ended sense amplifier (SA) is necessary since read-bit-line (RBL) is the only port used for the read operation. Different SA techniques have been analyzed such as non-strobed regenerative sensing ^[2] and strobed strong-arm based sensing; the latter is chosen due to its robust design and low-voltage compatibility. The offset of SA is reduced using offset-compensation techniques, and this concept is illustrated by 1000-point Monte Carlo analyses on input offset of our strong-arm type SA with or without compensation. All analyses shown are done on 22-nm predictive technology ^[3] .

1. Chang, L.; Fried, D.M.; Hergenrother, J.; Sleight, J.W.; Dennard, R.H.; Montoye, R.K.; Sekaric, L.; McNab, S.J.; Topol, A.W.; Adams, C.D.; Guarini, K.W.; Haensch, W.; , “Stable SRAM cell design for the 32 nm node and beyond,” VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on , pp. 128- 129, 14-16 June 2005.
2. Verma, N.; Chandrakasan, A.P., “A High-Density 45nm SRAM Using Small-Signal Non-Strobed Regenerative Sensing,” Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International, pp. 380-621, 3-7 Feb. 2008.
3. N. Integration and T. Modeling (NIMO) Group, Arizona State Univ.,  “Predictive technology model,” 2008. [Online]. Available: http://ptm.asu.edu/.

Low-power portable electronics such as implantable medical devices require low-access-energy non-volatile memory to deliver longer battery lifetime and richer functionality. Ferroelectric random access memory (FRAM) technology is a good candidate for both storage and non-volatile RAM (NVRAM) because it provides significant improvement in energy consumption, performance, and endurance compared to current solutions based on FLASH memory technology. The power and supply voltage of FRAM need further reduction in order to achieve the full potential of the technology. This work addresses the challenge of sensing diminishingly small charge and develops circuits compatible with the scaling of FRAM technology to low voltage and more advanced CMOS nodes with a time-to-digital sensing scheme.

A 1-Mb 1T1C FRAM is designed and fabricated in 130-nm CMOS. Measured results show that performance, spanning 5.03 MHz at 1.5 V to 1.37 MHz at 1.0 V, can be traded off for a reduction in access energy from 19.2 pJ (1.5 V operation) to 9.8 pJ per bit (1.0 V operation). By converting the bitcell charge to a delay, the proposed sensing scheme multiplexes the continuous signal in time simply through a daisy chain of OR gates. Thus 2²⁰ 1T1C cells multiplex to eight 5-bit time-to-digital converters (TDCs) while preserving 64.4% memory array efficiency. Low voltage operation is enabled by a TDC sensing network that captures the bitcell signal to a finer resolution by digitizing and then subtracting the offset of circuits in the read path. A 128-kb 8T8C design further illustrates the voltage scaling of the sensing network by operating down to 0.8 V with 8.4 pJ access energy. Ultimately, the time-to-digital sensing scheme generalizes across NVRAM technologies as a means to 1) compensate analog offset with digital circuits, 2) operate at low voltage with minimum static power, and 3) better serve the essential multiplexing operation of memory.

1. M. Qazi, M. Clinton, S. Bartling, and A. Chandrakasan, “A low-voltage 1Mb FeRAM in 0.13um CMOS featuring time-to-digital sensing for expanded operating margin in scaled CMOS,” IEEE International Solid-State Circuits Conference, pp. 208-209, Feb. 2011.