The Center for Integrated Circuits and Systems (CICS) at MIT, established in early 1998, is an industrial consortium created to promote new research initiatives in circuits and systems design, as well as to promote a tighter technical relationship between MIT’s research and relevant industry. Seven faculty members participate in the CICS: Hae-Seung Lee (director), Duane Boning, Anantha Chandrakasan, Joel Dawson, David Perreault, Charles Sodini, and Vladimir Stojanovic. CICS investigates a wide range of circuits and systems, including wireless and wireline communication, high-speed and RF circuits, microsensor/actuator systems, imagers, digital and analog signal processing circuits, and power conversion circuits, among others.

We strongly believe in the synergistic relationship between industry and academia, especially in practical research areas of integrated circuits and systems. CICS is designed to be the conduit for such synergy. At present, participating companies include Analog Devices, IBM, Linear Technology, Marvell Technology Group, Maxim Integrated Products, Media Tek, National Semiconductor, and Texas Instruments.

CICS’s research portfolio includes all research projects that the seven participating faculty members conduct, regardless of source(s) of funding, with a few exceptions.

Technical interaction between industry and MIT researchers occurs on both a broad and individual level. Since its inception, CICS recognized the importance of holding technical meetings to facilitate communication among MIT faculty, students, and industry.  We hold two informal technical meetings per year open to CICS faculty, students, and representatives from participating companies. Throughout each full-day meeting, faculty and students present their research, often presenting early concepts, designs, and results that have not been published yet. The participants then offer valuable technical feedback, as well as suggestions for future research.  More intimate interaction between MIT researchers and industry takes place during work on projects of particular interest to participating companies. Companies may invite students to give on-site presentations, or they may offer students summer employment. Additionally, companies may send visiting scholars to MIT or enter into a separate research contract for more focused research for their particular interest.. The result is truly synergistic, and it will have a lasting impact on the field of integrated circuits and systems.

In today’s large systems-on-a-chip, communication infrastructure such as high-speed I/Os consumes a significant portion of power, limiting the amount left for useful computation ^[1] . The conflicting bandwidth and power scaling requirements have stimulated vigorous research activities resulting in significant improvements in link energy-efficiency ^{[2] [3]} . These improvements in energy-efficiency have focused on the most dominant sub-systems, such as the clocking and signaling transmit‑receive chain. To that end, voltage-mode (VM) drivers have been introduced instead of current-mode (CM) drivers to improve the energy-efficiency of the transmitter ^{[2] [3]} . However, these VM drivers suffer from a power penalty when used to implement a transmit pre-emphasis filter ^[2] , which is particularly well suited for asymmetric-complexity link channel applications such as memory interfaces ^[4] and lossy channels with long intersymbol-interference (ISI) tails such as cables or silicon carriers ^[5] .

In this work, we show that the power penalty incurred by the traditional driver topologies can be tied to the channel impedance matching constraints. Analysis reveals that power-efficiency improvements over the VM transmit-equalization scheme must come from the controlled relaxation of impedance matching constraints on common‑mode and/or differential‑mode matching. One design that makes such a tradeoff, with frequency-selective common‑mode matching for improved power efficiency, appears in ^[6] . Going a step further, we re-examine the benefits of the static differential impedance matching, and analyze the possible tradeoffs if this constraint is removed, showing that the most efficient driver topology is based on dynamic resistance-modulation (RM) of transmitter impedance.

A test chip fabricated in a 90-nm CMOS process shows relatively small signal degradation from dynamic modulation of driver output impedance over a variety of 20” backplanes at 4 Gb/s, with energy-efficiency of  2pJ/bit at 100 mV of receiver eye, in Figure 1. Despite the signal degradation due to impedance mismatch in its operation, the RM driver compares favorably with the traditional driver topologies (CM and different forms of VM driver) in terms of power efficiency, Figure 2, while allowing for a very compact, fully-digital, implementation.

1. J. L. Shin, K. Tam, D. Huang, B. Petrick, H. Pham, C. Hwang, H. Li, A. Smith, T. Johnson, and F. Schumacher, “A 40nm 16-core 128-thread CMT SPARC SoC processor,” IEEE Journal of Solid State Circuits, vol. 46, p. 131–144, 2011.
2. H. Hatamkhani and R. Drost, “A 10-mW 3.6-Gbps I/O transmitter,” 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408), 2003, pp. 97-98.
3. J. Poulton, R. Palmer, A. Fuller, T. Greer, J. Eyles, W. Dally, M. Horowitz, I. Rambus, and C. Hill, “A 14-mW 6.25-Gb/s transceiver in 90-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 42, p. 2745–2757, 2007.
4. K. Chang, H. Lee, J.-H. Chun, T. Wu, T. J. Chin, K. Kaviani, J. Shen, X. Shi, W. Beyene, Y. Frans, B. Leibowitz, N. Nguyen, F. Quan, J. Zerbe, R. Perego, F. Assaderaghi, E. C. Real, and L. Altos, “A 16Gb/s/link, 64GB/s bidirectional asymmetric memory interface cell,” 2008 IEEE Symposium on VLSI Circuits, June 2008, pp. 126-127.
5. B. Kim, Y. Liu, T. O. Dickson, J. F. Bulzacchelli, and D. J. Friedman, “A 10-Gb/s compact low-power serial I/O with DFE-IIR equalization in 65-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3526–3538, Dec. 2009.
6. W. D. Dettloff, J C. Eble, L. Luo, P. Kumar, F. Heaton, T. Stone, and B. Daly, “A 32mW 7.4 Gb/s protocol-agile source-series-terminated transmitter in 45nm CMOS SOI,” Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, IEEE, pp. 370–371.

Implantable medical sensors are an emerging application area that exemplifies the stringent energy constraints imposed on wireless sensor circuits. In typical circuit blocks used for medical monitoring, the cost to wirelessly transmit data is orders of magnitude greater than for any other function. State-of-the-art radio transmitters exhibit energy-efficiencies in the nJ/bit range while every other component consumes at most only 10’s of pJ/bit. This cost disparity suggests that some data reduction strategy at the sensor node should be employed to minimize the energy cost of the system. Existing strategies for implementing integrated data compression or filtering solutions under these constraints largely revolve around detecting and extracting specific signal data ^{[1] [2] [3]} . However, the filtered data often contains limited information. For these signal processing strategies, there is a tradeoff between data reduction, robustness, implementation cost, and the granularity of information captured. In each case, the goal is to minimize the number of bits transmitted (to minimize the average radio power) while reliably preserving the signal information at a minimum implementation cost.

In this work, we introduce the design and implementation of a sensor compression architecture (Figure 1) based on the theory of compressed sensing (CS) ^[4] that offers an improved set of tradeoffs toward achieving this goal. A CS-based sensor system combines the positive qualities of existing data acquisition and compression systems: it provides a flexible and general interface like an analog-to-digital converter (ADC) yet still enables data compression proportional to the signal information content, which is consistent with the performance of source coding. For wireless sensor applications, this combination of characteristics is particularly attractive as it would enable a single hardware interface across many applications while simultaneously addressing the energy cost of the wireless telemetry. This approach reduces the average radio power by exploiting signal sparseness to encode the data at a high compression factor (>10x) while enabling a faithful reconstruction of the entire original signal. An efficient implementation of the CS encoder and encoder matrix generation (Figure 2) is realized and demonstrated in a 90-nm CMOS process and consumes 1.9 µW at 0.6 V and 20 kS/s ^[5] .

1. R. Harrison, P. Watkins, R. Kier, R. Lovejoy, D. Black, B. Greger, and F. Solzbacher, “A low-power integrated circuit for a wireless 100-electrode neural recording system,” IEEE Journal of Solid-State Circuits, vol. 42, pp. 123-133, 2007.
2. R. Olsson and K. Wise, “A three-dimensional neural recording microsystem with implantable data compression circuitry,” IEEE Journal of Solid-State Circuits, vol. 40, pp. 2796-2804, 2005.
3. N. Verma, A. Shoeb, J. Bohorquez, J. Dawson, J. Guttag, and A.P. Chandrakasan, “A micro-power EEG acquisition SoC with integrated feature extraction processor for a chronic seizure detection system,” IEEE Journal of Solid-State Circuits, vol. 45, pp. 804-816, 2010.
4. D. Donoho, “Compressed sensing,” IEEE Transactions on Information Theory, vol. 52, pp. 1289–1306, 2006.
5. F. Chen, A.P. Chandrakasan, and V. Stojanovic, “A Signal-agnostic compressed sensing acquisition system for wireless and implantable sensors,” presented at IEEE Custom Integrated Circuits Conference, San Jose, CA, 2010.

Intracranial pressure (ICP) is a key factor in monitoring a patient’s cerebrovascular state.  However, current ICP measurement modalities are highly invasive, relying on surgical penetration of the skull.  Recent developments in model-based physiology allow ICP to be estimated using arterial blood pressure and cerebral blood flow velocity (CBFV) measurements ^[1] .  CBFV can be obtained non-invasively using transcranial Doppler (TCD) ultrasonography, but requires bulky capital equipment and an expert operator to manually focus the ultrasound beam on a particular intracranial blood vessel.  Therefore, TCD measurements of CBFV are currently restricted to clinical environments in which such technology and expertise are available (typically neurocritical care units).

This project seeks to develop a low-power, miniaturized TCD ultrasonography system for measuring CBFV in the middle cerebral artery (MCA) in support of continuous monitoring of ICP.  The MCA is typically about 3 mm in diameter and is insonated through the temporal bony window at a distance of 40 to 60 mm from the ultrasonic transducer array.  These anatomic considerations place significant constraints on the focal length and spatial resolution requirements of the transducer array.  Adjusting the transmit amplitude and phase of each element in the 2D transducer array via a digital beamformer and high voltage (HV) pulser achieves electronic beam steering in three spatial dimensions.  Figure 1 shows relative acoustic power density for a 15° off-axis focus using a 2D transducer array with electronic beam steering.

Development of a beam steering algorithm will allow for autonomous location of the MCA, eliminating the need for a skilled operator. TCD ultrasonography focusing is further complicated by the highly non-homogenous acoustic propagating medium (i.e., presence of high-density cranium).   This issue can be mitigated, however, using calibration methods ^[2] . An HV multiplexer (MUX) is utilized so that a single transmit/receive (T/R) channel can connect to multiple transducer elements and thus greatly reduce the necessary electronics and power requirements.  This system architecture, as illustrated in Figure 2, will allow for a self-contained system for continuous CBFV measurement in a low-power and wearable form-factor.

1. F. M. Kashif, T. Heldt, and G. C. Verghese. “Model-based estimation of intracranial pressure and cerebrovascular autoregulation,” Computers in Cardiology, vol. 35, pp. 369-372, Sep. 2008.
2. G.T. Clement and K. Hynynen, “A non-invasive method for focusing ultrasound through the human skull,” Physics in Medicine and Biology, vol. 47, pp. 1219-1236, Apr. 2002.

Vital signs such as heart rate, blood pressure, blood oxygenation, cardiac output, and respiratory rate are necessary in determining the overall health of a patient.  Continuous monitoring of these vital signs can help assess the wearer’s overall state of health and identify risks for cardiovascular diseases ^[1] .

We propose the site behind the ear as a location for an integrated wearable vital signs monitor ^[2] . This location offers physiological signals such as the electrocardiogram (ECG), the photoplethysmogram (PPG), and the head ballistocardiogram (hBCG). The ECG measures the electrical activity from the heart and offers information such as continuous heart rate, blood pressure (when coupled with PPG or hBCG), and respiratory rate. The PPG measures the blood volume and color under the skin using optical illumination. The PPG offers information such as continuous heart rate and blood oxygenation. The hBCG measures the head’s mechanical reaction to the blood expelled by the heart and offers information about continuous heart rate, cardiac output, and respiratory rate.

A simultaneous measurement of ECG, PPG, and hBCG is shown in Figure 1. Using the peak timing data from ECG, PPG, and hBCG, blood pressure can be estimated. Figure 2 compares the estimated blood pressure with a commercial blood pressure measurement during a Valsalva breath-hold maneuver.

To make the monitor wearable, the electrodes must be small, comfortable, and gel-less to avoid skin irritation. We use 1-cm² capacitive and dry electrodes made of wearable fabric materials. The device is designed to use the ear as a discreet and a natural anchor that reduces device visibility and the need for skin adhesives.

1. S. D. Pierdomenico, M. Di Nicola, A. L. Esposito, R. Di Mascio, E. Ballone, D. Lapenna, F. Cuccurullo, “Prognostic value of different indices of blood pressure variability in hypertensive patients,” American Journal of Hypertension, vol. 22(8), pp. 842-847, June 2009.
2. D. He, E. S. Winokur, T. Heldt, C. G. Sodini, “The ear as a location for wearable vital signs monitoring,” Proc. of the IEEE Engineering in Medicine and Biology Conference, Sept. 2010, pp. 6389-6392.

Figure 1: Simplified system block diagram.

Epilepsy is a common chronic neurological disorder that affects about 1% of the world population ^[1] . It is characterized by repeated seizures, which are caused by an abnormal neuronal firing rate of the affected brain area. One way to detect a seizure is through an electroencephalogram (EEG), which is the recording of the electrical activity produced by the firing of neurons in the brain. Continuous EEG recording is extremely important for patients with epilepsy because doctors cannot only track the number of seizures the patient has, but also have access to the recordings during the attacks which allows doctors to determine the efficacy of the treatment.

The most common EEG recording place is at the scalp; however, it can also be obtained at the skull (subdermal) or at the brain (subdural). Continuous EEG recordings through measurements at the scalp require that the patient wears an external medical device at all times, which can be extremely inconvenient. One way to solve this problem is to implant the medical device. A subdural EEG implant would require a very complex surgery, so we have decided to do a subdermal EEG and avoid such complications. Our minimally invasive implant will be placed between the scalp and the skull behind the right ear, and the electrodes will run to the front part of the skull.

Our system consists of 2 EEG channels sampled at approximately 250 Hz with a 12-bit resolution. Figure 1 shows the simplified system block diagram.

1. W. C. Stacey and B. Litt, “Technology insight: neuroengineering and epilepsy – designing devices for seizure control,” Nature Clinical Practice Neurology, vol. 4, pp. 190-201, 2008.

Technology scaling poses challenges in designing analog circuits because of the decrease in intrinsic gain and reduced swing. An alternative to using high-gain amplifiers in the implementation of switched capacitor circuits has been proposed ^[1] that replaces the amplifier with a current source and a comparator. The new comparator-based switch capacitor (CBSC) and zero-crossing-based circuit (ZCBC) techniques have been implemented in two pipelined ADC architectures at 10 MHz and 200 MHz and 10-bit and 8-bit accuracy, respectively ^{[1] [2]} .

The purpose of this project is to explore the use of the ZCBC technique for very-high-precision AD converters. The goal of the project is a 100 MHz, 14-bit pipelined ADC. First, we are investigating dual-phase hybrid ZCBC operation to improve the power-linearity tradeoff of the A/D conversion ^[3] and to improve the power supply rejection. The first phase approximates the final output value, while the second phase allows the output to settle to its accurate value. Since the output is allowed to settle in the second phase, the currents through capacitors decay, permitting higher accuracy and power-supply rejection compared with standard ZCBCs.  We are also developing linearization techniques for the ramp waveforms. Linear ramp waveforms require less correction in the second phase for given linearity, thus allowing faster operation. Innovative techniques for improving linearity beyond using a cascoded current source are explored; these techniques include output pre-sampling and bi-directional output operation. In addition, overshoot reduction calibration is implemented to improve the linearity requirements of the final phase. Digital self- calibration will be explored to reduce the residual constant offset. The ADC was implemented in a 65-nm 1-V process, and its operation is currently being evaluated.

1. T. Sepke, J. K. Fiorenza, C. G. Sodini, P. Holloway, and H.-S. Lee, “Comparator-based switched capacitor circuits for scaled CMOS technologies,” IEEE International Solid State Circuits Conference Digest of Technical Papers, Feb. 2006, pp. 220-221.
2. L. Brooks and H.-S. Lee, “A zero-crossing based 8b 200MS/s pipelined ADC,” IEEE International Solid State Circuits Conference Digest of Technical Papers, Feb. 2007, pp. 460-461.
3. J. K. Fiorenza, “A comparator-based switched –capacitor pipelined analog-to-digital converter,” Ph.D. thesis, Massachusetts Institute of Technology, Cambridge, 2007.

Figure 1

Most current ultrasound imaging systems use piezoelectric materials for the ultrasound transducer. The recent development of micro-electromechanical systems (MEMS) allowed fabrication of capacitive micromachined ultrasound transducers (CMUTs).  A CMUT is a micromachined capacitor whose value changes according to the DC bias voltage or external pressure due to the physical deformation of the top plate by electrostatic force or external pressure. The major advantages of this transducer technology are the potential for integration with supporting electronic circuits, ease of fabrication, higher resolution due to small transducer size, and improved bandwidth and sensitivity ^[1] .

This project focuses on the front-end design of portable ultrasound systems using CMUTs. Figure 1 presents a conceptual block diagram of the system. Implementing an ADC at each channel input makes possible digital beam-forming in the receive (Rx) path, which enhances ultrasound image quality. To implement as many ADCs as the number of transducer channels, each ADC must consume as little power as possible, and each should be implemented in a small area. Considering the required performance, a zero-crossing-based (ZCB) pipelined ADC is a suitable architecture ^[2] .  For the first part of this project, a 50-MHz 12-bit ZCB pipelined ADC is designed. The highly digital implementation characteristic of the zero-crossing detection technique enables energy-efficient operation and voltage scaling. Supply voltage scaling based on the required sampling frequency and resolution provides constant energy efficiency over a wide range of sampling frequencies and resolutions.

Recently, a few 2D imaging systems using CMUT as ultrasound transducers have been reported, but they do not use real-time imaging ^[1] . The digital image processing block will be considered in the system level for real-time imaging.  After completing the 2D ultrasound image system using a 1D transducer, we will examine the feasibility of the 3D ultrasound image system using 2D transducers.

1. O. Oralkan, “Acoustical imaging using capacitive micromachined ultrasonic transducer arrays: Devices, circuits, and systems,” Ph.D. thesis, Stanford University, Palo Alto, CA, 2004.
2. L. Brooks and H.-S. Lee, “A zero-crossing-based 8b 200MS/s pipelined ADC,” IEEE International Solid-State Circuits Conference, 2007. Digest of Technical Papers, pp. 460-615.

Malaria prevails mainly in the countries that lack proper medical facilities, and it kills about a million people worldwide a year. This parasitic disease invades human red blood cells (RBCs), and it is life-threatening unless treated immediately ^[1] .

This work focuses on utilizing a single cell analysis technique to develop a rapid malaria diagnostic test system among various approaches to diagnose the disease in its early stage. Single cell analysis based on electronics enables high throughput tests of biological cells. The specific analysis method used in this research is electric impedance spectroscopy (EIS), which measures the electric impedance of biological cells flowing continuously over a pair of electrodes, so that it can differentiatecells whose impedance is highly correlated to cell size and cytoplasm permittivity ^{[2] [3] [4] [5] [6]} .

The system consists of two parts: a MEMS probe and a reader circuit. To investigate one cell at a time and to achieve enough sensitivity to tiny (<10 µm) human red blood cells, a MEMS device consisting of a microfluidic channel and micro-electrodes is fabricated. The probe MEMS device is made of transparent materials except the electrodes for convenience of monitoring. In addition, a printed-circuit-board using a commercial impedance-to-digital chip is made to continuously measure electric impedance in high-speed manner. The circuit board generates a sinusoidal voltage signal, measures the DFT of the resulting current, and calculates the impedance from DFT. We are seeing this system as a possible solution for developing a low-power, highly sensitive, and cost-effective malaria diagnostic device.

1. World Health Organization Staff, World Malaria Report 2009, World Health Organization, Geneva, Switzerland, 2009.
2. A. Valero, T. Braschler and P. Renaud, “A unified approach to dielectric single cell analysis: Impedance and dielectrophoretic force spectroscopy,” Lab on a Chip, vol. 10, pp. 2216-2225, June 2010.
3. H. Morgan, T. Sun, D. Holmes, S. Gawad and N. G. Green, “Single cell dielectric spectroscopy,” J. Phys. D: Appl. Phys., vol. 40, pp.61-70, 2007.
4. H. E. Ayliffe, A. B. Frazier and R. D. Rabbitt, “Electric impedance spectroscopy using microchannels with integrated metal electrodes,” J. Microelectromechanical systems, vol. 8, Mar. 1999.
5. C. Ribaut, K. Reybier, O. Reynes, J. Launay, A. Valentin, P. L. Fabre and F. Nepveu, “Electrochemical impedance spectroscopy to study physiological changes affecting the red blood cell after invasion by malaria parasites,” Biosensors and Bioelectronics, vol. 24, pp. 2721-2725, Dec. 2009.
6. L. I. Segerink, A. J. Sprenkels, P. M. ter Braak, I. Vermes and A. van Den Berg, “On-chip determination of spermatozoa concentration using electrical impedance measurement,” Lab on a Chip, vol.10, pp. 1018-1024, Feb. 2010.