Collaborators

• D. Antoniadis, EECS
• F. Kartner, EECS
• M. Canonico, ASU
• T. Lyszczarz, MIT Lincoln Labs
• J. Yoon, MIT Lincoln Labs
• A. Nayfeh, Masdar Institute

Graduate Students

• W. Chern, EECS
• N. DiLello, EECS
• L. Gomez, EECS
• M. Kim, DMSE
• J. Teherani, EECS

Research Staff

• G. Riggott, Research Specialist
• P. Hashemi, Post-doctoral Scholar

Support Staff

• W. Rokui, Admin. Asst. II

Publications

P. Hashemi, J.T. Teherani, and J.L. Hoyt, “Investigation of Hole Mobility in Gate-All-Around Si Nanowire p-MOSFETs with High-k/Metal-Gate: Effects of Hydrogen Thermal Annealing and Nanowire Shape,” International Electron De­vice Meeting (IEDM 2010), San Francisco, USA, Session 34.5 De­cember 2010.

P. Hashemi, C.D. Poweleit, M. Canonico, and J.L. Hoyt, “Ad­vanced Strained-Silicon and Core-Shell Si/Si_1-xGe_x Nanowires for CMOS Transport Enhancement,” ECS (Electrochemical Society) Transactions, October 2010.

M. Kim, P. Hashemi, and J.L. Hoyt, Increased critical success for high Ge-content strained SiGe-on Si Using selective epitaxial growth, Appl. Phys. Lett. 97, 262106, 2010.

L. Gomez, C. Ni Chleirigh, P. Hashemi, and J.L. Hoyt, “En­hanced Hole Mobility in High-Ge Content Asymmetrically Strained-SiGe p-MOSFETs,” IEEE Electron Device Letters, vol. 31, no. 8, pp. 782 – 784, August, 2010.

Guangrui Xia and J.L. Hoyt, “Si-Ge interdiffusion under oxidizing con­ditions in epitaxial SiGe hetero­structures with high compressive stress,” Applied Physics Letters, v 96, n 12, p 122107 (3 pp.), 22 March 2010.

P. Hashemi, M. Kim, J. Hennessy, L. Gomez, D.A. Antoniadis and J.L. Hoyt, “Width-dependent hole mobility in top-down fabricated Si-core/Ge-shell nanowire MOS­FETs”, Appl. Phys. Lett. 96 (6), p. 063109, Feb. 2010.

J.S. Orcutt, A. Khilo, M.A. Popovic, C.W. Holzwarth, H. Li, J. Sun, B. Moss, M.S. Dahlem, E.P. Ippen, J.L. Hoyt, V. Stojanovic, F.X. Kärt­ner, H.I. Smith, and R.J. Ram, “Photonic integration in a commer­cial scaled bulk-CMOS process,” Source: 2009 International Confer­ence on Photonics in Switching, PS ’09, 2009, 2009 International Conference on Photonics in Switching, PS ’09, p. 2.

L. Gomez, P. Hashemi, and J.L. Hoyt, “Enhanced Hole Transport in Short-Channel Strained-SiGe p-MOSFETs,” IEEE Transactions on Electron Devices, vol. 56, no.11, pp.2644-2651, Nov. 2009.

O.M. Nayfeh, J.L. Hoyt and D.A. Antoniadis, “Strained Si1-xGex/Si Band-to-Band Tunneling Transis­tors: Impact of Tunnel-Junction Germanium Composition and Doping Concentration on Switch­ing Behavior,” IEEE Transactions on Electron Devices, vol. 56,   no. 10,  pp. 2264-2669, Oct. 2009.

P. Hashemi, L. Gomez, and J.L. Hoyt, “Gate-All-Around N-MOSFETs with Uniaxial Tensile Strain-Induced Performance En­hancement Scalable to Sub-10-nm Nanowire Diameter,” IEEE Elec­tron Device Letters, vol. 30, no. 4, pp. 401-403, April 2009.

A.K. Sood, R.A. Richwine, Y.R. Puri, N. DiLello, J.L. Hoyt, T.I. Akinwande, S. Horn, R.S. Balcerak, G. Bulman, R. Venka­tasubramanian, R., A.I. D’Souza, T.G. Bramhall, “Development of low dark current SiGe-detector arrays for visible-NIR imaging sen­sor,” Proceedings of the SPIE, vol.  7298, p 72983D, 2009.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M.A. Popovic, Hanqing Li, H.I. Smith, J.L. Hoyt, F.X. Kartner, R.J. Ram, V. Stojanovic, and K. Asanovic, “Building many-core processor-to-DRAM networks with monolithic CMOS silicon photonics,” IEEE Micro, vol. 29, no.  4, pp. 8-21, July-Aug. 2009.

C.W. Holzwarth, et al., “High speed analog-to-digital conversion with silicon photonics,” Proceedings of the SPIE v 7220, p 72200B (15 pp.), 2009.

L. Gomez, P. Hashemi, and J.L. Hoyt, “Enhanced Hole Transport in Short-Channel Strained-SiGe p-MOSFETs,” IEEE Transactions on Electron Devices, vol. 56, no. 11, pp. 2644-2651, Nov. 2009.

O.M. Nayfeh, J.L. Hoyt and D.A. Antoniadis, “Strained Si1-xGex/Si Band-to-Band Tunneling Transis­tors: Impact of Tunnel-Junction Germanium Composition and Doping Concentration on Switch­ing Behavior,” IEEE Transactions on Electron Devices, vol. 56, no. 10, pp. 2264-2669, Oct. 2009.

P. Hashemi, L. Gomez, and J.L. Hoyt, “Gate-All-Around N-MOS­FETs with Uniaxial Tensile Strain-Induced Performance Enhance­ment Scalable to Sub-10-nm Na­nowire Diameter,” IEEE Electron Device Letters, vol. 30, no. 4, pp. 401-403, April 2009.

The type-II band alignment between strained-silicon (s-Si) and strained-germanium (s-Ge) has been proposed for use in tunneling transistors due to the small effective band gap between the s-Si conduction band and s-Ge valence band ^[1] . The small effective band gap may substantially increase tunneling current compared to a Ge homostructure while maintaining low off-state leakage. However, the valence band alignment between thin layers of s-Si and s-Ge on a relaxed SiGe substrate has not been experimentally extracted.

The experimental device structure consists of an Al₂O₃ high-κ dielectric (~6 nm) on a Si capping layer (~ 6 nm) on s-Ge (~ 6 nm) grown pseudomorphically on a relaxed SiGe buffer (~1 µm) with 40% Ge concentration. The wafers were processed into MOS-capacitors and measured using low-frequency and quasistatic C-V techniques. The valence band offset can be extracted by fitting the simulation data to experimental C-V measurements ^[2] . In Figure 1, the width of region II is dependent on the valence band offset and effective band gap between the s-Si and s-Ge layers.

Figure 2 shows the band structure and hole density as a function of position for the fabricated structure. At 0 V gate voltage, most holes near the surface of the capacitor are contained in the s-Ge quantum well. Since the s-Ge quantum well is displaced from the Al₂O₃ surface by the s-Si layer, the effective thickness is larger and thus the measured capacitance is lower than the oxide capacitance. As a more negative bias is applied to the gate, holes begin to accumulate at the s-Si/Al₂O₃ surface so that the total capacitance increases and approaches the oxide capacitance. The extracted valence band offset between the s-Si and s-Ge layers was 740±30 meV, which also suggests a small effective band gap.

1. O. M. Nayfeh, C. N. Chleirigh, J. Hennessy, L. Gomez, J. L. Hoyt, and D. A. Antoniadis, “Design of tunneling field-effect transistors using strained-silicon/strained-germanium Type-II staggered heterojunctions,” IEEE Electron Device Letters, vol. 29, no. 9, pp. 1074-1077, Sep. 2008.
2. C. N. Chleirigh, C. Jungemann, J. Jung, O. O. Olubuyide, and J. L. Hoyt, “Extraction of band offsets in strained Si/strained Si1-yGey on relaxed Si1-xGex dual-channel enhanced mobility structures,” in Proc. Electrochemical Society: SiGe: Materials, Processing and Devices, pp. 99–109, 2005.

Germanium is a promising candidate for use in CMOS-compatible photodiodes.  Its strong absorption in the 1.55-µm range and relative ease of integration on silicon substrates make it suitable for high-speed electronic photonic integrated circuits as well as in infrared sensors.  To reduce power consumption and improve the signal-to-noise ratio, the diodes must have a low leakage current in reverse bias.  This study has investigated the leakage current of germanium photodiodes grown by low-pressure chemical vapor deposition (LPCVD) using an Applied Materials epitaxial reactor.   This study specifically looks at the effect of a post-metallization nitrogen anneal on the dark current.

To fabricate these diodes, germanium was grown epitaxially on a p+ Si substrate.  The wafers then received an in-situ cyclic anneal to reduce the threading dislocation density.  The wafers were subsequently implanted with phosphorus to create a vertical pin junction, passivated with a low temperature oxide, and contacted with metal.  Following metallization, the wafers saw an optional anneal in nitrogen for 45 minutes at varying temperatures.  Figure 1 shows the current v. voltage characteristics for a 10- x 10-μm square device at different temperatures.  The dark current is reduced from 10 μA for diodes without an anneal to 8 nA for a sample with a 400°C anneal.  To further investigate this effect, Ge-on-Si capacitors were made with LTO as their dielectric.  They were annealed at the same temperatures as the diodes.  Figure 2 shows the capacitance v. voltage measurements for different annealing temperatures.  The anneal shifts the flatband voltage to the right, indicating that the anneal changes the fixed charge in the LTO.  Without an anneal, the Ge surface is depleted, causing a high surface recombination velocity.  After an anneal at 400°C, the surface is accumulated with holes, which reduces the recombination velocity and decreases the dark current.

Uniaxial strained Ge “nanobars” are of interest for future sub-10-nm gate length p-MOSFETs because of the excellent electrostatic control afforded by the non-planar device geometry and the potential for high hole velocity in the uniaxial strained Ge.  This work investigates the fabrication technology for uniaxial strained Ge structures.  The basic approach is to pattern a biaxially strained Ge epitaxial layer grown on a relaxed SiGe substrate into a narrow nanobar.  The free surfaces of the nanobar sidewalls allow for the elastic relaxation of the lattice strain in the direction transverse to the bar, while maintaining the strain in the longitudinal direction ^[1] .   Figure 1 shows a simulation of this effect, for 11-nm-thick strained Ge grown on relaxed SiGe after patterning into a 26-nm-wide nanobar. Figure 2 shows experimental results illustrating this concept.  Raman spectroscopy was used to measure the amount of strain in the Ge nanobars for various widths that were patterned by e-beam lithography.  The Raman data is consistent with lateral relaxation and shows that the strain approaches the uniaxial limit for ~ 20-nm-wide bars.  These results are promising for the fabrication of future tri-gate type p-MOSFETs with improved transport properties.

1. P. Hashemi, L. Gomez, M. D. Robertson, M. Canonico, and J. L. Hoyt, “Asymmetric strain in nanoscale patterned strained-Si/strained-Ge/strained-Si heterostructures on insulator,” Applied Physics Letters, vol. 90, no. 8, pp. 083109, Aug. 2007.

As demands for high storage density, high chip memory capacity, and decreasing process costs continue to mount, conventional flash memory has found it challenging to continue scaling because of the minimum tunnel oxide thickness and poor charge retention due to defects in the tunneling oxide, necessitating modification in the implementation of the flash memory technology ^{[1] [2]} .

Molecular organic materials exhibit fascinating electronic properties that motivate their hybridization with traditional silicon-based memory devices in order to continue memory scaling. A floating gate consisting of a thin film of molecules would provide the advantage of a uniform set of identical nanostructured charge storage elements with high molecular area densities (e.g., 8 × 10¹³ cm^-2, which can result in a several-fold higher density of charge-storage sites as compared to QD memory and even SONOS devices) ^{[3] [4]} . Additionally, the discrete charge storage in such nano-segmented floating gate designs limits the impact of any tunnel oxide defects to the charge stored in the proximity of the defect site.

In order to study the memory behavior of organic molecules, we inject electrons/holes into the molecules by applying negative/positive bias to a conductive atomic force microscopy (AFM) tip (Pt probe tip with 10-nm radius) in contact with the organic layer (Figure 1). During the charge injection phase, the tip is brought into contact with the sample surface by reducing the amplitude setpoint to 0.5 V. The stored charges within molecules can be detected from surface potential mapping of the sample by Kelvin force microscopy (KFM). Figure 1 shows the KFM image of the charged spots by applying 9V tip bias. The minimal temporal decay of injected charges and their corresponding lateral spreading indicate highly localized charge distribution, suggesting potential use of small organic molecules in multi level trap based molecular flash memory cells with high storage capacity. The calculated stored charge density within molecules is shown in Figure 2.

1. P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells-An overview,” Proc. IEEE., vol. 85, no. 8, pp. 1248-1271,1997.
2. International Technology Roadmap for Semiconductors, ITRS. (2007). [Online]. Available: http://www.itrs.net.
3. P. K. Singh, R. Hofmann, K. K. Singh, N. Krishna, and S. Mahapatra “Performance and reliability of Au and Pt single-layer metal nanocrystal flash memory under NAND (FN/FN) operation,” IEEE Trans. Electron Devices, vol. 56, no. 9, Sep. 2009.
4. S. Paydavosi, H. Abdu, G. J. Supran, V. Bulović, “Performance Comparison of Different Organic Molecular Floating Gate Memories,” IEEE Trans. Nanotechnology, vol. 10, no. 3, May 2011.

The need for high speed and density in modern integrated circuits requires new MOSFET channel materials, techniques for improved carrier transport, and continuous scaling of the device dimensions. Strained-Ge is implemented in this work as a material for enhanced hole transport.  A high-k dielectric and metal gate stack is used for improved electrostatic control. At present, incorporating an epitaxial Si capping layer between the high-k dielectric and the Ge is the most promising approach for achieving a high quality Ge-dielectric interface, with 10x hole mobility enhancement relative to Si control devices reported for p-MOSFETs using this approach ^[1] .  However, the use of a Si-cap leads to increased Capacitance Equivalent Thickness (CET) of the structure, which degrades electrostatic control.  In addition, a Si cap provides a parasitic path for hole transport, which can deteriorate the effective hole mobility of the device at high inversion charge densities. Therefore, a process to fabricate MOSFETs by depositing a high-k dielectric directly on strained-Ge substrate should be developed and is the aim of this research.

Strained-Ge MOSFETs with and without a Si-cap were fabricated to quantitatively assess the hole mobility and its dependence on dielectric interface quality. The gate stack for all the devices was 6-nm Al₂O₃/30 nm WN.  Figure 1 shows the I-V characteristics of a strained-Ge MOSFET without a Si cap with the device cross-section shown in the inset. A very respectable on-to-off ratio is demonstrated for this long-channel (20-µm) device.  Figure 2 shows the hole mobility for the devices with and without a silicon cap, compared to the universal mobility and previous results reported by Weber et al ^[2] . The samples without a silicon cap showed relatively high hysteresis (~150 mV) and lower hole mobility than the Si-capped devices. However, the mobility enhancement observed for the sample without the Si cap is larger than reported values for relaxed or strained Ge without a Si cap ^{[3] [4]} .  This result is promising and illustrates the need for continued investigation of methods for improved passivation of the strained-Ge surface prior to direct high-k dielectric deposition.

1. M. L. Lee and E. A. Fitzgerald, “Optimized strained Si/strained ge dual-channel heterostructures for high mobility P- and N-MOSFETs,” IEDM Technical Digest, vol. 18, no. 1, pp. 1-4, 2003.
2. O. Weber, Y. Bogumilowicz, T. Ernst, J.-M. Hartmann, F. Ducroquet, F. Andrieu, C. Dupre, L. Clavelier, C. Le Royer, N. Cherkashin, M. Hytch, D. Rouchon, H. Dansas, A.-M. Papon, V. Carron, C. Tabone, and S. Deleonibus, “Strained Si and Ge MOSFETs with high-k/metal gate stack for high mobility dual channel CMOS,” in Electron Devices Meeting, 2005, pp. 137-140.
3. A. Ritenour, S. Yu, M. L. Lee, N. Lu, W. Bai, A. Pitera, E. A. Fitzgerald, D. L. Kwong, and D. A. Antoniadis, “Epitaxial strained germanium p-MOSFETs with HfO₂ gate dielectric and TaN gate electrode,” IEDM ’03 Technical Digest, vol. 18, no. 2., pp. 1-4.
4. J. Hennessy, “High mobility germanium MOSFETs: Study of ozone surface passivation and n-type dopant channel implants combined with ALD dielectrics,” Ph.D. Thesis, MIT, Cambridge, 2010.