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	<title>MTL Annual Research Report 2011 &#187; Li-Shiuan Peh</title>
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		<title>Li-Shiuan Peh</title>
		<link>http://www-mtl.mit.edu/wpmu/ar2011/li-shiuan-peh/</link>
		<comments>http://www-mtl.mit.edu/wpmu/ar2011/li-shiuan-peh/#comments</comments>
		<pubDate>Wed, 13 Jul 2011 17:26:45 +0000</pubDate>
		<dc:creator>MTL WP admin</dc:creator>
				<category><![CDATA[Faculty Research Staff & Publications]]></category>
		<category><![CDATA[Li-Shiuan Peh]]></category>

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		<description><![CDATA[On-chip networks, parallel architectures mobile computing.]]></description>
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<h3>Graduate Students</h3>
<ul>
<li>N. Agarwal, Visiting Student, EECS</li>
<li>K. Aisopos, Visiting Student, EECS</li>
<li>O. Chen, Res. Asst., EECS</li>
<li>B. Daya, Res. Asst., EECS</li>
<li>J. Gao, Res. Asst., EECS</li>
<li>E. Koukoumidis, Visiting Student, EECS</li>
<li>T. Krishna, Res. Asst., EECS</li>
<li>W. Kwon, Res. Asst., EECS</li>
<li>S. Park, Res. Asst., EECS</li>
<li>A. Sivaraman, Res. Asst., EECS</li>
</ul>
<h3>Support Staff</h3>
<ul>
<li>M. Rebelo, Admin. Asst.</li>
</ul>
<h3>Publications</h3>
<p>O. Chen, S. Park, T. Krishna and L-S. Peh, ”A Low-Swing Crossbar and Link Generator for Low-Power Networks-on-Chip,” In <em>International Conference on Computer</em>-<em>Aided Design (ICCAD)</em>, San Jose, California, November 2011.</p>
<p>K. Aisopos, O. Chen and L-S. Peh, ”Enabling System-Level Modeling of Variation-Induced Faults in Networks-on-Chip,” In <em>48th Design Automation Conference (DAC)</em>, San Diego, CA, June 2011.</p>
<p>E. Koukoumidis, L-S. Peh and M. Martonosi, “SignalGuru: Leveraging Mobile Phones for Collaborative Traffic Signal Schedule Advisory,” In <em>9th ACM International Conference</em> <em>on Mobile Systems, Applications and Services (MobiSys)</em>, Washington, DC, June 2011 (Best Paper Award).</p>
</div>]]></content:encoded>
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		<title>A Broadcast-optimized, Low-Swing Signaling-based On-Chip Network in 45nm SOI CMOS</title>
		<link>http://www-mtl.mit.edu/wpmu/ar2011/a-broadcast-optimized-low-swing-signaling-based-on-chip-network-in-45nm-soi-cmos/</link>
		<comments>http://www-mtl.mit.edu/wpmu/ar2011/a-broadcast-optimized-low-swing-signaling-based-on-chip-network-in-45nm-soi-cmos/#comments</comments>
		<pubDate>Tue, 05 Jul 2011 21:05:16 +0000</pubDate>
		<dc:creator>MTL WP admin</dc:creator>
				<category><![CDATA[Circuits & Systems]]></category>
		<category><![CDATA[Anantha Chandrakasan]]></category>
		<category><![CDATA[Li-Shiuan Peh]]></category>
		<category><![CDATA[Sunghyun Park]]></category>

		<guid isPermaLink="false">http://www-mtl.mit.edu/wpmu/ar2011/?p=3377</guid>
		<description><![CDATA[Designing on-chip networks optimized for a cache coherence protocol is critical for many-core processors to achieve peak efficiency in energy,...]]></description>
				<content:encoded><![CDATA[<div class="page-restrict-output"><p>Designing on-chip networks optimized for a cache coherence protocol is critical for many-core processors to achieve peak efficiency in energy, latency, and throughput performance. Considering that advanced cache coherence protocols<sup> [<a href="http://www-mtl.mit.edu/wpmu/ar2011/a-broadcast-optimized-low-swing-signaling-based-on-chip-network-in-45nm-soi-cmos/#footnote_0_3377" id="identifier_0_3377" class="footnote-link footnote-identifier-link" title="N. Agarwal, L.-S. Peh, and N. K. Jha, &ldquo;In-network coherence filtering: snoopy coherence without broadcast,&rdquo; IEEE/ACM International Symposium on Microarchitecture (MICRO), no. 42, pp.232-243, 2009.">1</a>] </sup><sup> [<a href="http://www-mtl.mit.edu/wpmu/ar2011/a-broadcast-optimized-low-swing-signaling-based-on-chip-network-in-45nm-soi-cmos/#footnote_1_3377" id="identifier_1_3377" class="footnote-link footnote-identifier-link" title="P. Conway, N. Kalyanasundharam, G. Donley, K. Lepak, and B. Hughes, &ldquo;Cache hierarchy and memory subsystem of the AMD Opteron processor,&rdquo; IEEE/ACM International Symposium on Microarchitecture (MICRO), no. 30, pp. 16-29, 2010.">2</a>] </sup><sup> [<a href="http://www-mtl.mit.edu/wpmu/ar2011/a-broadcast-optimized-low-swing-signaling-based-on-chip-network-in-45nm-soi-cmos/#footnote_2_3377" id="identifier_2_3377" class="footnote-link footnote-identifier-link" title="E. E. Bilir, R. M. Dickson, Y. Hu, M. Plakal, D. J. Sorin, M. D. Hill, and D. A. Wood, &ldquo;Multicast snooping: A coherence method using a multicast address network,&rdquo; IEEE/ACM International Symposium on Computer Architecture (ISCA), pp. 294-304, 1999.">3</a>] </sup> count on a combination of multicasts, broadcasts, and direct requests, it is essential to optimize on-chip networks for one-to-many multicasts and broadcasts. In addition, since such bandwidth-hungry on-chip networks consume substantial energy in their data path, energy-efficient crossbar switches and links are required.</p>
<p>This work presents broadcast-optimized, low-swing signaling-based on-chip networks. The proposed on-chip networks feature (1) multicast buffer bypassing flow control, (2) a broadcast-optimized crossbar switch, and (3) low-swing signaling in the data path. The multicast bypassing scheme generates multiple lookahead signals, one corresponding to each output port out of which the flit forks. To maximize bypassing efficiency, output port requests of the incoming lookahead signals are prioritized over the requests of other flits buffered at the same input port. When the lookahead wins all of its output ports, the intermediate router sets up the bypass control signals that allow the flit to connect directly to the crossbar and link, instead of getting buffered. For the broadcast-optimized crossbar switch and low-swing signaling in the data path, a tri-state RSD-based crossbar is presented. The proposed low-swing crossbar features (1) an inherent power gating circuit, (2) higher bandwidth driven by linear-mode RSD, (3) a longer low-swing signaling data path from cross points to link RXs, (4) SOI-friendly circuit design, and (5) potential to be integrated into the CAD synthesis flow.</p>

<a href='http://www-mtl.mit.edu/wpmu/ar2011/a-broadcast-optimized-low-swing-signaling-based-on-chip-network-in-45nm-soi-cmos/park_onchipnetworks_1/' title='Figure 1'><img width="300" height="270" src="http://www-mtl.mit.edu/wpmu/ar2011/files/2011/07/park_onchipnetworks_1-300x270.png" class="attachment-medium" alt="Figure 1" /></a>
<a href='http://www-mtl.mit.edu/wpmu/ar2011/a-broadcast-optimized-low-swing-signaling-based-on-chip-network-in-45nm-soi-cmos/park_onchipnetworks_2/' title='Figure 2'><img width="300" height="300" src="http://www-mtl.mit.edu/wpmu/ar2011/files/2011/07/park_onchipnetworks_2-300x300.png" class="attachment-medium" alt="Figure 2" /></a>

<ol class="footnotes"><li id="footnote_0_3377" class="footnote">N. Agarwal, L.-S. Peh, and N. K. Jha, “In-network coherence filtering: snoopy coherence without broadcast,” <em>IEEE/ACM International Symposium on Microarchitecture (MICRO)</em>, no. 42, pp.232-243, 2009.</li><li id="footnote_1_3377" class="footnote">P. Conway, N. Kalyanasundharam, G. Donley, K. Lepak, and B. Hughes, “Cache hierarchy and memory subsystem of the AMD Opteron processor,” <em>IEEE/ACM International Symposium on Microarchitecture (MICRO),</em> no. 30, pp. 16-29, 2010.</li><li id="footnote_2_3377" class="footnote">E. E. Bilir, R. M. Dickson, Y. Hu, M. Plakal, D. J. Sorin, M. D. Hill, and D. A. Wood, “Multicast snooping: A coherence method using a multicast address network,” <em>IEEE/ACM International Symposium on Computer Architecture (ISCA),</em> pp. 294-304, 1999.</li></ol></div>]]></content:encoded>
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