Technology scaling has enabled low-power operations in digital integrated circuits.  Therefore, the trend to move analog-to-digital operations upstream to allow more signal-processing to shift from the analog domain to the digital domain is inevitable. As most real world signals remain analog, the design of high-performance and low-power analog-digital converters (ADC) plays a key role in the success of future integrated system design. In this research, we focus on designing a (1) robust, (2) low-power, and (3) high-performance time-interleaved successive-approximation-register (SAR) ADCs. The SAR architecture is adopted because of its good digital compatibility and high energy efficiency while achieving high sampling rates.

The robustness of SAR ADCs is achieved by analyzing the effectiveness of redundancy (digital error correction) ^{[1] [2]} in improving sampling rates and its immunity from incomplete bit-settling errors. Analysis shows that the redundancy algorithm does not help improve sampling rate in all SAR ADC designs; instead, the maximum sampling rate depends on the settling time constant (τ) and the relative magnitude of the ADC delay components ^[3] . As shown in Figure 1, in order to benefit from redundancy algorithm, τ has to be more than 50ps.

The low-power operation is achieved by combining the merged capacitor switching algorithm ^[4] and split capacitive array ^[5] . The merged capacitor-switching algorithm suffers from its sensitivity to the parasitic capacitance on the outputs of the capacitive DAC. The split capacitive array suffers from 4x loss in signal power to keep voltage below the supply rail on the sub-DAC and from the mismatch problem between the fractional bridge capacitor to other capacitors in the DAC. Both issues are researched and resolved in our design. A new digital calibration scheme is developed to digitally calibrate the ADCs to resolve the mismatches and parasitic issues. Our design also incorporates an asynchronous on-chip pulse generator to avoid synchronous high-power clock distribution circuit on-chip. The overall SAR ADCs architecture is depicted in Figure 2.

1. F. Futtner, “A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13μm CMOS,” in IEEE International Solid-State Circuit Conference Digest of Technical Papers, 2002, pp. 136-137.
2. T. Ogawa, H. Kobayashi, M. Hotta, Y. Takahashi, H. San, and N. Takai, “SAR ADC Algorithm with redundancy,” in IEEE APCCAS, pp. 268-271, Nov. 2008.
3. A. H. Chang, H.-S. Lee, and D. S. Boning, “Redundancy in SAR ADCs,” in Great Lakes Symposium on VLSI, May 2011.
4. V. Hariprasath, J. Guerber, S.-H. Lee, and U.-K. Moon, “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,” Electronics Letters, vol. 46, pp. 620-621, Apr. 2010.
5. Y. Chen, X. Zhu, H. Tamura, M. Kibune, Y. Tomita, T. Hamada, M. Yoshioka, K. Ishikawa, T. Takayama, J. Ogawa, S. Tsukamoto, and T. Kuroda, “Split capacitor DAC mismatch calibration in successive approximation ADC,” in IEEE Custom Integrated Circuits Conference, 2009, pp. 279 –282.

Electromechanical resonators such as quartz crystals, surface acoustic wave (SAW) resonators, and ceramic resonators have become essential components in electronic systems. However, due to their large footprint and difficulty in integrating with CMOS processes, there has been much development in realizing microelectromechanical system (MEMS) resonators that achieve comparable performance yet have smaller footprint and are compatible with CMOS. As with other semiconductor devices, with increasing frequency and with decreasing device size into the submicron scale, variability has started to become a critical issue in MEMS resonators. However, one of the critical challenges is the lack of a characterization method that is accurate but efficient enough to be used for testing the large number of devices necessary to acquire accurate statistical distribution of the parameters of interest. This project proposes an on-chip test circuit that can accurately characterize a large number of resonators for variation analysis and that is general enough that it can be used with a wide range of resonators, not limited to specific frequencies or other properties. The proposed test circuit is based on a transient step response method using a voltage step that can accurately measure the resonant frequencies and the quality factor of devices ^[1] . The circuit employs a sub-sampling method to capture the high-frequency decay signal ^[2] and a simple analog-to-digital converter (ADC) ^[3] allowing complete digital interface, an important feature for test automation. SPICE level simulation combined with a behavioral simulation tool that was developed showed acceptable extraction errors of <1% for RS, <0.1% for Lx, <0.1% for Cx, <100 ppm for fs, and <1% for Qs. A test chip implementing the proposed test circuit has been designed and fabricated in NSC 0.18-um CMOS process.

1. M. Zhang, N. Llaser, H. Mathias, and F. Rodes, “CMOS offset-free circuit for resonator quality factor measurement,” IEEE Electronic Letters, vol. 46, no. 10, p. 706, May 2010.
2. R. Ho, B. Amrutur, K. Mai, B. Wilburn, T. Mori, and M. Horowitz, “Applications of on-chip samplers for test and measurement of integrated circuits,” in Proc. 1998 IEEE Symposium on VLSI Circuits, June, 1998, pp. 138-139.
3. E. Alon, V. Stojanović, and M. A. Horowitz, “Circuits and techniques for high-resolution measurement of on-chip power supply noise,” IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 820-828, Apr. 2005.

In this work, the virtual source (VS) charge-based compact model is validated for standard cell libraries and digital circuits. The VS model is a simple analytical ultra-compact model for deeply scaled CMOS transistors with guaranteed continuity in current, charges, and their derivatives in all operation regions ^{[1] [2]} . With only a modest number of physically meaningful parameters, the extended VS compact model includes all of the main physical effects in nanometer technologies. The VS model is verified with simulated data from a well-characterized, industrial 40-nm bulk silicon model. Standard cell library characterization is also conducted using both the VS FET model and its “golden” industrial counterpart with excellent agreement between the timing results of the two models. Finally, a 1001-stage inverter chain and a 32-bit ripple-adder are employed as test cases in a vendor CAD environment to validate the use of the VS model for large-scale digital circuit applications. Parametric V_dd sweeps show that the VS model is ready for usage in low-power design methodologies.

The first circuit we consider is an inverter undergoing trapezoidal input transitions. This basic example is used to illustrate several important features of our calibrated VS model. It is well known that the charging and discharging activities during input gate transitions require precise balancing of both static and dynamic behavior of the NFET and PFET transistors. The output voltage waveforms using the VS model in comparison with the industry-standard BSIM4 model are depicted in Figure 1. The input slew is fixed at 10ps and the load (fanout) are 1, 2, and 4. The average delay error between the VS model and the “golden” or baseline BSIM4 model is 0.88%, and the 10% -90% rising/falling time errors are 0.92%/1.11%. This timing error is a good indication of the accuracy of the transient calibration of the proposed VS model.

To further verify the calibrated VS model, a 32-bit ripple-carry adder is designed in the targeted technology (40-nm bulk CMOS), and the transient waveform of the critical path is compared using VS and BSIM4 models. The simulation environment and the SPICE convergence setting using both models are exactly the same. The test circuit includes 0.9k transistors in total belonging to various library cell types (INV, NAND, NOR and XOR). We select the worst-case delay for a 32-bit add operation. To show the robustness of the VS model for low-power design, the supply voltage V_dd is swept from 0.6V to 0.9V. The transient signals C_in0 and C_out32 at different V_dd from both VS and BSIM4 model are shown in Figure 2, which demonstrates that the output signals of the two models have excellent matching. The average delay mismatch under all V_dd conditions is about 0.3%.  The simulation we conduct achieves an average runtime speed up of 7.6X, which is in line with the order of magnitude reduction in the number of VS parameters.

1. A. Khakifirooz et al. “A simple semi-empirical short-channel MOSFET current-voltage model continuous across all regions of operation and employing only physical parameters,” IEEE Trans. on Electron Devices, pp. 1674-1680, Aug. 2009.
2. L. Wei et al. “Virtual-source-based self-consistent current and charge FET models: From ballistic to drift-diffusion velocity-saturation operation,” IEEE Trans. on Electron Devices, pp. 1-9, 2012.

Nanostructured solar cells are attracting increasing attention as a promising photovoltaic (PV) technology ^[1] . Generation of free charge carriers in nanostructured PV devices occurs at the electron donor-acceptor interface, analogous to the pn-junction interface in traditional crystalline silicon solar cells. However, recombination at this interface constitutes one of the major charge carrier loss pathways. Thus characterizing and controlling recombination dynamics is critical for informing the design of novel device architectures. Recombination parameters also enable comparisons between different device architectures.

In this work, we employ the transient photovoltage (TPV) technique ^[2] to probe recombination mechanisms under standard operating conditions in three different solar cells, as shown in Figure 1: a poly(3-hexylthiophene) and phenyl-C₆₁-butyric acid methyl ester (P3HT:PCBM) bulk heterojunction; a chloroaluminium phthalocyanine and fullerene (ClAlPc:C₆₀) planar mixed heterojunction; and a lead sulfide quantum dot and zinc oxide (QD PbS:ZnO) pn-heterojunction. The normalized TPV data acquired at 0.5-sun illumination intensity are shown in Figure 2a, which compares the recombination lifetimes of charge carriers in these devices. The observed differences in carrier lifetimes may arise from variations in the respective interface morphologies: for example, the slower recombination transients observed in the ClAlPc:C₆₀ device may be attributed to the intrinsic planarity of this particular architecture.  We can also measure the charge carrier lifetime as a function of the light intensity, as shown in Figure 2b; this result confirms that recombination dynamics are faster in P3HT:PCBM and QD PbS:ZnO than in ClAlPc:C₆₀ PV devices.

1. Anonymous, “A sunny outlook,” Nature Photonics, vol. 6, no. 3, p. 129, Mar. 2012.
2. C. G. Shuttle, B. O’Regan, A. M. Ballantyne, J. Nelson, D. D. C. Bradley, J. de Mello, and J. R. Durrant, “Experimental determination of the rate law for charge carrier decay in a polythiophene: Fullerene solar cell,” Applied Physics Letters, vol. 92, p. 3, 2008.

Designing a low-power wireless communication system involves two major milestones: use of very efficient RF architectures, including circuits for power amplifiers, mixers, etc., as well as employing the appropriate protocol-level algorithms, such as forward error correction (FEC) codes, CRCs, etc. Although these two steps are usually performed in isolation, the result has been extremely successful for designing efficient long-distance communication systems. However, this approach is highly suboptimal for short-range communication systems (i.e., Body Area Networks), where the power consumption of these two components can be comparable ^[1] . For this reason, very careful, system-level analysis is required to achieve the minimum energy consumption in transmitting the required information.

We have designed a flexible, ultra-low-power ISM-band transmitter, including baseband processing and basic protocol functionality (i.e., packetization, CRC calculation), using a 65-nm TSMC process. The simplistic block diagram of the transmitter is shown in Figure 1. The fabricated chip includes four memory banks to store incoming data, a tunable convolutional encoder optimized for short-distance RF modules, and an RF transmitter that utilizes a high-Q FBAR resonator as a local oscillator ^[2] . The transmitter has an output power of ~-10dBm and supports 1Mbps OOK and FSK modulation.  An on-chip FIR filter implements Gaussian pulse shaping for GFSK modulation. In addition to the FEC code, the transmitter has a dedicated accelerator implementing a new form of coding, called network coding (NC) ^[3] , which can increase the reliability of the communication system under challenged channel conditions and potentially reduce the required amount of energy communicating information.

Figure 1: Simplistic block diagram of our ultra-low-power ISM-band transmitter.

1. P. Grover, K. Woyach, and A. Sahai, “Towards a communication-theoretic understanding of system-level power consumption,” IEEE Journal on Selected Areas in Communications, vol. 29, no. 8, pp. 1744-1755, Sept. 2011.
2. A. Paidimarri, “Architecture for ultra-low powermulti-channel transmitters for body area networks using RF Resonators,” Master’s thesis, Massachusetts Institute of Technology, Cambridge, 2011.
3. R. Koetter and M. Medard, “An algebraic approach to network coding,” IEEE/ACM Transactions on Networking, vol. 11, no. 5, pp. 782- 795, Oct. 2003.

This work focuses on using gallium nitride (GaN) FETs for an LED lighting system. The idea is to utilize the favorable figure of merit provided by the GaN technology to miniaturize the magnetic components in the power converter by using high switching frequencies for the power converter. An LED driver application is chosen because the lighting industry is expected to see substantial growth in the near future with the advent of high-efficiency LEDs. This project will demonstrate a high-efficiency, small form factor LED lighting system with a long lifetime that can replace incandescent bulbs or CFLs. Efforts aim for design and implementation of high power density, off-line, high-frequency power conversion and control circuits.

The drivers are being implemented on a CMOS die. This will directly interface with discrete commercial GaN power devices. Circuits to perform power factor correction and dimming control are also being designed. Since the system will interface directly with the AC mains, an EMI filter is being used with the rectifier. Figure 1 shows the high-level block diagram of the system envisioned.

Figure 1: Block diagram of LED driver.

Advancements in low-power electronics have opened up many opportunities to provide healthcare solutions through continuous, unobtrusive sensing of vital physiological signs. Power budgets and, by extension, size and cost of such sensors are now dominated by the communication costs, which have not scaled as rapidly ^[1] . We are working on a topology and associated protocols customized for such networks that relax power requirements enough for the network itself to power sensors.

The network consists of clothing made from e-textiles containing a number of strategically-placed inductors screen-printed using a silver paste ^[2] . Sensor Nodes (SNs) can be placed beneath any number of inductors. Power is transferred from the central Base Station (BS) to the SNs in the 27-MHz ISM band, which eliminates the need for bulky energy sources at each SN. Data from the SN is transferred at 1 Mbps through an impedance modulation link, similar to RFID, and is perceived as an ASK waveform by the BS. The high data rate allows each SN to have a very low transmit duty cycle (~1-2 %).

The medium-access protocol is designed to minimize the decision-making burden on the SN. Upon configuring the network, each SN is classified as a “Stream” mode (e.g., EKG, EEG) sensor or a “Contention Access (CA)” mode (e.g., blood pressure, glucose) sensor, which sends data infrequently. The BS assigns fixed timeslots to each stream-mode sensor. Once it has looped through all such sensors, it opens a CA period for the other sensors in the network. The protocol ensures that an SN always waits for a signal from the BS before transmitting and renders synchronization routines, such as the one presented in ^[3] , unnecessary.

1. N. Verma,  A, Shoeb, J. Bohorquez,  J. Dawson, J. Guttag, and A. P. Chandrakasan, “A micro-power EEG acquisition SoC with integrated feature extraction processor for a chronic seizure detection system,” IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 804-816, Apr. 2010.
2. K. Yongsang, K. Hyejung, and Y. Hoi-Jun, “Electrical characterization of screen-printed circuits on the fabric,” IEEE Transactions on Advanced Packaging, vol. 33, no. 1, pp. 196-205, Feb. 2010.
3. O. Omeni, A. Wong, A. J. Burdett, and C. Toumazou, “Energy efficient medium access protocol for wireless medical Body Area SSensor Networks,” IEEE Transactions on Biomedical Circuits and Systems, vol.2, no. 4, pp. 251-259, Dec. 2008.

Continuous tracking of neurological disorders is crucial for the proper diagnosis and medication of epilepsy, and it mandates the design of ultra-low power sensor with a small form factor and continuous EEG classification. The main challenges arise from three factors: 1) variation in seizure pattern from person to person and age to age; 2) the need for wide dynamic range, low-noise AFE with high CMRR; and 3) the area overhead of integrating classification processor to enable seizure monitoring, detection, and storage in one chip. We present an ultra-low-power scalable EEG acquisition SoC for continuous seizure detection and recording with fully integrated patient-specific Support Vector Machine (SVM)-based classification processor. The proposed SoC is composed of 8 high-dynamic range Analog Front-End (AFE) channels, an SRAM and a patient-specific machine-learning seizure classification processor with a Feature Extraction (FE) Engine and a Classification Engine (CE).  Each channel in the AFE integrates a Chopper-Stabilized Capacitive Coupled Instrumentation Amplifier (CS-CCIA) followed by an Analog Signal Processing Unit (ASPU). The SoC maintains high-accuracy seizure detection while minimizing the area overhead of the FE Engine by operating in two separate modes for seizure detection and recording. In seizure detection mode, the AFE uses a bandwidth of 30Hz with a 4-step adapted channel gain according to the signal strength. Once seizure is classified, the SoC automatically runs in seizure-recording mode at 100Hz bandwidth to store the EEG data in the internal SRAM.  Digital filters are implemented using Distributed Quad-LUT (DQ-LUT) architecture, which enables area reduction for full integration of the classification processor. The SoC shows a detection accuracy of 84.4% in a rapid eye blink test while consuming 2.03μJ/classification.

1. J. Yoo, L. Yan, D. El-Damak, M. A. Altaf, A. Shoeb, H.-J. Yoo, and A. P. Chandrakasan, “An 8-channel scalable EEG acquisition SoC with fully integrated patient-specific seizure classification and recording processor,” IEEE Intl. Solid-State Circuits Conference Dig.Tech. Papers, Feb. 2012, pp. 292–293.

The ever-increasing demand for richer internet video content and larger video resolution has motivated work on algorithms that achieve higher compression without sacrificing visual quality. High Efficiency Video Coding (HEVC) ^[1] is being developed by the Joint Collaborative Team on Video Coding as a successor to the popular H.264/MPEG-4 AVC standard. For the same quality, HEVC aims for a 50% bit-rate savings over AVC. This improvement comes at the cost of larger coding units, increased complexity through the addition of new coding tools, and increased computation in existing tools.

Key features of HEVC include hierarchical coding structures of sizes 64×64 down to 8×8 pixels, 36 intra-prediction modes, asymmetric motion partitions, large and non-square transforms, and multiple concatenated loop filters. This work aims at developing a new system architecture for the hierarchical coding structure along with novel designs for the coding tools themselves. A hybrid system pipeline structure is proposed to support all three largest coding units. The transform block uses SRAM-based 2-D transpose memory and leverages DCT matrix properties for extensive resource-sharing techniques for area reduction. External memory bandwidth and power are major concerns for high definition video decoding. These goals are addressed by a novel cache design with 2-D memory mapping and high throughput.

An HEVC video decoder chip capable of real time Quad Full HD (3840×2160) at 30 fps has been implemented. The decoder supports the HEVC Test Model HM-4.0 with low-complexity entropy coding and both low-delay and random-access encoding profiles.

Figure 1: Hierarchical coding structure of HEVC.

1. B. Bross, W.-J. Han, J.-R. Ohm, G. J. Sullivan, and T. Wiegand, “High efficiency video coding (HEVC) text specification draft 6,” ITU-T SG16 WP3 and ISO/IEC JTC1/SC29/WG11 document JCTVC-H1003, Joint Collaborative Team on Video Coding, San Jose, CA, Feb. 2012.

An ultrasound image is formed from a collection of ultrasonic beams transmitted and received by an array of transducer elements.  As the resolution of an image and the range over which an image is to be formed increase, so do the number of these transducer elements and the corresponding digital processing units.  The intensive signal processing power required for ultrasound imaging ^[1] means that conventional ultrasound systems are often large and expensive, and this demand for processing power can only worsen as more transducers and signal channels are implemented.  In applications such as point-of-care diagnostics in rural areas, the movement to a portable and low-power ultrasound imaging system is warranted.

Beamforming, which in its simplest form involves delaying, scaling, and summing to produce a coherent signal from the collection of received beams, has been identified as an area for algorithmic research and development ^[2] .  In this work, an 8-channel wide, scalable digital beamformer is implemented with feedback for power reduction.  Two modes of operation are available: coarse and fine beamforming.  In the coarse beamforming mode, digitized data from an evenly spaced subset of transducer elements are processed, providing a low-quality image of the full region of interest, which yields power savings by turning off the analog front end electronics and analog-to-digital converters corresponding to the unused 50% or 75% of array channels (schematically shown in Figure 1).  Figures 2a and b show the coarse images for quarter and half resolution coarse beamforming modes.  Next, the user can specify a smaller region in which a higher quality image is desired, which is then beamformed by the same 8-channel wide processing unit using all available channels (an example of the full region full resolution image is shown in Figure 2c).

1. M. Ali, D. Magee, and U. Dasgupta, “Signal processing overview of ultrasound systems for medical imaging,” Texas Instruments, Dallas, TX, SPRAB12, 2008.
2. S. Stergiopoulos, Advanced Signal Processing Handbook: Theory and Implementation for Radar, Sonar, and Medical Imaging Real-Time Systems.  Boca Raton: CRC Press, Inc., 2000.