In our previous work on CMP modeling, we developed an original physical die-level model to understand the pattern density dependence of planarization since it is known to be the dominant effect of die-level non-uniformity ^[1] . However, a significant variation with layout feature size is also observed in oxide CMP ^[2] . A recent modeling improvement focuses on feature size effects based on empirical die-level models ^[3] . A physically-based die-level model including both pattern density and feature size effects is desired.

To understand the feature size effect, an extended physical die-level model is developed by considering the interactions between CMP pad asperities and step features on a chip. The extended die-level model attributes feature size dependence on pad asperity size and asperity shape. As shown in Figure 1, although both features have same pattern density, small feature planarization is faster than in large features because no down area removal occurs until a late polishing stage. Since the shape of a step feature during CMP is not ideal due to the structure corner roll off, a parabolic shape approximation can be made to utilize the Greenwood-Williamson approach including the curvature of up and down areas of each feature ^[3] . Then Hertzian contact theory ^[4] is applied to calculate pressure distribution, and Preston’s law ^[5] is used to estimate the die-level topography evolution during the CMP process. A full-chip simulation on an MIT standard STI CMP test layout shows that small features are planarized faster than large features (Figure 2), even though they have same pattern density.

1. X. Xie, “Physical understanding and modeling of chemical mechanical planarization in dielectric materials,” Ph.D. thesis, Massachusetts Institute of Technology, Cambridge, 2007.
2. R. Rzehak, “Pitch-dependence in oxide CMP,” in Proc. Eleventh International Conference on Chemical-Mechanical Polish Planarization for ULSI Multilevel Interconnection (CMP-MIC), 2006, p. 137.
3. B. Vasilev, R. Rzehak, S. Bott, P. Kucher, and J. W. Bartha, “Greenwood-Williamson model combining pattern-density and pattern-size effects in CMP,” IEEE Transactions On Semiconductor Manufacturing, vol. 24, no. 2, pp. 338-347, May 2011.
4. K. L. Johnson, Contact Mechanics. Cambridge: Cambridge University Press, 1985.
5. F. Preston, “The theory and design of plate glass polishing machines,” Journal of the Society of Glass Technology, vol. 11, pp. 214-256, 1927.

Self-assembled block copolymer structures are useful in nanolithography applications, producing patterns with high resolution and throughput. We previously showed control over the direction of in-plane cylindrical microdomains formed by self-assembly of a block copolymer (BCP) using a variety of physical templates made from hydrogen silsesquioxane (HSQ) resist ^{[1] [2]} . The HSQ templates were fabricated by electron-beam lithography and then functionalized with a minority or majority block brush to interact with the BCP and direct the self-assembly (as shown in Figure 1). However, HSQ templates were not easily removed and remained as part of the final pattern. Remaining HSQ caused non-uniform pattern transfer due to dissimilar etch rates between the BCP and HSQ. In this study, we solved this issue by using a removable-resist template coated with an etchable-block brush. We fabricated two- and three-dimensional BCP patterns and then removed the templates. Examples (Figure 2) include three-dimensional bends, junctions and mesh-shaped structures, and the ability to change the BCP morphology through templating.

The negative-tone-post templates were made by electron-beam lithography of poly (methyl methacrylate) (PMMA) resist at high dose (100-600 pC/pixel). After development of patterns using methyl isobutyl ketone (MIBK) and acetone ultrasonication, the surface of the patterns was coated with hydroxyl-terminated polystyrene (PS) brush (1 kg mol^-1). Then poly(styrene-b-dimethylsiloxane) (PS-b-PDMS) BCP (MW=45.5 kg mol^-1, f_PDMS=0.32, period 35 nm) was spun and solvent annealed with a mixture of heptane and toluene. CF₄ and O₂ reactive ion etch (RIE) was used to remove the top PDMS layer and the PS matrix.  The O₂ RIE not only removed not only the PS matrix but also removed the PMMA template in the same step. The final results were in-plane oxidized-PDMS cylindrical microdomain patterns in the form of two- and three-dimensional structures devoid of templates. This study provides a path to complex pattern formation for nanolithography with feature sizes below 20 nm.

1. Yang, J. K. W. et al. Nature Nanotechnology 5, 256-260, 2010.
2. Duan H. et al. Journal of Vacuum Science and Technology B 28 C6C58-C6C62, 2010.

Strained-Ge MOSFETs with significantly enhanced mobility compared to Si/SiO₂ hole mobility have previously been reported by our group (see Figure 1).  To enable use of these enhanced channel materials in future nanoscale gate-length FETs, the equivalent oxide thickness (EOT) must be scaled, and improved dielectric/semiconductor interface properties are required. In the search for  suitable gate dielectrics for use with Ge, bilayer dielectric systems have been investigated.  The bottom layer in these systems is expected to provide a high-quality interface to the semiconductor while the top layer is a high-k dielectric used to reduce the overall EOT and gate leakage of the structure.  An Al₂O₃/TiO₂ dielectric system with a sub-nm EOT and low density of interface states on bulk Ge wafers has been demonstrated ^[1] , and its implementation with strained-Ge devices is the aim of this work. Due to the limited thermal budget associated with the bilayer dielectric/metal gate stack, a gate-last process is developed.

In the gate-last process, the source and drain regions are activated before the gate dielectric and gate metal are deposited.  This is done to improve device reliability and mobility at scaled EOT, which can be significantly degraded when the high-k dielectric has gone through the high-temperature steps. Figure 2 shows the schematic gate-last process flow as well as the mask layout of the designed MOSFET structure. The preliminary experiments on gate-last Si MOSFETs show a superior interface quality compared to gate-first devices, a promising result in favor of gate-last strained-Ge MOSFETs, at least as a means of studying the dielectric/semiconductor interface.

1. S. Swaminathan. M.  Shandalov, Y.  Oshima, and P. C.  McIntyre, “Bilayer metal oxide gate insulators for scaled Ge-channel metal-oxide-semiconductor devices,” Applied Physics Letters, vol. 96, no. 8, pp. 082904-082904-3, Feb. 2010.

Compact models for GaN based HEMTs describing the voltage-dependent terminal currents are essential for circuit simulations.  In this work, we extend the virtual-source (VS)-based transport model ^[1] originally developed for Si MOSFETs to GaN based HEMTs along with models for non-linear access regions and device self-heating. The model is suitable for quasi-ballistic or fully ballistic short channel devices typically used for RF and mixed-signal applications. The model has been implemented in Verilog-A language.

Access region behavior is analyzed by measuring I-Vs of TLM structures that represent those transistor access regions. Velocity versus field plot obtained from the I-Vs is shown in Figure 1. The velocity undergoes quasi-saturation at a field of about 5 KV/cm, which is lower than in ^[2] . The quasi-saturation is attributed to velocity saturation and self-heating. Access regions are modeled as non-linear resistors to capture this effect. The intrinsic transistor region is modeled using the VS model including self-heating in the channel. The developed model is compared against DC measurements of a short channel RF HEMT. The device has a gate length of 105 nm, access region lengths of 0.5 µm, and device structure as reported in ^[3] . DC characteristics obtained from the model and measurements are shown in Figure 2. The model gives a good match to the measurements, as Figure 2 shows. Results show that the access regions rather than the intrinsic channel region limit the maximum current in output characteristics. Access regions also cause reduction of transconductance (g_m) with gate voltage after reaching a peak value. The compact model captures these effects well.  The g_m estimated from the model along with gate capacitances would enable estimation of f_T and make projections for future scaling of GaN based HEMTs.

1. A. Khakifirooz, O. M. Nayfeh, D. Antoniadis, “A simple semiempirical short-channel MOSFET current–voltage model continuous across all regions of operation and employing only physical parameters,” IEEE Transactions on Electron Devices, vol.56, no.8, pp.1674-1680, Aug. 2009.
2. L. Ardaravicius, A. Matulionis, J. Liberis, O. Kiprijanovic, M. Ramonas, L. F. Eastman, J. R. Shealy, A. Vertiatchikh, “Electron drift velocity in AlGaN/GaN channel at high electric fields,” Applied Physics Letters , vol.83, no.19, pp.4038-4040, Nov. 2003.
3. D. S.  Lee, X.  Gao, S. Guo, T. Palacios, “InAlN/GaN HEMTs with AlGaN back barriers,” Electron Device Letters, IEEE, vol.32, no.5, pp.617-619, May 2011.

Given recent advances in the field of global optimization, we aim to make advances towards deterministic global optimization of some important engineering systems (namely, multilayer filters, lens systems, and semiconductors),. The design of these systems is an activity popularly regarded as an art, and it may potentially be turned into a science using the deterministic global optimization technique of branch-and-bound. The technique of branch-bound is briefly illustrated in Figure 1 below.

Figure 1: An illustration of the technique of branch-and-bound.

As Figure 1 shows, this methodology requires the cheap construction of tight bounds on the merit function defining each optimization problem. With the recent availability of extensively verified and parallelizable software for suppressing the dependency problem (using the technique of Taylor arithmetic) arising in attempts to bound explicit merit functions (of sufficient differentiability), we aim to identify the subset of the important classes of multilayer filters and lens systems accessible by rigorous global optimization. Given recent advances in mathematical theory for constructing parametric bounds on ODE solutions (in particular, suppressing the wrapping effect using the technique of generalized McCormick Relaxations), we have developed a mathematical methodology for constructing parametric bounds on semilinear parabolic PDE solutions. The specific long-term goal of the PDE work is rigorous global optimization of semiconductors. The project is presently in the supercomputing software development phase. Preliminary serial work in the domain of multilayer filters yielded an important broadband omnidirectional antireflection coating design for silicon solar cells. Work is in progress to experimentally demonstrate this design.

In recent years, several ion-trapping groups have shown that microwave electrodes integrated into surface electrode ion traps can be used for state manipulation of trapped ions ^[1] . Our group has pursued integrating microwave electrodes into superconducting ion traps to perform microwave spectroscopy in both atomic and molecular ions. Large fields are required to perform state manipulation, and these fields can be locally amplified using resonators. This amplification comes at the expense of bandwidth on the spectroscopic signal.

We designed microwave-integrated ion traps and fabricated them with a niobium on A-plane sapphire process in the Nanostructures Laboratory at MIT. We deposited thin films between 50-200 nm of niobium on the sapphire with an in-house DC magnetron sputtering system. Once we completed the material stack, we patterned the front niobium layer in PR1-2000A resist using the Heidelberg uPG-101 pattern generator, developed it, and then reactive-ion etched it with CF4 and O2 to transfer the pattern into the niobium

We are currently testing to see if our integrated microwave signals can excite the microwave clock transition in ⁸⁷Sr⁺ ions. This experiment uses microwave signals to couple between two hyperfine levels in the ground state of ⁸⁷Sr⁺. A laser excites the atom from one of the ground states to an excited state; when the atom decays back to one of the ground states, photons are emitted, and they can be imaged. Without the applied microwaves, the ion would quickly shelve into a dark state.

1. Ospelkaus, C., Warring, U., Colombe, Y., Brown, K.R., Amini, J.M., Leibfried, D., Wineland, D.J., “Microwave quantum logic gates for trapped ions,” Nature, vol. 476, no. 7359, pp. 181-184, 2011.

In this research we seek to develop acousto-optic, guided-wave modulators in proton-exchanged lithium niobate for use in holographic and other high-bandwidth displays.  Guided-wave techniques make possible the fabrication of modulators that are higher in bandwidth and lower in cost than analogous bulk-wave acousto-optic devices.  In particular, we are investigating multichannel variants of these devices with an emphasis on maximizing the number of modulating channels to achieve large total bandwidths.  Efficient, low-cost, monolithic modulators capable of modulating billions of pixels/sec should be possible.

1. C. S. Tsai, Q. Li, and C. L. Chang, “Guided-wave two-dimensional acousto-optic scanner using proton-exchanged lithium niobate waveguide,” Fiber and Integrated Optics, vol. 17, pp. 57-166, 1998.
2. D. Smalley, “High-resolution spatial light modulation for holographic video,” Master’s thesis, Massachusetts Institute of Technology, Cambridge MA, 2008.
3. D. E. Smalley, Q. Y. J. Smithwick, and V. M. Bove, Jr., “Holographic video display based on guided-wave acousto-optic devices,” Proc. SPIE Practical Holography XXI, 2007, vol. 6488, p. 64880L.
4. J. Barabas, S. Jolly, D. E. Smalley, and V. M. Bove, Jr., “Diffraction specific coherent panoramagrams of real scenes,” Proc. SPIE Practical Holography XXV, 2011, vol. 7957, p. 795702.

Thin-film solar cells incorporating colloidal quantum dot active layers have recently emerged as a notable third-generation photovoltaic (PV) technology, largely due to the strong absorption, tunable infrared bandgap, and ambient-atmosphere stability of lead sulfide quantum dots (PbS QDs). Photoactive PbS QDs can be solution-deposited on a transparent zinc oxide (ZnO) film to form a depleted np-heterojunction device (Figure 1a,b). However, this standard planar architecture incurs a fundamental trade-off between light absorption and carrier collection: to absorb most incident light, we need a ~1-µm-thick QD film ^[1] , but to collect most photocarriers, we need absorption to occur within a minority carrier diffusion length (~100 nm) of the ~150-nm-thick depletion region ^[2] . By introducing 1-D nanostructures (Figure 1c), we can decouple these parallel requirements and optimize for each independently. A vertical, QD-infiltrated array of ZnO nanowires orthogonalizes the mechanistic length scales of absorption and collection. Absorption is maximized as light traverses a thick QD film in the axial direction, while field-driven carrier collection is retained throughout the film as photogenerated electrons drift to nearby PbS/ZnO interfaces in the radial direction.

Our research demonstrates that moving from a planar ZnO film to a nanowire array can significantly improve QDPV performance, increasing short-circuit current density (J_SC) by ~40% and overall power conversion efficiency by ~15% ^[3] . We confirm the near-complete infiltration of PbS QDs into the ZnO nanowire array via cross-sectional scanning electron microscopy (Figure 1d) and elemental mapping with energy-dispersive x-ray spectroscopy. We further demonstrate a fast solution treatment to assist interfacial charge transfer using a bifunctional linker molecule, 3-mercaptopropionic acid (MPA). A simple MPA treatment increases both J_SC and open-circuit voltage (V_OC) of nanowire-QD devices (see Figure 2). Our work on ZnO nanowire-based QD solar cells—along with the recent demonstration of a 5.6%-efficient TiO₂nanopillar-based QDPV ^[4] —suggests that 1-D nanostructures may be the key to enhancing the efficiency and hence the economic viability of quantum dot photovoltaics.

1. A. G. Pattantyus-Abraham,I. J. Kramer, A. R. Barkhouse,X. Wang, G.Konstantatos, R. Debnath,L. Levina,I. Raabe,M. K. Nazeeruddin, M.Grätzel, and E. H. Sargent, “Depleted-heterojunction colloidal quantum dot solar cells,” ACS Nano, vol. 4, no. 6, pp. 3374-3380, May 2010.
2. K. W. Johnston, A. G. Pattantyus-Abraham, J. P. Clifford, S. H. Myrskog, S. Hoogland, S. Sjoerd, H. Shukla, E. J. D. Klem, L. Levina, and E. H. Sargent, “Efficient Schottky-quantum-dot photovoltaics: The roles of depletion, drift, and diffusion,” Applied Physics Letters, vol. 92, no. 12, pp. 122111, Mar. 2008.
3. P. R. Brown, R. R. Lunt, N. Zhao, T. P. Osedach,D. D. Wanger, L.-Y.Chang, M. G.Bawendi, and V. Bulović, “Improved current extraction from ZnO/PbS quantum dot heterojunction photovoltaics using a MoO₃ interfacial layer,” Nano Letters, vol. 11, no. 7, pp. 2955-2961, June 2011.
4. I. J. Kramer, D. Zhitomirsky, J. D. Bass, P. M. Rice, T. Topuria, L. Krupp, S. M. Thon, A. H. Ip, R. Debnath, H.-C. Kim, and E. H. Sargent, “Ordered nanopillar structured electrodes for depleted bulk heterojunction colloidal quantum dot solar cells,” Advanced Materials, vol. 24, no. 17, pp. 2315-2319, Mar. 2012.

Nanostructured solar cells are attracting increasing attention as a promising photovoltaic (PV) technology ^[1] . Generation of free charge carriers in nanostructured PV devices occurs at the electron donor-acceptor interface, analogous to the pn-junction interface in traditional crystalline silicon solar cells. However, recombination at this interface constitutes one of the major charge carrier loss pathways. Thus characterizing and controlling recombination dynamics is critical for informing the design of novel device architectures. Recombination parameters also enable comparisons between different device architectures.

In this work, we employ the transient photovoltage (TPV) technique ^[2] to probe recombination mechanisms under standard operating conditions in three different solar cells, as shown in Figure 1: a poly(3-hexylthiophene) and phenyl-C₆₁-butyric acid methyl ester (P3HT:PCBM) bulk heterojunction; a chloroaluminium phthalocyanine and fullerene (ClAlPc:C₆₀) planar mixed heterojunction; and a lead sulfide quantum dot and zinc oxide (QD PbS:ZnO) pn-heterojunction. The normalized TPV data acquired at 0.5-sun illumination intensity are shown in Figure 2a, which compares the recombination lifetimes of charge carriers in these devices. The observed differences in carrier lifetimes may arise from variations in the respective interface morphologies: for example, the slower recombination transients observed in the ClAlPc:C₆₀ device may be attributed to the intrinsic planarity of this particular architecture.  We can also measure the charge carrier lifetime as a function of the light intensity, as shown in Figure 2b; this result confirms that recombination dynamics are faster in P3HT:PCBM and QD PbS:ZnO than in ClAlPc:C₆₀ PV devices.

1. Anonymous, “A sunny outlook,” Nature Photonics, vol. 6, no. 3, p. 129, Mar. 2012.
2. C. G. Shuttle, B. O’Regan, A. M. Ballantyne, J. Nelson, D. D. C. Bradley, J. de Mello, and J. R. Durrant, “Experimental determination of the rate law for charge carrier decay in a polythiophene: Fullerene solar cell,” Applied Physics Letters, vol. 92, p. 3, 2008.

Deeply scaled III-V MOSFETs have demonstrated logic performance at 0.5 V, exceeding that of Si ^[1] . The gate length of modern III-V MOSFETs has been recently reduced to sub-100-nm dimensions.  However, the actual contacts in current research devices still are many times larger than this. Going forward, a key element for a high-performance, small-footprint III-V CMOS technology is the achievement of nanometer-scale source and drain contacts with low contact resistance. This goal is challenging because as the contact length decreases to the nanometer regime, the contact resistance is expected to increase dramatically. This study focuses on characterizing nanometer-scale metal contacts to III-V heterostructures.

We have first developed a fabrication process to build nano-TLM structures with different contact length (L_c) and spacing (d). We have used Mo contacts to an InGaAs-based heterostructure. Mo definition was achieved by electron-beam lithography followed by dry etching. The mesa and contact pads were formed using photo lithography and a series of dry etching and lift off processes. Figure 1 shows a fabricated nano-TLM structure with ~160-nm contact length and a spacing of ~440 nm. The devices are being characterized using Kelvin (4-terminal) measurements. The sheet resistance of Mo film needs to be considered because the film thickness is decreased to ~50 nm. The contact resistance (R_c) and metal sheet resistance (R_shm) can be extracted using an equivalent circuit model developed for this specific nano-TLM structure. In the future we will expect to integrate nano-scale ohmic contact into a III-V CMOS process, with the goal of reducing transistor footprint and provide insight into the limitations that nano-scale contacts impose on transistor characteristics.

Figure 1: Plan view image of a nano-TLM structure with ~160-nm contact length Mo contacts about ~440 nm apart.

1. J. A. del Alamo, “Nanometre-scale electronics with III-V compound semiconductors,” Nature, vol. 479, no. 7373, pp. 317-323, Nov. 2011.