polyzoeva_mosfets_02

Figure 2: Schematic gate-last process flow and mask layout of the MOSFET structure. The S/D regions are activated prior to gate dielectric/metal gate deposition to avoid high-k degradation during the high-temperature step.

  • Tags

    ahmed al-obeidi akintunde akinwande anantha chandrakasan brian wardle carl thompson caroline ross center for excitonics charles sodini clifton fonstad dana weinstein dimitri antoniadis duane boning eugene fitzgerald farnaz niroui frances hill gallium nitride gang chen graphene hae-seung lee harry tuller healthcare iii-v materials jeffrey lang jesús del alamo jing kong joel voldman jongyoon han judy l. hoyt karl berggren lionel kimerling luca daniel luis velasquez-garcia marc baldo mildred dresselhaus pablo jarillo-herrero pao lin patrick brown qing hu sang-gook kim silvija gradecak tomas palacios vladimir bulovic vladimir stojanovic yu-chung hsiao zohaib mahmood