sinangil_sram_01

Figure 1: (a) Simulated memory maps for an 8k-bit memory at 250mV show that 8T with WA has fewer errors (b) The side length of the largest square that can fit inside the lobes of a butterfly curve gives the hold margin. (c) Measured energy per operation per bit decreases by ~10X by voltage scaling from 1.2V to 0.4V (d) 8T bit-cell

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