Designing a low-power wireless communication system involves two major milestones: use of very efficient RF architectures, including circuits for power amplifiers, mixers, etc., as well as employing the appropriate protocol-level algorithms, such as forward error correction (FEC) codes, CRCs, etc. Although these two steps are usually performed in isolation, the result has been extremely successful for designing efficient long-distance communication systems. However, this approach is highly suboptimal for short-range communication systems (i.e., Body Area Networks), where the power consumption of these two components can be comparable ^[1] . For this reason, very careful, system-level analysis is required to achieve the minimum energy consumption in transmitting the required information.

We have designed a flexible, ultra-low-power ISM-band transmitter, including baseband processing and basic protocol functionality (i.e., packetization, CRC calculation), using a 65-nm TSMC process. The simplistic block diagram of the transmitter is shown in Figure 1. The fabricated chip includes four memory banks to store incoming data, a tunable convolutional encoder optimized for short-distance RF modules, and an RF transmitter that utilizes a high-Q FBAR resonator as a local oscillator ^[2] . The transmitter has an output power of ~-10dBm and supports 1Mbps OOK and FSK modulation.  An on-chip FIR filter implements Gaussian pulse shaping for GFSK modulation. In addition to the FEC code, the transmitter has a dedicated accelerator implementing a new form of coding, called network coding (NC) ^[3] , which can increase the reliability of the communication system under challenged channel conditions and potentially reduce the required amount of energy communicating information.

Figure 1: Simplistic block diagram of our ultra-low-power ISM-band transmitter.

1. P. Grover, K. Woyach, and A. Sahai, “Towards a communication-theoretic understanding of system-level power consumption,” IEEE Journal on Selected Areas in Communications, vol. 29, no. 8, pp. 1744-1755, Sept. 2011.
2. A. Paidimarri, “Architecture for ultra-low powermulti-channel transmitters for body area networks using RF Resonators,” Master’s thesis, Massachusetts Institute of Technology, Cambridge, 2011.
3. R. Koetter and M. Medard, “An algebraic approach to network coding,” IEEE/ACM Transactions on Networking, vol. 11, no. 5, pp. 782- 795, Oct. 2003.

This work focuses on using gallium nitride (GaN) FETs for an LED lighting system. The idea is to utilize the favorable figure of merit provided by the GaN technology to miniaturize the magnetic components in the power converter by using high switching frequencies for the power converter. An LED driver application is chosen because the lighting industry is expected to see substantial growth in the near future with the advent of high-efficiency LEDs. This project will demonstrate a high-efficiency, small form factor LED lighting system with a long lifetime that can replace incandescent bulbs or CFLs. Efforts aim for design and implementation of high power density, off-line, high-frequency power conversion and control circuits.

The drivers are being implemented on a CMOS die. This will directly interface with discrete commercial GaN power devices. Circuits to perform power factor correction and dimming control are also being designed. Since the system will interface directly with the AC mains, an EMI filter is being used with the rectifier. Figure 1 shows the high-level block diagram of the system envisioned.

Figure 1: Block diagram of LED driver.

Advancements in low-power electronics have opened up many opportunities to provide healthcare solutions through continuous, unobtrusive sensing of vital physiological signs. Power budgets and, by extension, size and cost of such sensors are now dominated by the communication costs, which have not scaled as rapidly ^[1] . We are working on a topology and associated protocols customized for such networks that relax power requirements enough for the network itself to power sensors.

The network consists of clothing made from e-textiles containing a number of strategically-placed inductors screen-printed using a silver paste ^[2] . Sensor Nodes (SNs) can be placed beneath any number of inductors. Power is transferred from the central Base Station (BS) to the SNs in the 27-MHz ISM band, which eliminates the need for bulky energy sources at each SN. Data from the SN is transferred at 1 Mbps through an impedance modulation link, similar to RFID, and is perceived as an ASK waveform by the BS. The high data rate allows each SN to have a very low transmit duty cycle (~1-2 %).

The medium-access protocol is designed to minimize the decision-making burden on the SN. Upon configuring the network, each SN is classified as a “Stream” mode (e.g., EKG, EEG) sensor or a “Contention Access (CA)” mode (e.g., blood pressure, glucose) sensor, which sends data infrequently. The BS assigns fixed timeslots to each stream-mode sensor. Once it has looped through all such sensors, it opens a CA period for the other sensors in the network. The protocol ensures that an SN always waits for a signal from the BS before transmitting and renders synchronization routines, such as the one presented in ^[3] , unnecessary.

1. N. Verma,  A, Shoeb, J. Bohorquez,  J. Dawson, J. Guttag, and A. P. Chandrakasan, “A micro-power EEG acquisition SoC with integrated feature extraction processor for a chronic seizure detection system,” IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 804-816, Apr. 2010.
2. K. Yongsang, K. Hyejung, and Y. Hoi-Jun, “Electrical characterization of screen-printed circuits on the fabric,” IEEE Transactions on Advanced Packaging, vol. 33, no. 1, pp. 196-205, Feb. 2010.
3. O. Omeni, A. Wong, A. J. Burdett, and C. Toumazou, “Energy efficient medium access protocol for wireless medical Body Area SSensor Networks,” IEEE Transactions on Biomedical Circuits and Systems, vol.2, no. 4, pp. 251-259, Dec. 2008.

Continuous tracking of neurological disorders is crucial for the proper diagnosis and medication of epilepsy, and it mandates the design of ultra-low power sensor with a small form factor and continuous EEG classification. The main challenges arise from three factors: 1) variation in seizure pattern from person to person and age to age; 2) the need for wide dynamic range, low-noise AFE with high CMRR; and 3) the area overhead of integrating classification processor to enable seizure monitoring, detection, and storage in one chip. We present an ultra-low-power scalable EEG acquisition SoC for continuous seizure detection and recording with fully integrated patient-specific Support Vector Machine (SVM)-based classification processor. The proposed SoC is composed of 8 high-dynamic range Analog Front-End (AFE) channels, an SRAM and a patient-specific machine-learning seizure classification processor with a Feature Extraction (FE) Engine and a Classification Engine (CE).  Each channel in the AFE integrates a Chopper-Stabilized Capacitive Coupled Instrumentation Amplifier (CS-CCIA) followed by an Analog Signal Processing Unit (ASPU). The SoC maintains high-accuracy seizure detection while minimizing the area overhead of the FE Engine by operating in two separate modes for seizure detection and recording. In seizure detection mode, the AFE uses a bandwidth of 30Hz with a 4-step adapted channel gain according to the signal strength. Once seizure is classified, the SoC automatically runs in seizure-recording mode at 100Hz bandwidth to store the EEG data in the internal SRAM.  Digital filters are implemented using Distributed Quad-LUT (DQ-LUT) architecture, which enables area reduction for full integration of the classification processor. The SoC shows a detection accuracy of 84.4% in a rapid eye blink test while consuming 2.03μJ/classification.

1. J. Yoo, L. Yan, D. El-Damak, M. A. Altaf, A. Shoeb, H.-J. Yoo, and A. P. Chandrakasan, “An 8-channel scalable EEG acquisition SoC with fully integrated patient-specific seizure classification and recording processor,” IEEE Intl. Solid-State Circuits Conference Dig.Tech. Papers, Feb. 2012, pp. 292–293.

The ever-increasing demand for richer internet video content and larger video resolution has motivated work on algorithms that achieve higher compression without sacrificing visual quality. High Efficiency Video Coding (HEVC) ^[1] is being developed by the Joint Collaborative Team on Video Coding as a successor to the popular H.264/MPEG-4 AVC standard. For the same quality, HEVC aims for a 50% bit-rate savings over AVC. This improvement comes at the cost of larger coding units, increased complexity through the addition of new coding tools, and increased computation in existing tools.

Key features of HEVC include hierarchical coding structures of sizes 64×64 down to 8×8 pixels, 36 intra-prediction modes, asymmetric motion partitions, large and non-square transforms, and multiple concatenated loop filters. This work aims at developing a new system architecture for the hierarchical coding structure along with novel designs for the coding tools themselves. A hybrid system pipeline structure is proposed to support all three largest coding units. The transform block uses SRAM-based 2-D transpose memory and leverages DCT matrix properties for extensive resource-sharing techniques for area reduction. External memory bandwidth and power are major concerns for high definition video decoding. These goals are addressed by a novel cache design with 2-D memory mapping and high throughput.

An HEVC video decoder chip capable of real time Quad Full HD (3840×2160) at 30 fps has been implemented. The decoder supports the HEVC Test Model HM-4.0 with low-complexity entropy coding and both low-delay and random-access encoding profiles.

Figure 1: Hierarchical coding structure of HEVC.

1. B. Bross, W.-J. Han, J.-R. Ohm, G. J. Sullivan, and T. Wiegand, “High efficiency video coding (HEVC) text specification draft 6,” ITU-T SG16 WP3 and ISO/IEC JTC1/SC29/WG11 document JCTVC-H1003, Joint Collaborative Team on Video Coding, San Jose, CA, Feb. 2012.

An ultrasound image is formed from a collection of ultrasonic beams transmitted and received by an array of transducer elements.  As the resolution of an image and the range over which an image is to be formed increase, so do the number of these transducer elements and the corresponding digital processing units.  The intensive signal processing power required for ultrasound imaging ^[1] means that conventional ultrasound systems are often large and expensive, and this demand for processing power can only worsen as more transducers and signal channels are implemented.  In applications such as point-of-care diagnostics in rural areas, the movement to a portable and low-power ultrasound imaging system is warranted.

Beamforming, which in its simplest form involves delaying, scaling, and summing to produce a coherent signal from the collection of received beams, has been identified as an area for algorithmic research and development ^[2] .  In this work, an 8-channel wide, scalable digital beamformer is implemented with feedback for power reduction.  Two modes of operation are available: coarse and fine beamforming.  In the coarse beamforming mode, digitized data from an evenly spaced subset of transducer elements are processed, providing a low-quality image of the full region of interest, which yields power savings by turning off the analog front end electronics and analog-to-digital converters corresponding to the unused 50% or 75% of array channels (schematically shown in Figure 1).  Figures 2a and b show the coarse images for quarter and half resolution coarse beamforming modes.  Next, the user can specify a smaller region in which a higher quality image is desired, which is then beamformed by the same 8-channel wide processing unit using all available channels (an example of the full region full resolution image is shown in Figure 2c).

1. M. Ali, D. Magee, and U. Dasgupta, “Signal processing overview of ultrasound systems for medical imaging,” Texas Instruments, Dallas, TX, SPRAB12, 2008.
2. S. Stergiopoulos, Advanced Signal Processing Handbook: Theory and Implementation for Radar, Sonar, and Medical Imaging Real-Time Systems.  Boca Raton: CRC Press, Inc., 2000.

Sensing, data processing, and communication are essential functions of a useful sensor node, whether used in industrial, health or sports monitoring applications. Long battery lifetimes are required for these sensors, and the small size requirements imply small energy storage/harvesting capability. Extreme energy efficiency is thus required in the system and circuit design. This project developed a mini-platform for wireless sensors that highlights the capabilities of two custom ultra-low power transmitter and receiver chips. Figure 1 shows a photograph of the completed prototype with the important modules highlighted. Accelerometer data is packetized and transmitted to a base-station, and a reverse communication link from the base-station to the low-power radio controls some features of the node. The base-station is a custom USB dongle containing a commercial transceiver (TI CC2500), demonstrating the ability of the custom ultra-low-power radios to communicate with generic and readily available hardware. On the mini-platform, an FPGA is used to manage system-level applications. A thumbwheel on the board controls the state of the system, and a Li-ion battery powers the board. The board and battery size is limited by the FPGA and not the featured custom transceiver ICs; hence, dramatic size and power improvements are possible with integration of the application logic into the same silicon as the transceivers.

Figure 2 shows the block diagrams of the transmitter and receiver chips. These have been built for short-distance applications such as Body Area Networks. High-Q FBARs are leveraged to provide front-end filters in the receiver and stable center frequencies in the transmitter with ultra-low power consumption. The high-Q resonators result in inherently single-channel operation in the 2.4GHz ISM band; however, the TX and RX architectures provide multi-channel operation by using multiple FBARs. The PA is optimized for output powers near -10dBm and provides a power-efficient amplitude pulse-shaping scheme. In the RX, the LNA filters incoming RF using the parallel resonance of the FBAR. The cascode switches multiplex channels without degrading the LNA performance. A low-power ring oscillator mixes down to the IF frequency, where envelope detection gives the OOK demodulated data. The circuits are fabricated in 65nm CMOS and operate from a 0.7V supply. The TX consumes 436pJ/bit for 1Mbps -10dBm OOK data while the RX has a sensitivity of -67dBm for 1Mbps OOK and consumes 180pJ/bit.

In the mini-platform, due to aggressive duty-cycling, low energy per bit, and low startup time, the average power consumption of the transmitter was measured to be <14µW.

Speech recognition is becoming a ubiquitous component of the digital infrastructure, serving as an I/O adapter between people and electronic devices.  However, the computational demands imposed by speech recognition make it difficult to integrate into a wide variety of systems.  Today’s popular practice of transmitting voice data to cloud servers requires an Internet connection that may impose unwanted complexity, bandwidth, and latency constraints.  In order to lift these constraints, we are developing a hardware speech decoder architecture that can easily be scaled to trade among performance (vocabulary, decoding speed, and accuracy), power consumption, and cost.

We are now designing a “baseline” speech recognizer IC to serve as a starting point for architectural studies and improved designs in the future.  This chip is intended to decode the 5,000-word Wall Street Journal (Nov. 1992) data set in real time with 10% word error rate (WER) and system power consumption of 100 mW.  Building on the architecture of ^[1] , it performs a Viterbi search over a hidden Markov model using industry-standard weighted finite-state transducer (WFST) transition probabilities ^[2] and Gaussian mixture model (GMM) emission probabilities.  The WFST and GMM parameters are stored in an off-chip NAND flash memory; models for different speakers, vocabularies, and/or languages can be prepared offline and loaded from a computer.  The chip integrates the front-end, modeling, and search components needed to convert audio samples from an ADC directly to text without software assistance.  Its tradeoffs among energy, speed, and accuracy can be manipulated via the model complexity, runtime parameters (e.g., beam width), and voltage/frequency scaling.

Memory access is expected to be the limiting factor in both decoding speed and power consumption.  Previous FPGA implementations required DDR SDRAM with multi-GB/s bandwidth, which is not practical for low-power systems.  We are focusing our efforts on minimizing the off-chip memory bandwidth demands using model compression (e.g., nonlinear quantization of parameters ^[3] ), access reordering, and caching techniques.  Future implementations will also allow larger active state list sizes to improve decoding accuracy, especially with larger vocabularies.

1. J. Choi, K. You, and W. Sung, “An FPGA implementation of speech recognition with weighted finite state transducers,” in IEEE International Conference on Acoustics Speech and Signal Processing, 2010, pp. 1602-1605.
2. M. Mohri, F. Pereira, and M. Riley, “Speech recognition with weighted finite-state transducers,” in Springer Handbook on Speech Processing and Speech Communication. Heidelberg, Germany: Springer-Verlag, 2008
3. I. L. Hetherington, “PocketSUMMIT: Small-footprint continuous speech recognition,” in INTERSPEECH, 2007, pp. 1465-1468.

The emergence of faster and lower-power non-volatile memory technologies has opened up the investigation of ways to integrate these technologies into digital systems ^[1] . This work explores the implementation of a battery-less sensor node as a demonstration of a new kind of ultra-low-power system. In order to operate without a battery, the system must manage the state efficiently in terms of energy overhead during frequent and spontaneous periods of power loss. Figure 1 shows the system block diagram. The memory hierarchy from instruction and data memory to registers in the logic is implemented with non-volatile memory elements. As a result, during spontaneous power disruptions, the system quickly saves the state, and, during power recovery, the system quickly restores the state and resumes computation. In order to achieve the desired functionality (illustrated in Figure 2), a custom non-volatile register must be designed and integrated into a digital design flow. Furthermore, the power management unit must be augmented to interface with the energy harvester, the clocking, and registers in the digital circuitry.

1. T. Kawahara, “Scalable spin-transfer torque RAM technology for normally-off computing,” IEEE Design & Test of Computers, vol. 28, no. 1, pp. 52-63, Jan.-Feb. 2011.

With computational imaging becoming an integral part of photography, enabling this functionality on portable multimedia device is important. Portable device processors lack hardware support for computational imaging. Software-based applications add significant complexity and reduce battery life. This project aims to implement computational photography algorithms on-chip, to enable computational photography on portable multimedia devices, as in Figure 1.

While integrating computational photography is integrated into the camera processor or the processor in a portable multimedia device, power consumption becomes a key concern. This project explores power reduction techniques at different stages of the design, such as algorithmic optimization to reduce computational complexity, architectural optimizations to achieve shared/reconfigurable and parallel-pipelined architecture, and circuit level optimizations to operate at low voltage (V_DD ≤ 0.5V).

A bilateral filter ^[1] , is an edge-preserving filter that takes into account not just the spatial location of pixels but also the intensity variation, is commonly used in several computational photography applications, such as high dynamic range (HDR) imaging ^[2] , low-light image enhancement ^{[3] [4]} , tone management, etc. This project implements a bilateral grid ^[5] as a core processing unit, as in Figure 2, that is shared among multiple applications, such as HDR imaging, low-light imaging, haze removal, and color enhancement. The grid can be accessed directly to implement other applications that require use of bilateral filtering. The project explores energy-scalable image processing using a scalable bilateral grid budget to achieve energy vs. quality trade-offs. Grid dimensions can vary depending on the energy budget. The design can achieve real-time processing for 10 megapixel images.

1. C. Tomasi and R. Manduchi, “Bilateral filtering for grey and color images,” IEEE Int. Conference on Computer Vision, pp. 836-846, Jan. 1998.
2. F. Durand and J. Dorsey, “Fast bilateral filtering for the display of high-dynamic range imaging,” ACM SIGGRAPH, pp. 257-266, July 2002.
3. E. Eisemann and F. Durand, “Flash photography enhancement via intrinsic relighting,” ACM SIGGRAPH, pp. 673-678, Aug. 2004.
4. G. Petschnigg, M. Agrawala, H. Hoppe, R. Szeliski, M. Kohen, and K. Toyama, “Digital photography with flash and no-flash image pairs,” ACM SIGGRAPH, pp. 664-672, Aug. 2004.
5. J. Chen, S. Paris, and F. Durand, “Real-time edge-aware image processing with the bilateral grid,” ACM SIGGRAPH, pp. 1031-1039, July 2007.