Strained-Ge MOSFETs with significantly enhanced mobility compared to Si/SiO₂ hole mobility have previously been reported by our group (see Figure 1).  To enable use of these enhanced channel materials in future nanoscale gate-length FETs, the equivalent oxide thickness (EOT) must be scaled, and improved dielectric/semiconductor interface properties are required. In the search for  suitable gate dielectrics for use with Ge, bilayer dielectric systems have been investigated.  The bottom layer in these systems is expected to provide a high-quality interface to the semiconductor while the top layer is a high-k dielectric used to reduce the overall EOT and gate leakage of the structure.  An Al₂O₃/TiO₂ dielectric system with a sub-nm EOT and low density of interface states on bulk Ge wafers has been demonstrated ^[1] , and its implementation with strained-Ge devices is the aim of this work. Due to the limited thermal budget associated with the bilayer dielectric/metal gate stack, a gate-last process is developed.

In the gate-last process, the source and drain regions are activated before the gate dielectric and gate metal are deposited.  This is done to improve device reliability and mobility at scaled EOT, which can be significantly degraded when the high-k dielectric has gone through the high-temperature steps. Figure 2 shows the schematic gate-last process flow as well as the mask layout of the designed MOSFET structure. The preliminary experiments on gate-last Si MOSFETs show a superior interface quality compared to gate-first devices, a promising result in favor of gate-last strained-Ge MOSFETs, at least as a means of studying the dielectric/semiconductor interface.

1. S. Swaminathan. M.  Shandalov, Y.  Oshima, and P. C.  McIntyre, “Bilayer metal oxide gate insulators for scaled Ge-channel metal-oxide-semiconductor devices,” Applied Physics Letters, vol. 96, no. 8, pp. 082904-082904-3, Feb. 2010.

Compact models for GaN based HEMTs describing the voltage-dependent terminal currents are essential for circuit simulations.  In this work, we extend the virtual-source (VS)-based transport model ^[1] originally developed for Si MOSFETs to GaN based HEMTs along with models for non-linear access regions and device self-heating. The model is suitable for quasi-ballistic or fully ballistic short channel devices typically used for RF and mixed-signal applications. The model has been implemented in Verilog-A language.

Access region behavior is analyzed by measuring I-Vs of TLM structures that represent those transistor access regions. Velocity versus field plot obtained from the I-Vs is shown in Figure 1. The velocity undergoes quasi-saturation at a field of about 5 KV/cm, which is lower than in ^[2] . The quasi-saturation is attributed to velocity saturation and self-heating. Access regions are modeled as non-linear resistors to capture this effect. The intrinsic transistor region is modeled using the VS model including self-heating in the channel. The developed model is compared against DC measurements of a short channel RF HEMT. The device has a gate length of 105 nm, access region lengths of 0.5 µm, and device structure as reported in ^[3] . DC characteristics obtained from the model and measurements are shown in Figure 2. The model gives a good match to the measurements, as Figure 2 shows. Results show that the access regions rather than the intrinsic channel region limit the maximum current in output characteristics. Access regions also cause reduction of transconductance (g_m) with gate voltage after reaching a peak value. The compact model captures these effects well.  The g_m estimated from the model along with gate capacitances would enable estimation of f_T and make projections for future scaling of GaN based HEMTs.

1. A. Khakifirooz, O. M. Nayfeh, D. Antoniadis, “A simple semiempirical short-channel MOSFET current–voltage model continuous across all regions of operation and employing only physical parameters,” IEEE Transactions on Electron Devices, vol.56, no.8, pp.1674-1680, Aug. 2009.
2. L. Ardaravicius, A. Matulionis, J. Liberis, O. Kiprijanovic, M. Ramonas, L. F. Eastman, J. R. Shealy, A. Vertiatchikh, “Electron drift velocity in AlGaN/GaN channel at high electric fields,” Applied Physics Letters , vol.83, no.19, pp.4038-4040, Nov. 2003.
3. D. S.  Lee, X.  Gao, S. Guo, T. Palacios, “InAlN/GaN HEMTs with AlGaN back barriers,” Electron Device Letters, IEEE, vol.32, no.5, pp.617-619, May 2011.

Significant reduction in processor power is needed in order to sustain future data center growth and extend battery life of mobile devices. To this end, we are investigating tunneling field-effect transistors (TFETs) ^[1] as a new type of switch that could potentially provide a subthreshold swing (SS) lower than 60 mV/decade at room temperature, which would enable low power, energy efficient devices.

The structure and energy band diagram of an InAs/GaSb TFET are shown in Figure 1a and 1b, respectively. The TFET switches by modulating the electron tunneling current that flows from the GaSb valence band to the InAs conduction band through the application of a gate voltage that bends the bands. Quantum mechanical tunneling depends strongly on the effective band gap, E_G,eff, the energy difference between the InAs conduction band and the GaSb valence band at the InAs/GaSb interface, as indicated in Figure 1b. Since tunneling current is exponentially dependent on the effective band gap, characterizing the band alignment of the InAs/GaSb heterojunction is critical for optimal device design.

Figure 2 shows a simulated quasi-static capacitance-voltage curve of an ideal InAs/GaSb MOS-capacitor. Structure and material parameters (such as band alignment of the InAs/GaSb heterojunction) that affect specific regions of the capacitance-voltage curve are labeled in the figure. These parameters can be extracted by fitting quasi-static quantum mechanical simulations to experimentally measured capacitance-voltage data using a technique that was used successfully in the study of band alignments in the Si-Ge material system ^[2] . Additionally, a new technique has also been developed to properly model the density of interface traps (D_it) at the dielectric/InAs interface.

1. A. C. Seabaugh and Qin Zhang, “Low-Voltage Tunnel Transistors for Beyond CMOS Logic,” Proceedings of the IEEE, vol. 98, no. 12, pp. 2095–2110, 2010.
2. S. P. Voinigescu, K. Iniewski, R. Lisak, C. A. T. Salama, J.-P. Noél, and D. C. Houghton, “New technique for the characterization of Si/SiGe layers using heterostructure MOS capacitors,” Solid-State Electronics, vol. 37, no. 8, pp. 1491–1501, Aug. 1994.

Collaborators

• T. Equi, FCRP Materials, Structures, and Devices Focus Center, Executive Director
• L. Wei, Post-Doctoral Fellow

Graduate Students

• J. Teherani, Res. Asst., EECS
• J. Lin, Res. Asst., EECS
• E. Polyzoeva, Res. Asst., EECS
• U. Radhakrishna, Res. Asst., EECS

Support Staff

• W. Rokui, Admin. Asst. II
• L. McCormick, Admin. Asst. II

Publications

B.S. Ong, K. L. Pey, C. Y. Ong, C. S. Tan, D. A. Antoniadis, and E. E. Fitzgerald, “Comparison between chemical vapor deposited and physical vapor deposited WSi2 metal gate for InGaAs n-metal-oxide-semiconductor field-effect transistors”,  Applied Phys. Lett. 98, 182102 (3 pages), 2011.

J. Lin, T-W. Kim, D. A. Antoniadis, and J. A. del Alamo, “A Self-Aligned InGaAs Quantum-Well MOSFET Fabricated through a Lift-off Free Front-end Process”, Accepted for publication, IEEE Electr. Dev. Lett., 2012.

Y. Liu, M. Luisier, A. Majumdar, D. A. Antoniadis, and M. S. Lundstrom, “On the Interpretation of Ballisitc Injection Velocity in Deeply Scaled MOSFETs”, IEEE Trans. Elcetron Dev. 59, pp. 994-1001, 2012.

L. Wei, O. Mysore, and D. A. Antoniadis, “Virtual-Source Based Self-Consistent Current and Charge FET Models – From Ballistic to Drift-Diffusion Velocity- Saturation Operation”, IEEE, Trans. Electron Dev.,  Vol. 59, pp. 1263-1271, 2012.

M. Luisier, M. Lundstrom, D. A. Antoniadis, and J. Bokor, “Ultimate Device Scaling: Intrinsic Performance Comparisons of Carbon-based, InGaAs, and Si Field-effect Transistors for 5 nm Gate Length”, Proc. International Electron Devices Meeting (IEDM), pp. 11.2.1 – 11.2.4, 2011.

L. Wei and D. A. Antoniadis, “CMOS Device Design and Optimization from a Perspective of Circuit-Level Energy-Delay Optimization “Proc. International Electron Devices Meeting (IEDM), pp. 15.3.1 – 15.3.4 , 2011.

G. Kurian, C. Sun, C-H Owen Chen, J. E. Miller, J. Michel, L. Wei, D. A. Antoniadis, L-S Peh, L. Kimerling, V. Stojanovic and A. Agarwal, “Cross-layer Energy and Performance Evaluation of a Nanophotonic Manycore Processor System using Real Application Workloads “, Proceedings of the IEEE International Parallel and Distributed Processing Symposium, May 2012.

InGaAs-based metal-oxide-semiconductor field-effect transistors (MOSFETs) have shown great potential for future high- performance and low-power logic applications ^[1] .  Superior electron transport properties ^[2] and impressive device prototypes have been recently demonstrated ^{[3] [4]} . The parasitic resistance is an important problem to address, especially in deeply scaled devices. In addition, the gate-contact separation has to be kept to a minimum to achieve the device footprint goals. We address these requirements by introducing a novel transistor architecture with self-aligned contacts and a gate-last fabrication scheme.

In this work, self-aligned InGaAs quantum-well MOSFETs in the sub-100-nm regime have been demonstrated.  A cross- sectional SEM image of a device with gate length of 90 nm is shown in Figure 1. As shown, the S/D metal (Mo) and the n⁺ cap are self-aligned to the gate. With an optimized recess etch process, the device has achieved a very tight S/D-to-channel spacing (L_side < 20 nm). The channel consists of an InGaAs quantum well buried under a thin InP layer. A composite dielectric consisting of thin layers of Al₂O₃ and HfO₂ is grown by atomic layer deposition (ALD).  Well-behaved output characteristics are shown in Figure 2 for a 90-nm-gate length device. The total on-resistance of this device at V_gs-V_t= 0.7 V is 595 W.mm which is an excellent value. The subthreshold swing for a 60-nm-gate device at V_ds = 0.5 V is 120 mV/dec. The gate current is below 3×10^-3 A/cm² at the maximum operating voltage (V_gs-V_t =0.7 V). The process yields devices with gate lengths down to 30 nm with acceptable parasitic resistance. This self-aligned architecture will enable us to explore the scaling behavior and electron transport characteristics of InGaAs QW-MOSFETs in a dimensional range of interest for future CMOS.

1. J. A. del Alamo, “Nanometer-scale electronics with III-V compound semiconductors,” Nature, vol. 479, pp. 317-323, 2011.
2. D.-H. Kim, B. Brar and J. A. del Alamo, “f_T = 688 GHz and f_max = 800 GHz in L_g = 40 nm In_0.7Ga_0.3As MHEMTs with g_{m_max} > 2.7 mS/μm,” IEDM Tech. Dig., 2011, p. 319.
3. M. Egard, L. Ohlsson, B. M. Borg, F. Lenrick, R. Wallenberg, L.-E. Wernersson, and E. Lind, “High ransconductance self-aligned gate-last surface channel In_0.53Ga_0.47As MOSFET” in IEDM Tech. Dig., 2011, pp. 304.
4. M. Radosavljevic, B. Chu-Kung, S. Corcoran, G. Dewey, M. K. Hudait, J. M. Fastenau, J. Kavalieros, W. K. Liu, D. Lubyshev, M. Metz, K. Millard, N. Mukherjee, W. Rachmady, U. Shah, and R. Chau, “Advanced high-K gate dielectric for high-performance short-channel In_0.7Ga_0.3As auantum well field effect transistors on silicon substrate for low power logic applications,” in IEDM Tech. Dig., 2009, pp. 319.