Continuous tracking of neurological disorders is crucial for the proper diagnosis and medication of epilepsy, and it mandates the design of ultra-low power sensor with a small form factor and continuous EEG classification. The main challenges arise from three factors: 1) variation in seizure pattern from person to person and age to age; 2) the need for wide dynamic range, low-noise AFE with high CMRR; and 3) the area overhead of integrating classification processor to enable seizure monitoring, detection, and storage in one chip. We present an ultra-low-power scalable EEG acquisition SoC for continuous seizure detection and recording with fully integrated patient-specific Support Vector Machine (SVM)-based classification processor. The proposed SoC is composed of 8 high-dynamic range Analog Front-End (AFE) channels, an SRAM and a patient-specific machine-learning seizure classification processor with a Feature Extraction (FE) Engine and a Classification Engine (CE).  Each channel in the AFE integrates a Chopper-Stabilized Capacitive Coupled Instrumentation Amplifier (CS-CCIA) followed by an Analog Signal Processing Unit (ASPU). The SoC maintains high-accuracy seizure detection while minimizing the area overhead of the FE Engine by operating in two separate modes for seizure detection and recording. In seizure detection mode, the AFE uses a bandwidth of 30Hz with a 4-step adapted channel gain according to the signal strength. Once seizure is classified, the SoC automatically runs in seizure-recording mode at 100Hz bandwidth to store the EEG data in the internal SRAM.  Digital filters are implemented using Distributed Quad-LUT (DQ-LUT) architecture, which enables area reduction for full integration of the classification processor. The SoC shows a detection accuracy of 84.4% in a rapid eye blink test while consuming 2.03μJ/classification.

1. J. Yoo, L. Yan, D. El-Damak, M. A. Altaf, A. Shoeb, H.-J. Yoo, and A. P. Chandrakasan, “An 8-channel scalable EEG acquisition SoC with fully integrated patient-specific seizure classification and recording processor,” IEEE Intl. Solid-State Circuits Conference Dig.Tech. Papers, Feb. 2012, pp. 292–293.