Technology scaling has enabled low-power operations in digital integrated circuits.  Therefore, the trend to move analog-to-digital operations upstream to allow more signal-processing to shift from the analog domain to the digital domain is inevitable. As most real world signals remain analog, the design of high-performance and low-power analog-digital converters (ADC) plays a key role in the success of future integrated system design. In this research, we focus on designing a (1) robust, (2) low-power, and (3) high-performance time-interleaved successive-approximation-register (SAR) ADCs. The SAR architecture is adopted because of its good digital compatibility and high energy efficiency while achieving high sampling rates.

The robustness of SAR ADCs is achieved by analyzing the effectiveness of redundancy (digital error correction) ^{[1] [2]} in improving sampling rates and its immunity from incomplete bit-settling errors. Analysis shows that the redundancy algorithm does not help improve sampling rate in all SAR ADC designs; instead, the maximum sampling rate depends on the settling time constant (τ) and the relative magnitude of the ADC delay components ^[3] . As shown in Figure 1, in order to benefit from redundancy algorithm, τ has to be more than 50ps.

The low-power operation is achieved by combining the merged capacitor switching algorithm ^[4] and split capacitive array ^[5] . The merged capacitor-switching algorithm suffers from its sensitivity to the parasitic capacitance on the outputs of the capacitive DAC. The split capacitive array suffers from 4x loss in signal power to keep voltage below the supply rail on the sub-DAC and from the mismatch problem between the fractional bridge capacitor to other capacitors in the DAC. Both issues are researched and resolved in our design. A new digital calibration scheme is developed to digitally calibrate the ADCs to resolve the mismatches and parasitic issues. Our design also incorporates an asynchronous on-chip pulse generator to avoid synchronous high-power clock distribution circuit on-chip. The overall SAR ADCs architecture is depicted in Figure 2.

1. F. Futtner, “A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13μm CMOS,” in IEEE International Solid-State Circuit Conference Digest of Technical Papers, 2002, pp. 136-137.
2. T. Ogawa, H. Kobayashi, M. Hotta, Y. Takahashi, H. San, and N. Takai, “SAR ADC Algorithm with redundancy,” in IEEE APCCAS, pp. 268-271, Nov. 2008.
3. A. H. Chang, H.-S. Lee, and D. S. Boning, “Redundancy in SAR ADCs,” in Great Lakes Symposium on VLSI, May 2011.
4. V. Hariprasath, J. Guerber, S.-H. Lee, and U.-K. Moon, “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,” Electronics Letters, vol. 46, pp. 620-621, Apr. 2010.
5. Y. Chen, X. Zhu, H. Tamura, M. Kibune, Y. Tomita, T. Hamada, M. Yoshioka, K. Ishikawa, T. Takayama, J. Ogawa, S. Tsukamoto, and T. Kuroda, “Split capacitor DAC mismatch calibration in successive approximation ADC,” in IEEE Custom Integrated Circuits Conference, 2009, pp. 279 –282.

The Center for Integrated Circuits and Systems (CICS) at MIT, established in early 1998, is an industrial consortium created to promote new research initiatives in circuits and systems design, as well as to promote a tighter technical relationship between MIT’s research and relevant industry. Seven faculty members participate in the CICS: Hae-Seung Lee (director), Duane Boning, Anantha Chandrakasan, Joel Dawson, David Perreault, Charles Sodini, and Vladimir Stojanovic. CICS investigates a wide range of circuits and systems, including wireless and wireline communication, high-speed and RF circuits, microsensor/actuator systems, imagers, digital and analog signal processing circuits, and power conversion circuits, among others.

We strongly believe in the synergistic relationship between industry and academia, especially in practical research areas of integrated circuits and systems. CICS is designed to be the conduit for such synergy. At present, participating companies include Analog Devices, IBM, Linear Technology, Marvell Technology Group, Maxim Integrated Products, MediaTek, and Texas Instruments.

CICS’s research portfolio includes all research projects that the seven participating faculty members conduct, regardless of source(s) of funding, with a few exceptions.

Technical interaction between industry and MIT researchers occurs on both a broad and individual level. Since its inception, CICS recognized the importance of holding technical meetings to facilitate communication among MIT faculty, students, and industry.  We hold two informal technical meetings per year open to CICS faculty, students, and representatives from participating companies. Throughout each full-day meeting, faculty and students present their research, often presenting early concepts, designs, and results that have not been published yet. The participants then offer valuable technical feedback, as well as suggestions for future research.  More intimate interaction between MIT researchers and industry takes place during work on projects of particular interest to participating companies. Companies may invite students to give on-site presentations, or they may offer students summer employment. Additionally, companies may send visiting scholars to MIT or enter into a separate research contract for more focused research for their particular interest. The result is truly synergistic, and it will have a lasting impact on the field of integrated circuits and systems.

There is an ever-increasing demand for high-resolution and high-accuracy A/D converters in communication systems. In order to raise the sampling rates to the GHz range in a power efficient manner, time-interleaving is an essential technique whereby N A/D channels each operating at a sampling frequency f_s are used to achieve an effective conversion speed of Nf_s as illustrated in Figure 1.

While time-interleaving enables higher conversion rates in a given technology, mismatch issues such as gain, offset, and sampling clock skew errors between channels degrade the overall A/D performance ^[1] . Of these issues, sampling clock skew between channels is the biggest problem in time-interleaved A/Ds with high resolution and high sampling rates. There are a few sources of sampling clock skew between channels. Mismatches in the sampling clock path and logic delays are the most obvious. Input signal routing mismatch and RC mismatch of the input sampling circuits also cause sampling clock skew. The sampling skew can be mitigated by various calibration techniques. Previous calibration techniques employ either analog and digital timing adjustment or digital calibration of output data. The timing adjustment requires adjustable delay resulting in increased sampling jitter, which cannot be compensated by calibration. The digital calibration of output data requires complex interpolation.

In this research project, we are developing a much simpler calibration algorithm for sampling clock skew based on rapid consecutive sampling whereby two samples of the input are acquired a short time apart for each A/D channel. The consecutive sampling method allows for a simple linear interpolation, and the impact on noise or power consumption in the analog circuits is negligible. Since the calibration algorithm is simple, the power consumption in the digital calibration circuits will be low. We are implementing a 12b, 1GS/s time-interleaved ADC to demonstrate the new calibration scheme.

Figure 1: Block diagram of a time-interleaved (TI) A/D.

1. N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, and K. Kobayashi, “Explicit analysis of channel mismatch effects in time-interleaved ADC systems,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 48, no. 3, pp. 261-271, Mar. 2001.

Most current ultrasound imaging systems use piezoelectric materials for the ultrasound transducer. The recent development of micro-electromechanical systems (MEMS) allowed fabrication of capacitive micromachined ultrasound transducers (CMUTs).  A CMUT is a micromachined capacitor whose value changes according to the DC bias voltage or external pressure due to the physical deformation of the top plate by electrostatic force or external pressure. The major advantages of this transducer technology are the potential for integration with supporting electronic circuits, ease of fabrication, higher resolution due to small transducer size, and improved bandwidth and sensitivity ^[1] .

This project focuses on the front-end design of portable ultrasound systems using CMUTs. Figure 1 presents a conceptual block diagram of the system. Implementing an ADC at each channel input makes possible digital beam-forming in the receive (Rx) path, which enhances ultrasound image quality. To implement as many ADCs as the number of transducer channels, each ADC must consume as little power as possible, and each should be implemented in a small area. Considering the required performance, zero-crossing-based (ZCB) pipelined ADC is a suitable architecture ^[2] .  For the first part of this project, a 50-MHz 12-bit ZCB pipelined ADC is designed. The highly digital implementation characteristic of the zero-crossing detection technique enables energy-efficient operation and voltage scaling. Supply voltage scaling based on the required sampling frequency and resolution provides constant energy efficiency over a wide range of sampling frequencies and resolutions.

Recently, a few 2D imaging systems using CMUT as ultrasound transducers have been reported, but they do not use real-time imaging ^[1] . We will consider the digital image processing block in the system level for real-time imaging.  After completing the 2D ultrasound image system using a 1D transducer, we will examine the feasibility of the 3D ultrasound image system using 2D transducers.

Figure 1: Conceptual block diagram of portable ultrasound system.

1. O. Oralkan, “Acoustical Imaging Using Capacitive Micromachined Ultrasonic Transducer Arrays: Devices, Circuits, and Systems,” Ph.D. thesis, Stanford University, Stanford, 2004.
2. L. Brooks and H.-S. Lee, “A zero- crossing-based 8b 200MS/s pipelined ADC,” IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2007, pp. 460-615.

High resolution and high speed in data converters are difficult to achieve at low power consumption levels ^[1] .   This is due to the fundamental limit imposed by thermal noise in high-resolution converters, among other factors.  In order to increase the resolution of a thermal noise limited data converter by one bit while maintaining the same sampling frequency, the power consumption must quadruple ^[2] .  Therefore, it is advantageous to exploit the benefits provided by multiple converter architectures in order to create the most energy-efficient design possible.

Figure 1: Output waveforms for the integrator used in the triple-slope architecture. Top waveform depicts ideal operation while the bottom waveform shows nonlinearity due to the OTA’s finite transconductance.

In this project, we explore the advantages provided by combining aspects from three standard data converter architectures.  The current design aims to achieve at least 16-bit linearity and at most an FOM of 100 [fJ/conv-step] by implementing a two-step pipeline triple-slope ADC.  This implementation takes advantage of the high linearity provided by integrating converters combined with the speed improvements inherent in the triple-slope, two-step and pipeline architectures ^[3] .

An important limitation in a standard triple-slope architecture that leads to non-linearity when operated at high speeds is the finite gain or transconductance of the Opamp or operational transconductance amplifier (OTA), respectively, employed in the integrator.  This particular non-ideality, as depicted in Figure 1, causes an input-dependent transient in the output waveform of the triple-slope integrator at every switching point, which results in a decrease in the converter’s overall linearity.  To mitigate this problem, we are investigating a current cancellation technique that relieves the amplifier from having to supply the current to the integrating capacitor.  This technique effectively increases the OTA’s transconductance as seen from the input node, ultimately producing an output waveform closer to the ideal version in Figure 1.

1. B. Murmann, “ADC Performance Survey 1997-2012,” [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html.
2. H. S. Lee, and C. G. Sodini, “Analog-to-Digital Converters: Digitizing the Analog World” Proc. IEEE, vol. 96, no. 2, pp. 323-334, Feb. 2008.
3. F. Maloberti, Data Converters. The Netherlands: Springer, 2007.

Bandpass delta-sigma modulators (BPDSMs) are particularly useful in modern receiver systems. In a BPDSM system, high-frequency narrow band signals are converted to digital form without prior down-conversion to baseband ^[1] . This pushes the signal-processing burden to the digital domain and helps improve both system simplicity and power efficiency (Figure 1).

BPDSMs can be realized in either continuous-time (CT) or discrete-time (DT) fashion. The CT structure enjoys three advantages over its DT counterpart ^[2] : it has the potential to achieve lower noise and better linearity; it relaxes the bandwidth requirement on Opamps; and it provides intrinsic anti-alias filtering. Therefore, this research focuses on the design of CTBPDSM in CMOS technology, aiming to achieve high resolution and large signal bandwidth.

Compared to lowpass (LP) DSMs, BPDSMs require similar clock frequencies for the same oversampling ratio and similar complexity in both the quantizer and the digital-to-analog converter blocks. However, the BPDSM loop filter, which is a bandpass filter with low power and high linearity requirements, is much more challenging to implement ^[3] . In recent years, several new techniques have been applied to CTLPDSMs that push their performances to wider bandwidth and higher resolution. This research focuses on examining these techniques, adapting them to CTBPDSMs, and investigating the potential for performance improvement. The techniques of interest include the noise-coupled time-interleaved topology ^[4] , the employment of a voltage-controlled-oscillator-based quantizer ^[5] , and a cascaded topology ^[6] .

Figure 1: A signal processing chain found in many receiver systems versus a signal processing chain in a receiver with bandpass analog-to-digital convers

1. R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters. Hoboken, NJ: John Wiley & Sons. Inc., 2005.
2. K. Philips, “Continuous-time sigma-delta ADCs,” Philips Research Laboratories, Eindhoven, the Netherlands, 2004.
3. C.-Y. Lu, J. F. S.-Rivas, P. Kode, J. S.-Martinez and S. Hoyos “A six-order 200MHz IF bandpass sigma-delta modulator with over 68dB SNDR in 10MHz bandwidth,” IEEE Journal of Solid-State Circuits, vol. 45, no. 6, pp. 1122-1136, Dec. 2010.
4. K. Lee, J. Chae, M. Aniya, K. Hamashita, K. Takasuka, S. Takeuchi and G. C. Temes, “A noise-coupled time-interleaved delta-sigma ADC with 4.2 MHz bandwidth, 98 dB THD, and 79 dB SNDR,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2601-2612, Dec. 2008.
5. K. Reddy, S. Rao, R. Inti, B. Young, A. Elshazly, M. Talegaonkar and P. K. Hanumolu, “A 16mW 78dB-SNDR 10MHz-BW CT-DS ADC using residue-cancelling VCO-based quantizer,” in Proc. International Solid State Circuit Conference, 2012, pp. 152-153.
6. L. J. Breems, R. Rutten, R. V. Veldohowen, G. V. D. Weide and H. Termeer, “A 56mW CT quadrature cascaded DS modulator with 77dB DR in a near zero-IF 20MHz band,” in Proc. International Solid State Circuit Conference, 2007, pp. 238-239.

As wireless communication technology is rapidly advancing, new wireless applications are continuously developed. Figure 1 shows each application space and the required dynamic range ^[1] . The new wireless applications demand wideband (50-MHz) and high resolution data converters (>14 bits). Delta-sigma (ΔΣ) analog-to-digital converters (ADCs) are best suited for their ability to achieve high resolution. However, the large bandwidth required poses a significant challenge.  ΔΣ ADCs can be implemented in either a discrete-time (DT) or a continuous-time (CT) structure. Since DT  ΔΣ ADCs require op amp settling within each half clock period, the gain-bandwidth requirement for the op amp is extremely high for the sampling rate required for 50MHz bandwidth. The CT  ΔΣ ADCs require much lower gain-bandwidth. Thus, CT DS ADCs can function at a higher sampling frequency and achieve a wider bandwidth compared to DT  ΔΣ ADCs. In addition, since the CT  ΔΣ ADCs are more power-efficient and have an inherent anti-aliasing property, they are more suitable for the demanding new wireless applications

This project focuses on the design of CT  ΔΣ ADCs, specifically for the application in multiple-input multiple-output wireless receivers. For this application, each CT  ΔΣ ADC in a channel must provide wide bandwidth and high dynamic range at low power consumption. The state-of-art CT  ΔΣ ADCs do not come close to achievingwide enough bandwidth and high enough dynamic range for such applications ^{[2] [3]} . We are investigating a new type of a CT multi-stage noise-shaping (MASH)  ΔΣ ADC based on a DT sturdy-MASH ΔΣ ADC ^[4] . Figure 2 shows the overall structure of a CT MASH ΔΣ ADC. The main advantage of this new type of CT ΔΣ ADCs is that it does not require digital filters that conventional MASH ΔΣ ADCs need to cancel out the quantization error of the first stage. We have developed several new techniques to make a CT MASH ΔΣ ADC faster, more accurate, and robust.

1. K. Lee, J. Chae, M. Aniya, K. Hamashita, K. Takasuka, S. Takeuchi, and G.C. Temes, “A noise-coupled time-interleaved delta-sigma ADC with 4.2 MHz bandwidth, 98 dB THD, and 79 dB SNDR,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2601-2612, Dec. 2008.
2. M. Bolatkale, L.J. Breems, R. Rutten, and K.A.A. Makinwa, “A 4GHz CT DS ADC with 70dB DR and −74dBFS THD in 125MHz BW,” ISSCC Dig. Tech. Papers, pp. 470-472, Feb. 2011.
3. G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, and E. Romani, “A 20-mW 640-MHz CMOS continuous-time DS ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB,” IEEE J. Solid-State Circuits, vol.41, no.12, pp.2641-2649, Dec. 2006.
4. N. Maghari, S. Kwon, and U. Moon, “74 dB SNDR multi-loop sturdy-MASH delta-sigma modulator using 35 dB open-loop Opamp gain,” IEEE J. Solid-State Circuits, vol. 44, no. 8, pp. 2212-2221, Aug. 2009.

The Capacitive Micromachined Ultrasound Transducer (CMUT) is an alternative to traditional piezoelectric transducers. The CMUT technology provides an opportunity for highly integrated ultrasound-imaging system solutions because of its CMOS compatibility and ease of large array fabrication ^[1] .

This project aims to provide a highly flexible platform for 3D ultrasound imaging. Figure 1 presents the system architecture. The CMUT device is flip-chip bonded to the supporting electronic circuits, which eliminates the cables. As a result, the channel count of the imaging system is increased and the capacitive loading due to cables is greatly reduced. The transmitters in the system are reconfigurable to implement Tx Beamforming; the analog front-end receivers and the DSP perform various Rx Beamforming algorithms from the received echo waveforms. We successfully implemented a 2D ultrasound imaging system based on a 1D transducer and corresponding electronics as the first step. Currently a 3D ultrasound-imaging system using 2D transducers is investigated.

In the finished 1D IC fabricated in 0.18µm CMOS process, we implemented 4 channels of Tx and Rx analog front-end circuits. Each channel includes an LNA, a VGA and a high voltage pulser. Acoustic measurements are carried out to demonstrate the improved energy efficiency of the 3-level pulser in Tx. A mechanical 3D translation stage is set up, which mounts a hydrophone to probe ultrasound pressure in the medium. The pressure field measured is referred back to the surface of the CMUT transducer, so that the total emitted acoustic power can be calculated. The Tx efficiency is measured by dividing the acoustic power by the total transmission power. Different pulse shapes lead to different Tx efficiency results. The efficiency improvement of 3-level pulse shape over the traditional 2-level pulse shape is measured to be approximately 50%, which is in agreement with the theory (shown in Figure 2).

1. O. Oralkan, “Acoustical imaging using capacitive micromachined ultrasonic transducer arrays: Devices, circuits, and systems,” Ph.D. dissertation, Stanford, Palo Alto, 2004.

Traumatic brain injury (TBI) occurs in over 1.4 million persons annually in the United States ^[1] .  Monitoring of a patient’s cerebrovascular state following TBI is used in guiding therapy and mitigating secondary injury ^[2] .  Such monitoring, however, often relies on bulky capital equipment and a skilled operator, thus restricting its use to limited clinical environments (typically neurocritical care units).  This project seeks to develop a low-power, miniaturized transcranial Doppler (TCD) ultrasound system for measuring cerebral blood flow velocity (CBFV) in support of continuous cerebrovascular monitoring.

The system architecture, as illustrated in Figure 1, employs multi-channel transceiver electronics and a two-dimensional transducer array to permit electronic steering of the ultrasound beam.  A first-generation discrete eight-channel TCD prototype is shown in Figure 2.  Further revisions of the prototype system will increase channel count for improved beam steering functionality.  Advanced beam steering algorithms will allow for autonomous vessel location, thereby obviating the need for manual transducer alignment and operator expertise.  The wearable system will permit monitoring of cerebrovascular state in a wide variety of contexts that are currently unfeasible under standard measurement modalities.

1. J. A. Langlois, W. Rutland-Brown, and K. E. Thomas, “Traumatic brain injury in the United States: Emergency department visits, hospitalizations, and deaths,” Centers for Disease Control and Prevention, Atlanta, GA, 2004.
2. M. R. Bullock, J. T. Povlishock, Ed., “Guidelines for the management of severe traumatic brain injury,” Journal of Neurotrauma, vol. 24, Supplement 1, 2007.

Graduate Students

• Albert Chang, Research Assistant, EECS
• Daniel Kumar, Research Assistant, EECS
• Sunghyuk Lee, Research Assistant, EECS
• Mariana Markova, Research Assistant, EECS
• Miguel Perez, Research Assistant, EECS
• Sabino Pietrangelo, Research Assistant, EECS
• Do Yeon Yoon, Research Assistant, EECS
• Xi Yang, Research Assistant, EECS

Visiting Scientists

• Doeg-Kyoon Jeong, Professor, Seoul National University
• Shumpei Ida, Murata Manufacturing Co., Ltd.

Support Staff

• Carolyn Collins, Assistant to Director of Center for Integrated Circuits and Systems

Publications

H.-S. Lee, “MOS A/D Converters: Development of Capacitor Array ADCs and Digital Self-Calibration,” ISSCC Special Evenings Session, San Francisco, CA, Feb. 2011.

A. Chang, H.-S. Lee and D. Boning, “Redundancy in SAR ADCs,” GLSVLSI ’11, Lausanne, Switzerland, May 2011.

S. Lee,  A. Chandrakasan, and H.-S. Lee, “A 12b 5-to-50MS/s 0.5-to-1V Voltage Scalable Zero-Crossing Based Pipelined ADC,” Proceedings of the European Solid-State Circuits Conference, pp. 355-358, Sept. 12-16, 2011, Helsinki, Finland.

J. Chu and H.-S. Lee, “A 450 MS/s 10-bit time-interleaved zero-crossing based ADC,” Proceedings of the IEEE Custom Integrated Circuits Conference, Sept. 19-21, 2011, San Jose, CA.

P. Lajevardi, A. Chandrakasan, and H.-S. Lee, “Zero-Crossing Detector Based Reconfigurable Analog System,” IEEE J. Solid-State Circuits, vol. SC-46, pp2478-2487, November, 2011.

S. Lee,  A. Chandrakasan, and H.-S. Lee, “A Voltage Scalable Zero-Crossing Based Pipelined ADC,” accepted to IEEE J. Solid-State Circuits, 2012.