Deeply scaled III-V MOSFETs have demonstrated logic performance at 0.5 V, exceeding that of Si ^[1] . The gate length of modern III-V MOSFETs has been recently reduced to sub-100-nm dimensions.  However, the actual contacts in current research devices still are many times larger than this. Going forward, a key element for a high-performance, small-footprint III-V CMOS technology is the achievement of nanometer-scale source and drain contacts with low contact resistance. This goal is challenging because as the contact length decreases to the nanometer regime, the contact resistance is expected to increase dramatically. This study focuses on characterizing nanometer-scale metal contacts to III-V heterostructures.

We have first developed a fabrication process to build nano-TLM structures with different contact length (L_c) and spacing (d). We have used Mo contacts to an InGaAs-based heterostructure. Mo definition was achieved by electron-beam lithography followed by dry etching. The mesa and contact pads were formed using photo lithography and a series of dry etching and lift off processes. Figure 1 shows a fabricated nano-TLM structure with ~160-nm contact length and a spacing of ~440 nm. The devices are being characterized using Kelvin (4-terminal) measurements. The sheet resistance of Mo film needs to be considered because the film thickness is decreased to ~50 nm. The contact resistance (R_c) and metal sheet resistance (R_shm) can be extracted using an equivalent circuit model developed for this specific nano-TLM structure. In the future we will expect to integrate nano-scale ohmic contact into a III-V CMOS process, with the goal of reducing transistor footprint and provide insight into the limitations that nano-scale contacts impose on transistor characteristics.

Figure 1: Plan view image of a nano-TLM structure with ~160-nm contact length Mo contacts about ~440 nm apart.

1. J. A. del Alamo, “Nanometre-scale electronics with III-V compound semiconductors,” Nature, vol. 479, no. 7373, pp. 317-323, Nov. 2011.

As CMOS technology continues to scale to the nanometer regime, there has been a strong demand for alternative materials to replace silicon. III-V materials, in particular, have shown great promise in extending the road map for high-performance CMOS technology because of their superior electron transport properties ^[1] . However, many III-V FETs are still fabricated using wet etchants that are difficult to control and give large undercuts, decreasing their feasibility for use in commercial logic applications that require very tight footprints. In addition, oversized gate-source and gate-drain separations result in parasitic series resistances that play a large role in degrading device characteristics. A great need exists for a low-damage and highly anisotropic dry-etch process for scaled logic III-V FETs.

This study explored a dry-etching technique for InGaAs caps using CH₄-based chemistry with the addition of SF₆. While a CH₄/H₂ dry etch chemistry gave relatively anisotropic sidewalls with minimal undercut, it was found that this chemistry alone gave rough surfaces, shown in Figure 1. With the addition of SF₆ to the discharge, the surface roughness of etched InGaAs was reduced significantly without affecting anisotropy, shown in Figure 2. Furthermore, when the same CH₄/H₂ dry etch without SF₆ was performed on a GaAs surface, it was found to give smooth surfaces, suggesting that the rough surface could be attributed to the formation of indium-based residue

Besides improving the surface roughness of InGaAs dry etching, the addition of SF₆ to the CH₄/H₂ plasma can also promote the use of InAlAs as an etch stop through the formation of AlF₃ compounds upon reaching the InAlAs surface ^[2] . However, a drawback to the use of SF₆, and many fluorine-containing compounds, is that it attacks silicon oxide and silicon nitride, reducing the effectiveness of these materials as dry-etching masks.

Our research will continue to explore selective dry etching chemistries for III-V heterostructures that provide smooth, highly anisotropic sidewalls with low damage.

1. J. A. del Alamo, “Nanometer-scale electronics with III-V compound semiconductors,” Nature, vol. 479, pp. 317-323, November 2011.
2. S. J. Pearton and W. S. Hobson, “Selective dry etching of InGaAs and InP over AlInAs in CH₄/H₂/SF₆,” Applied Physics Letters, vol. 56, pp. 2186-2188, May 1990.

As silicon MOSFETs approach the limits of their capabilities, III-V field-effect transistors show promise to replace them. The low-effective mass of various III-V materials such as InGaAs and InAs gives rise to extraordinarily high electron velocities ^[1] . III-V based High-Electron Mobility Transistors (HEMTs) represent a great model system to understand physics of relevance to future III-V MOSFETs. In HEMTs it is known that as the gate length is reduced to the sub-100-nm regime, the device enters the ballistic regime ^[2] . In this project, a comprehensive ballistic transport model is being developed to enable the analysis of nanometer-scale III-V HEMTs and MOSFETs and predict the performance of scaled transistors.

The model uses, at its core, a one-dimensional, self-consistent Poisson-Schrödinger simulation of the heterostructure of the transistor. We then add extrinsic device parameters such as source and drain parasitic resistances (R_S and R_D), as well as appropriate values for the drain-induced barrier lowering (DIBL) and a distribution of interface trap states across the bandgap at the semiconductor surface (D_it). The model uses ballistic transport theory to calculate the current-voltage characteristics of the device. Next, we can display the corresponding transconductance, transfer characteristics, output characteristics, or C-V characteristics. Using an option to graph experimental data on top of simulated data, we can adjust the extrinsic device parameters to fit the simulations to the experiments or to identify discrepancies between the two that indicate where more refined models are needed. In this development phase of the model, we are using HEMTs to calibrate the model’s validity in the various regimes of operation, after which physics of relevance to III-V MOSFETs, such as the effect of D_it and imperfect ballisticity, will be added. Ultimately, our modeling approach will allow us to easily characterize current and future MOSFETs.

1. J. A. del Alamo “Nanometer-scale electronics with III-V compound semiconductors,” Nature, vol. 479, pp. 317-323, Nov. 2011.
2. K. Natori, “Ballistic MOSFET reproduces current-voltage characteristics of an experimental device,” IEEE Electron Device Letters, vol. 23, no. 11, pp. 655-657, Nov. 2002.

Photovoltaics and sustainability have received much attention lately. We seek a tandem photovoltaic device using silicon as both the substrate and lower cell and GaAsP as the upper cell. The ideal band gaps for this two-cell tandem structure with silicon at 1.1eV and GaAsP at 1.75 eV allow access to the highest efficiency possible for a two-cell tandem, 36.5%. The lattice mismatch between GaP and Si is 0.37%; therefore, these two materials constitute a nearly ideal combination for the integration of Si and III–V semiconductor-based technologies. Nevertheless, defect-free heteroepitaxy of GaP on Si has been a major challenge.

One can envision a process in which a Si_1-xGe_x graded buffer is grown on a Si wafer to extend the lattice parameter part of the way to GaAs, at which point a lattice-matched GaAs_yP_1-y is grown on the Si_1-xGe_x surface, followed by tensile grading of the GaAs_yP_1-y until GaP is reached. Identifying the composition where the transition can be made from Si_1-xGe_x to GaAs_yP_1-y depending on the application is an integral objective of this study. This identification will provide the flexibility to engineer the lattice constants from Si to Ge and GaP to GaAs while maintaining low threading dislocation density (TDD) and surface morphology suitable for device processing. This study has achieved the successful growth of high-quality lattice-matched GaAs_yP_1-y on Si_0.5Ge_0.5, Si_0.4Ge_0.6, and Si_0.3Ge_0.7 virtual substrates. Various characterization techniques clearly reveal a high-quality crystalline interface (Figure 1) between Si_1-xGe_x and GaAs_yP_1-y with low TDD suitable for device processing, no rampant dislocation nucleation, anti-phase boundaries, stacking faults or other crystalline defects.  Further work will explore the temperature window for the epitaxial growth of GaAs_yP_1-y on Si_1-xGe_x with higher Si content, as the end goal is to obtain a defect-free GaP film on Si substrate.

Figure 1: Cross-sectionalbright field TEM of GaAsyP1-y on (a) Si0.5Ge0.5 and (b) Si0.4Ge0.6 virtual substrates on 6° offcut towards the nearest {111} plane Si (001) substrate.

With the rapid downscaling of CMOS technology, III-V materials have gained much attention due to their high electron mobility. In particular, indium-arsenide and gallium-antimonide are becoming more popular due to their matched lattice constant and their complimentary physical properties, such as bandgap and carrier mobility ^[1] ; various heterostructure-based high performance field-effect transistors (FET) and tunneling transistors have been proposed ^{[1] [2]} . On the other hand, this material system faces challenges due to the poor oxide/semiconductor interface, which results in high interface trap concentration (D_it) and hence Fermi-level pinning ^{[3] [4]} . Therefore, understanding the metal-oxide-semiconductor (MOS) interface in this material system is critical. This study investigates atomic-layer-deposited (ALD) Al₂O₃ on InAs to provide a preliminary understanding of the Al₂O₃/InAs interface.

On an S-doped n-type InAs substrate, 60 cycles of Al­₂O₃ are deposited at 200°C and 250°C after HCl wet chemical cleaning. Then, a Mo/Pt/Au (30 nm/20 nm/100 nm) gate stack is formed using electron-beam evaporation; the back contact is formed using Ti/Au. Finally, 30s post-metallization annealing in N₂ is carried out. Figure 1 shows the normalized capacitance-voltage (C-V) curves of both samples with frequencies varied from 10kHz to 1MHz. The depletion region of the C-V curve is not sharp and deep, as predicted by simulations ^[5] , which is mainly due to the series capacitance corresponding to D_it. Still, the comparison between the two samples shows that Al­₂O₃ deposited at 200°C yields lower D_it than 250°C. Figure 2 plots the C-V hysteresis of the two samples at 100kHz, which reflects the oxide mobile charge near the interface. The results show that the hysteresis is moderate for both samples and that the ALD dielectric quality is promising. Quantitative analysis of the D_it is ongoing.  In summary, InAs/GaSb is a promising heterojunction system, and research is needed to better understand and optimize the dielectric/semiconductor interface.

1. H. Kroemer, “The 6.1 Å family (InAs, GaSb, AlSb) and its heterostructures: A selective review,” Physica E: Low-dimensional Systems and Nanostructures, vol. 20, no. 3–4, pp. 196–203, Jan. 2004.
2. B. R. Bennett, R. Magno, J. B. Boos, W. Kruppa, and M. G. Ancona, “Antimonide-based compound semiconductors for electronic devices: A review,” Solid-State Electronics, vol. 49, no. 12, pp. 1875–1895, Dec. 2005.
3. H.-D. Trinh, E. Y. Chang, Y.-Y. Wong, C.-C. Yu, C.-Y. Chang, Y.-C. Lin, H.-Q. Nguyen, and B.-T. Tran, “Effects of wet chemical and trimethyl aluminum treatments on the interface properties in atomic layer deposition of Al₂O₃ on InAs,” Japanese Journal of Applied Physics, vol. 49, no. 11, p. 111201, Nov. 2010.
4. H.-Y. Lin, S.-L. Wu, C.-C. Cheng, C.-H. Ko, C. H. Wann, Y.-R. Lin, S.-J. Chang, and T.-B. Wu, “Influences of surface reconstruction on the atomic-layer-deposited HfO₂/Al₂O₃/n-InAs metal-oxide-semiconductor capacitors,” Applied Physics Letters, vol. 98, no. 12, p. 123509, 2011.
5. D. Wheeler, L.-E. Wernersson, L. Fröberg, C. Thelander, A. Mikkelsen, K.-J. Weststrate, A. Sonnet, E. M. Vogel, and A. Seabaugh, “Deposition of HfO2 on InAs by atomic-layer deposition,” Microelectronic Engineering, vol. 86, no. 7–9, pp. 1561–1563, Sep. 2009.