Deeply scaled III-V MOSFETs have demonstrated logic performance at 0.5 V, exceeding that of Si ^[1] . The gate length of modern III-V MOSFETs has been recently reduced to sub-100-nm dimensions.  However, the actual contacts in current research devices still are many times larger than this. Going forward, a key element for a high-performance, small-footprint III-V CMOS technology is the achievement of nanometer-scale source and drain contacts with low contact resistance. This goal is challenging because as the contact length decreases to the nanometer regime, the contact resistance is expected to increase dramatically. This study focuses on characterizing nanometer-scale metal contacts to III-V heterostructures.

We have first developed a fabrication process to build nano-TLM structures with different contact length (L_c) and spacing (d). We have used Mo contacts to an InGaAs-based heterostructure. Mo definition was achieved by electron-beam lithography followed by dry etching. The mesa and contact pads were formed using photo lithography and a series of dry etching and lift off processes. Figure 1 shows a fabricated nano-TLM structure with ~160-nm contact length and a spacing of ~440 nm. The devices are being characterized using Kelvin (4-terminal) measurements. The sheet resistance of Mo film needs to be considered because the film thickness is decreased to ~50 nm. The contact resistance (R_c) and metal sheet resistance (R_shm) can be extracted using an equivalent circuit model developed for this specific nano-TLM structure. In the future we will expect to integrate nano-scale ohmic contact into a III-V CMOS process, with the goal of reducing transistor footprint and provide insight into the limitations that nano-scale contacts impose on transistor characteristics.

Figure 1: Plan view image of a nano-TLM structure with ~160-nm contact length Mo contacts about ~440 nm apart.

1. J. A. del Alamo, “Nanometre-scale electronics with III-V compound semiconductors,” Nature, vol. 479, no. 7373, pp. 317-323, Nov. 2011.

As CMOS technology continues to scale to the nanometer regime, there has been a strong demand for alternative materials to replace silicon. III-V materials, in particular, have shown great promise in extending the road map for high-performance CMOS technology because of their superior electron transport properties ^[1] . However, many III-V FETs are still fabricated using wet etchants that are difficult to control and give large undercuts, decreasing their feasibility for use in commercial logic applications that require very tight footprints. In addition, oversized gate-source and gate-drain separations result in parasitic series resistances that play a large role in degrading device characteristics. A great need exists for a low-damage and highly anisotropic dry-etch process for scaled logic III-V FETs.

This study explored a dry-etching technique for InGaAs caps using CH₄-based chemistry with the addition of SF₆. While a CH₄/H₂ dry etch chemistry gave relatively anisotropic sidewalls with minimal undercut, it was found that this chemistry alone gave rough surfaces, shown in Figure 1. With the addition of SF₆ to the discharge, the surface roughness of etched InGaAs was reduced significantly without affecting anisotropy, shown in Figure 2. Furthermore, when the same CH₄/H₂ dry etch without SF₆ was performed on a GaAs surface, it was found to give smooth surfaces, suggesting that the rough surface could be attributed to the formation of indium-based residue

Besides improving the surface roughness of InGaAs dry etching, the addition of SF₆ to the CH₄/H₂ plasma can also promote the use of InAlAs as an etch stop through the formation of AlF₃ compounds upon reaching the InAlAs surface ^[2] . However, a drawback to the use of SF₆, and many fluorine-containing compounds, is that it attacks silicon oxide and silicon nitride, reducing the effectiveness of these materials as dry-etching masks.

Our research will continue to explore selective dry etching chemistries for III-V heterostructures that provide smooth, highly anisotropic sidewalls with low damage.

1. J. A. del Alamo, “Nanometer-scale electronics with III-V compound semiconductors,” Nature, vol. 479, pp. 317-323, November 2011.
2. S. J. Pearton and W. S. Hobson, “Selective dry etching of InGaAs and InP over AlInAs in CH₄/H₂/SF₆,” Applied Physics Letters, vol. 56, pp. 2186-2188, May 1990.

In the last few years, the development of energy-efficient electrical power management systems has received a great deal of interest. Recently, GaN Field-Effect-Transistors have emerged as a disruptive technology with great potential. The high breakdown electric field coupled with the high sheet electron density attainable in GaN heterostructures promises better than three orders of magnitude improvement in the ON-resistance/breakdown-voltage trade-off over conventional Si power-switching devices. However, in spite of recent great progress in GaN power device fabrication technologies, electrical reliability represents a great unknown in these devices. In particular, the dynamic ON-resistance (R_ON), in which the R_ON of the transistor remains high for a certain period of time after an OFF-ON switching event, is a big concern ^[1] . This phenomenon greatly affects the efficiency of electrical power management circuits based on GaN FETs.

Towards the goal of fundamental understanding on the dynamic ON resistance problem, we have developed a new dynamic R_ON measurement methodology that allows the observation of R_ON transients after an OFF-ON switching event from 200 ns to any arbitrary length of time over many decades in time ^[2] . Using this technique, we have performed a fundamental study of dynamic R_ON on high-voltage GaN FETs. Figure 1 shows two examples of R_ON transients obtained over 11 decades in time when the devices are switched from an OFF-state with V_GSQ=-5 V and V_DSQ=40 V. They are measured by a pulsed IV system (blue lines) and semiconductor device analyzer (red lines) on industrially prototyped AlGaN/GaN HEMTs fabricated on two nominally identical epitaxial wafers (labeled A and B) grown by two different commercial epitaxial vendors. In wafer A, R_ON at 200 ns is about 73% higher than in DC. For wafer B, R_ON (200 ns) is about 52% higher than R_{ON_DC}. Such a high dynamic R_ON represents a big problem for power-switching applications. The pattern of recovery of R_ON is also very different in both wafers. Wafer A exhibits a very slow transient in the s-ks time range, while wafer B recovers on a µs-s time scale. The very different transients obtained in these two wafers suggest that the details of epitaxial growth have a great impact on the dynamics of GaN devices. Figure 2 shows OFF to ON transients from different quiescent V_DS values for wafer B. As V_DSQ increases, the dynamic R_ON increases in a prominent manner in both devices, presumably as a result of the increased extension of the high-field region into the drain.

We have carried out additional studies at different temperature and pulse conditions. From all these results, we postulate that on a short time scale, dynamic R_ON arises from the fast release of electrons from border traps at the AlN/AlGaN interface right above the GaN channel through a tunneling process. In contrast, over a longer time scale, conventional thermally assisted detrapping processes from traps in the AlGaN or at the surface dominate. All of these findings provide a path for proper GaN power-switch device engineering and operation that minimize dynamic R_ON.

1. J. A. del Alamo and J. Joh, “GaN HEMT reliability,” Microelectronics Reliability, vol. 49, pp. 1200-1206, September 2009.
2. D. Jin and J. A. del Alamo, “Mechanisms responsible for dynamic ON-resistance in GaN high-voltage HEMTs,” International Symposium on Power Semiconductor Devices and ICs Technical Digest, June 2012.

As silicon MOSFETs approach the limits of their capabilities, III-V field-effect transistors show promise to replace them. The low-effective mass of various III-V materials such as InGaAs and InAs gives rise to extraordinarily high electron velocities ^[1] . III-V based High-Electron Mobility Transistors (HEMTs) represent a great model system to understand physics of relevance to future III-V MOSFETs. In HEMTs it is known that as the gate length is reduced to the sub-100-nm regime, the device enters the ballistic regime ^[2] . In this project, a comprehensive ballistic transport model is being developed to enable the analysis of nanometer-scale III-V HEMTs and MOSFETs and predict the performance of scaled transistors.

The model uses, at its core, a one-dimensional, self-consistent Poisson-Schrödinger simulation of the heterostructure of the transistor. We then add extrinsic device parameters such as source and drain parasitic resistances (R_S and R_D), as well as appropriate values for the drain-induced barrier lowering (DIBL) and a distribution of interface trap states across the bandgap at the semiconductor surface (D_it). The model uses ballistic transport theory to calculate the current-voltage characteristics of the device. Next, we can display the corresponding transconductance, transfer characteristics, output characteristics, or C-V characteristics. Using an option to graph experimental data on top of simulated data, we can adjust the extrinsic device parameters to fit the simulations to the experiments or to identify discrepancies between the two that indicate where more refined models are needed. In this development phase of the model, we are using HEMTs to calibrate the model’s validity in the various regimes of operation, after which physics of relevance to III-V MOSFETs, such as the effect of D_it and imperfect ballisticity, will be added. Ultimately, our modeling approach will allow us to easily characterize current and future MOSFETs.

1. J. A. del Alamo “Nanometer-scale electronics with III-V compound semiconductors,” Nature, vol. 479, pp. 317-323, Nov. 2011.
2. K. Natori, “Ballistic MOSFET reproduces current-voltage characteristics of an experimental device,” IEEE Electron Device Letters, vol. 23, no. 11, pp. 655-657, Nov. 2002.

Achieving a sharp subthreshold swing is crucial to enable the supply voltage scaling that is necessary to reducing power consumption in logic field-effect transistors. In this research, we are investigating a new approach to accomplish this swing based on nanowire FETs with a band engineered superlattice source (SLS).

A steep-subthreshold swing (S) in an FET requires suppressing the subthreshold regime, which in essence is the injection of relatively high-energy source electrons above the energy barrier with the channel. A way to accomplish this injection is to create a miniband in the source with a minigap above it, where no states are allowed. If appropriately designed, no current is possible until the top of the source miniband lines up with the conduction band edge in the channel.  The transition between the ON state and the OFF state can be quite sharp, and the attainable ON current can reach a value comparable to that of a regular FET. In theoretical calculations performed by Gnani et al ^[1] , they have concluded that a variety of SLs can accomplish these goals: AlGaAs/GaAs, InAlAs/InGaAs, and AlGaN/GaN, among others. These are short period SLs with barriers and wells in the 1-2 nm regime. Furthermore, 7 periods appears to be enough to accomplish the filtering action of the SL. They have shown that values of S in the 10-20 mV/dec are possible (at 300K).

Our goal is to demonstrate a prototype SLS NW-FET in the InAlAs/InGaAs system and to study its suitability for steep-subthreshold and ultra-low voltage operation. The proposed device will be a vertical nanowire transistor with superlattice region incorporated in the source. In order to design a suitable heterostructure and device architecture, we created a simulation environment for the miniband structure of superlattices in various material systems using Nextnano. Based on a built-in 1D ballistic transport model, the local density of states was calculated to show explicitly the miniband position, as in Figure 1. Our calculations indicate that a demanding nanowire diameter of sub-10 nm is needed to achieve single transversal sub-band behavior.

In our quest for nanowire FETs, we are developing a reactive ion etch (RIE) process for InGaAs/InAlAs nanowires. Using HSQ as the hard mask defined by electron beam lithography, we have shown promising etch results using Cl₂ based chemistry, as in Figure 2. This will follow with planarization to provide a contact to the top of the nanowire.

1. E. Gnani, P. Mariorano, S. Reggiani, A. Gnudi, G. Baccarani, “Investigation on superlattice heterostructures for steep-slope nanowire FETs,”, Device Research Conference, 2011, pp. 201-202.

There is an increasing interest in AlGaN/GaN high electron mobility transistors (HEMTs) due to their great potential for high performance at microwave frequencies. However, the performance of these devices is often limited by material reliability issues. Unfortunately, a detailed physical understanding of the degradation mechanisms is still lacking. The objective of this project is to develop that understanding through appropriate testing and failure analysis, so that test methods and models can be developed that will lead to further improvement in the reliability and electrical performance of these devices though optimization their design.

Figure 1: Pits and particles observed at the gate edges of a stressed AlGaN HEMT (top view) ^[1] .

Recent work has focused on the formation of pits at the edge of the gate contact during electrical stressing and performance degradation ^{[1] [2] [3]} . These pits have been observed to form under a variety of stressing conditions and in a range of temperatures.  We have found that in some cases the pits are associated with formation of particles that appear to be an oxide of Ga (Figure 1), and that pit and particle formation is suppressed when samples are properly passivated or when they are stressed in ultra-high vacuum conditions. Also, stressing in the presence of water vapor was found to enhance the rate of degradation ^[1] .  This suggests that this failure mechanism is associated with electrochemically-enhanced oxidation.  We have also observed that the rate of pit formation is affected by temperature, both in isothermal experiments and in experiments in which the temperature within an individual device varies significantly.  This finding indicates that this failure process is thermally activated. We estimate an activation energy of about 0.3eV ^[2] .

Analytical techniques such as scanning electron microscopy (SEM), transmission electron microscopy (TEM), atomic force microscopy (AFM), cathode luminescence (CL), and energy-dispersive X-ray spectroscopy (EDX) will be employed in future studies of this and other degradation processes, with the goal of developing predictive models for failure rates and reliability.

1. P. Makaram, J. Joh, J. A. del Alamo, T. Palacios, and C. V. Thompson, “Evolution of structural defects associated with electrical degradation in AlGaN/GaN high electron mobility transistors,” Appl. Phys. Lett,  Vol. 96, p. 233509, 2010.
2. F. Gao, B. Lu, L. Li, S. Kaun, J. S. Speck, C. V. Thompson, and T. Palacios, “Role of oxygen in the OFF-state degradation of AlGaN/GaN high electron mobility transistors,” Appl. Phys. Lett., vol. 99, p. 223506, 2011.
3. L. Li, J. Joh, J. A. del. Alamo, and C. V. Thompson,“Spatial distribution of structural degradation under high-power stress in AlGaN/GaN HEMTs,” Appl. Phys. Lett., to be published.

Collaborators

• J. Jimenez, Triquint Semiconductor
• D.H. Kim, Teledyne Scientific
• T.-W. Kim, Sematech
• B. R. Bennett, NRL

Graduate Students

• A. Guo, RA EECS
• L. Guo, RA EECS
• D.H. Jin, RA, EECS
• J. Lin, RA EECS
• S. Warnock, RA EECS
• X. Zhao, RA, DMSE

Support Staff

• E. Kubicki, Administrative Assistant II

Publications

Xia, L., B. Boos, B. R. Bennett, M. G. Ancona, and J. A. del Alamo, ”Hole Mobility Enhancement through <110> Uniaxial Strain in In_0.41Ga_0.59Sb Quantum-Well Field-Effect transistors.” Applied Physics Letters, vol. 98, 053505, 2011.

Kharche, H., G. Klimeck, D.-H. Kim, J. A. del Alamo, and M. Luisier, ”Multiscale Metrology and Optimization of Ultra-Scaled InAs Quantum Well FETs.” IEEE Transactions on Electron Devices, Vol. 58, no. 7, p. 1963, July 2011.

Xia, L., V. Tokranov, S. R. Oktyabrsky, and J. A. del Alamo, ”Experimental Study of <100> Uniaxial Stress Effects on P-channel GaAs Quantum-Well FETs.” IEEE Transactions on Electron Devices, vol. 58, no. 8, p. 2597, August 2011.

del Alamo, J. A. ”Nanometer-scale electronics with III-V compound semiconductors.” Invited Review paper. Nature, vol. 479, p. 317, 17 November 2011.

Joh, J. and J. A. del Alamo, “Impact of gate placement on RF degradation in GaN high electron mobility transistors.” Microelectronics Reliability, vol. 52, no. 1, p. 33, January 2012.

Li, L., J. Joh, J. A. del Alamo and C. V. Thompson, “Spatial distribution of structural degradation under high-power stress in AlGaN/GaN High-Electron Mobility Transistors.” Applied Physics Letters, vol. 100, p. 172109, 2012.

Joh, J. and J. A. del Alamo, “Time evolution of electrical degradation in GaN high electron mobility transistors.” IEEE International Reliability Physics Symposium, Monterey, CA, April 2011.

del Alamo, J. A., “The High-Electron Mobility Transistor at 30: impressive accomplishments and exciting prospects.” Invited Plenary Session talk at International Conference on Compound Semiconductor Manufacturing Technology, Palm Springs, CA, May 2011, p. 17.

del Alamo, J. A., D.-H. Kim, T.-W. Kim, D. Jin, and D. A. Antoniadis, “III-V CMOS: What Have we Learned from HEMTs?” Invited talk at the 23rd International Conference on Indium Phosphide and Related Materials, Berlin, Germany, May 2011.

Kim, T.-W and J. A. del Alamo, “Injection Velocity in Thin-Channel InAs HEMTs.” 23rd International Conference on Indium Phosphide and Related Materials, Berlin, Germany, May 2011.

Xia, L., V. Tokranov, S. Oktyabrsky and J. A. del Alamo, “Mobility Enhancement of Two-Dimensional hole Gas in an In_0.24Ga_0.76As Quantum Well by <100> Uniaxial Strain.” 38th International Symposium on Compound Semiconductors, Berlin, Germany, May 2011, p. 396.

Gogineni, U., J. A. del Alamo and A. Valdes Garcia, “Analytical Model for RF Power Performance of Deeply Scaled CMOS Devices.” IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Baltimore, MD, June 2011.

del Alamo, J. A., “InAs HEMTs: the path to THz electronics?” Invited talk at Workshop on High-Performance Narrow-Bandgap HEMT Technology for Advanced Microwave Front-Ends: Towards the End of the Roadmap? European Microwave Week, Manchester, UK, October 2011.

Xia, L., V. Tokranov, S. R. Oktyabrsky, and J. A. del Alamo, “Performance Enhancement of p-channel InGaAs Quantum-Well FETs by Superposition of Process-Induced Uniaxial Strain and Epitaxially-grown Biaxial Strain.” IEEE International Electron Devices Meeting, Washington DC, December 2011, p. 315.

Kim, D.-H., B. Brar and J. A. del Alamo, “f_T=688 GHz and f_max=800 GHz in L_g=40 nm In_0.7Ga_0.3As MHEMTs with g_m,max>2.7 mS/um.” IEEE International Electron Devices Meeting, Washington DC, December 2011, p. 319.

InGaAs-based metal-oxide-semiconductor field-effect transistors (MOSFETs) have shown great potential for future high- performance and low-power logic applications ^[1] .  Superior electron transport properties ^[2] and impressive device prototypes have been recently demonstrated ^{[3] [4]} . The parasitic resistance is an important problem to address, especially in deeply scaled devices. In addition, the gate-contact separation has to be kept to a minimum to achieve the device footprint goals. We address these requirements by introducing a novel transistor architecture with self-aligned contacts and a gate-last fabrication scheme.

In this work, self-aligned InGaAs quantum-well MOSFETs in the sub-100-nm regime have been demonstrated.  A cross- sectional SEM image of a device with gate length of 90 nm is shown in Figure 1. As shown, the S/D metal (Mo) and the n⁺ cap are self-aligned to the gate. With an optimized recess etch process, the device has achieved a very tight S/D-to-channel spacing (L_side < 20 nm). The channel consists of an InGaAs quantum well buried under a thin InP layer. A composite dielectric consisting of thin layers of Al₂O₃ and HfO₂ is grown by atomic layer deposition (ALD).  Well-behaved output characteristics are shown in Figure 2 for a 90-nm-gate length device. The total on-resistance of this device at V_gs-V_t= 0.7 V is 595 W.mm which is an excellent value. The subthreshold swing for a 60-nm-gate device at V_ds = 0.5 V is 120 mV/dec. The gate current is below 3×10^-3 A/cm² at the maximum operating voltage (V_gs-V_t =0.7 V). The process yields devices with gate lengths down to 30 nm with acceptable parasitic resistance. This self-aligned architecture will enable us to explore the scaling behavior and electron transport characteristics of InGaAs QW-MOSFETs in a dimensional range of interest for future CMOS.

1. J. A. del Alamo, “Nanometer-scale electronics with III-V compound semiconductors,” Nature, vol. 479, pp. 317-323, 2011.
2. D.-H. Kim, B. Brar and J. A. del Alamo, “f_T = 688 GHz and f_max = 800 GHz in L_g = 40 nm In_0.7Ga_0.3As MHEMTs with g_{m_max} > 2.7 mS/μm,” IEDM Tech. Dig., 2011, p. 319.
3. M. Egard, L. Ohlsson, B. M. Borg, F. Lenrick, R. Wallenberg, L.-E. Wernersson, and E. Lind, “High ransconductance self-aligned gate-last surface channel In_0.53Ga_0.47As MOSFET” in IEDM Tech. Dig., 2011, pp. 304.
4. M. Radosavljevic, B. Chu-Kung, S. Corcoran, G. Dewey, M. K. Hudait, J. M. Fastenau, J. Kavalieros, W. K. Liu, D. Lubyshev, M. Metz, K. Millard, N. Mukherjee, W. Rachmady, U. Shah, and R. Chau, “Advanced high-K gate dielectric for high-performance short-channel In_0.7Ga_0.3As auantum well field effect transistors on silicon substrate for low power logic applications,” in IEDM Tech. Dig., 2009, pp. 319.