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	<title>MTL Annual Research Report 2012 &#187; li-shiuan peh</title>
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		<title>Approaching the Theoretical Limits of a Mesh NoC with a 16-node Chip Prototype in 45nm SOI CMOS</title>
		<link>http://www-mtl.mit.edu/wpmu/ar2012/approaching-the-theoretical-limits-of-a-mesh-noc-with-a-16-node-chip-prototype-in-45nm-soi-cmos/</link>
		<comments>http://www-mtl.mit.edu/wpmu/ar2012/approaching-the-theoretical-limits-of-a-mesh-noc-with-a-16-node-chip-prototype-in-45nm-soi-cmos/#comments</comments>
		<pubDate>Wed, 18 Jul 2012 22:27:16 +0000</pubDate>
		<dc:creator>MTL WP admin</dc:creator>
				<category><![CDATA[Circuits & Systems]]></category>
		<category><![CDATA[anantha chandrakasan]]></category>
		<category><![CDATA[li-shiuan peh]]></category>
		<category><![CDATA[sunghyun park]]></category>

		<guid isPermaLink="false">http://www-mtl.mit.edu/wpmu/ar2012/?p=5841</guid>
		<description><![CDATA[Moore&#8217;s law scaling and the diminishing performance returns of complex uniprocessor chips have led to the advent of multicore processors...]]></description>
				<content:encoded><![CDATA[<div class="page-restrict-output"><p>Moore&#8217;s law scaling and the diminishing performance returns of complex uniprocessor chips have led to the advent of multicore processors with increasing core counts. Their scalability relies highly on the on-chip communication fabric connecting the cores. An ideal communication fabric would incur only metal-wire delay and energy between the source and destination core. However, there is insufficient wiring for dedicated global point-to-point wires between all cores<sup> [<a href="http://www-mtl.mit.edu/wpmu/ar2012/approaching-the-theoretical-limits-of-a-mesh-noc-with-a-16-node-chip-prototype-in-45nm-soi-cmos/#footnote_0_5841" id="identifier_0_5841" class="footnote-link footnote-identifier-link" title="S. Heo and K. Asanovic, &ldquo;Replacing global wires with an on-chip network: A power analysis,&rdquo; IEEE International Symposium on Low Power Electronics and Design, 2005, pp. 369-374.">1</a>] </sup>, and hence, packet-switched Networks-on-Chip (NoCs) with routers that multiplex wires across traffic flows are becoming the de-facto communication fabric in multicore chips<sup> [<a href="http://www-mtl.mit.edu/wpmu/ar2012/approaching-the-theoretical-limits-of-a-mesh-noc-with-a-16-node-chip-prototype-in-45nm-soi-cmos/#footnote_1_5841" id="identifier_1_5841" class="footnote-link footnote-identifier-link" title="W. J. Dally and B. Towles, &ldquo;Route packets not wires: On-chip interconnection networks,&rdquo; ACM/IEEE Design Automation Conference, pp. 684-689, 2001.">2</a>] </sup>.</p>
<p>These routers, however, can impose considerable overhead. In terms of latency, each router can take several pipeline stages to perform the control decisions necessary to regulate the sharing of wires across multiple flows. Inefficiency in the control also frequently leads to poor link utilization on NoCs. Buffers queues have been used to improve flow control and link utilization, but they come with overhead in energy consumption. The conventional wisdom is that NoC design involves trading off latency, bandwidth, and energy.</p>
<p>In this work, we present a case study of our chip prototype of a 16-node 4&#215;4 mesh NoC fabricated in 45nm SOI CMOS that aims to simultaneously optimize energy-latency-throughput for unicasts, multicasts, and broadcasts. We first define and analyze the theoretical limits of a mesh NoC in latency, throughput, and energy and then describe how we approach these limits through a combination of microarchitecture and circuit techniques. Our 1.1V 1GHz NoC chip achieves 1-cycle router-and-link latency at each hop and energy-efficient router-level multicast support, delivering 892Gb/s (87.1% of the theoretical bandwidth limit) at 531.4mW for a mixed traffic of unicasts and broadcasts. Through this fabrication, we derive insights that help guide our research and, we believe, will also be useful to the NoC and multicore research community.</p>

<a href='http://www-mtl.mit.edu/wpmu/ar2012/approaching-the-theoretical-limits-of-a-mesh-noc-with-a-16-node-chip-prototype-in-45nm-soi-cmos/park_meshnoc_01-3/' title='Park_MeshNoC_01'><img width="300" height="225" src="http://www-mtl.mit.edu/wpmu/ar2012/files/2012/07/Park_MeshNoC_01-300x225.png" class="attachment-medium" alt="Figure 1" /></a>
<a href='http://www-mtl.mit.edu/wpmu/ar2012/approaching-the-theoretical-limits-of-a-mesh-noc-with-a-16-node-chip-prototype-in-45nm-soi-cmos/park_meshnoc_02-2/' title='Park_MeshNoC_02'><img width="300" height="298" src="http://www-mtl.mit.edu/wpmu/ar2012/files/2012/07/Park_MeshNoC_02-300x298.png" class="attachment-medium" alt="Figure 2" /></a>

<ol class="footnotes"><li id="footnote_0_5841" class="footnote">S. Heo and K. Asanovic, “Replacing global wires with an on-chip network: A power analysis,” <em>IEEE International Symposium on </em><em>Low Power Electronics and Design</em>, 2005, pp. 369-374.</li><li id="footnote_1_5841" class="footnote">W. J. Dally and B. Towles, “Route packets not wires: On-chip interconnection networks,” <em>ACM/IEEE Design Automation Conference</em>, pp. 684-689, 2001.</li></ol></div>]]></content:encoded>
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		</item>
		<item>
		<title>Li-Shiuan Peh</title>
		<link>http://www-mtl.mit.edu/wpmu/ar2012/li-shiuan-peh/</link>
		<comments>http://www-mtl.mit.edu/wpmu/ar2012/li-shiuan-peh/#comments</comments>
		<pubDate>Wed, 18 Jul 2012 22:20:23 +0000</pubDate>
		<dc:creator>MTL WP admin</dc:creator>
				<category><![CDATA[Faculty Research Staff & Publications]]></category>
		<category><![CDATA[li-shiuan peh]]></category>

		<guid isPermaLink="false">http://www-mtl.mit.edu/wpmu/ar2012/?p=6247</guid>
		<description><![CDATA[On-chip networks; Parallel architectures, mobile computing]]></description>
				<content:encoded><![CDATA[<div class="page-restrict-output"><h3>Graduate Students</h3>
<ul>
<li>O. Chen,Research Assistant, EECS</li>
<li>B. Daya,Research Assistant, EECS</li>
<li>T. Krishna, Research Assistant, EECS</li>
<li>W. Kwon, Research Assistant, EECS</li>
<li>P. Ortiz, Research Assistant, EECS</li>
<li>S. Park, Research Assistant, EECS (co-advised with A. Chandrakasan)</li>
<li>A. Sivaraman, Research Assistant, EECS</li>
<li>S. Subramanian, Research Assistant,EECS</li>
</ul>
<h3>Support Staff</h3>
<ul>
<li>M. Rebelo, Administrative Assistant</li>
</ul>
<h3>Publications</h3>
<p>George Kurian, Chen Sun, Chia-Hsin Owen Chen, Jason E. Miller, Lan Wei, Jurgen Michel, Dimitri Antoniadis, Li-Shiuan Peh, Lionel C. Kimerling, Vladimir Marko Stojanovic and Anant Agarwal, &#8220;Cross-layer Energy and Performance Evaluation of a Nanophotonic Manycore Processor System using Real Application Workloads,&#8221; In 26th International Parallel &amp; Distributed Processing Symposium (IPDPS), Shanghai, China, May 2012.</p>
<p>Sunghyun Park, Tushar Krishna, Chia-Hsin Owen Chen, Bhavya K. Daya, Anantha P. Chandrakasan and Li-Shiuan Peh, &#8220;Approaching the Theoretical Limits of a Mesh NoC with a 16-Node Chip Prototype in 45nm SOI,&#8221; In 49th Design Automation Conference (DAC), San Fransisco, CA, June 2012.</p>
<p>Huayong Wang, Li-Shiuan Peh, Emmanouil Koukoumidis, Tao Shao and Mun Choon Chan, &#8220;Meteor Shower: a reliable stream processing system for commodity data centers&#8221;. In 26th International Parallel &amp; Distributed Processing Symposium (IPDPS), Shanghai, China, May 2012.</p>
<p>Chen Sun, Chia-Hsin Owen Chen, George Kurian, Lan Wei, Jason Miller, Anant Agarwal, Li-Shiuan Peh and Vladimir Stojanovic, &#8220;DSENT &#8212; A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling,&#8221; To appear in 6th International Symposium on Networks-on-Chip (NOCS), Lyngby, Denmark, May 2012.</p>
<p>Emmanouil Koukoumidis, Margaret Martonosi and Li-Shiuan Peh &#8220;Leveraging Smartphone Cameras for Collaborative Road Advisories,&#8221; IEEE Transactions on Mobile Computing, 2012.</p>
<p>Konstantinos Aisopos and Li-Shiuan Peh, &#8220;A Systematic Methodology to Develop Resilient Cache Coherence Protocols,&#8221; In 44th International Symposium on Microarchitecture (MICRO), Port Alegre, Brazil, December 2011.</p>
<p>Tushar Krishna, Li-Shiuan Peh, Bradford M. Beckmann and Steven K. Reinhardt, &#8220;Towards the Ideal On-chip Fabric for 1-to-Many and Many-to-1 Communication,&#8221; In 44th International Symposium on Microarchitecture (MICRO), Port Alegre, Brazil, December 2011.</p>
<p>Chia-Hsin Owen Chen, Sunghyun Park, Tushar Krishna and Li-Shiuan Peh, &#8220;A Low-Swing Crossbar and Link Generator for Low-Power Networks-on-Chip,&#8221; In International Conference on Computer-Aided Design (ICCAD), San Jose, November 2011.</p>
<p>Konstantinos Aisopos, Andrew DeOrio, Li-Shiuan Peh and Valeria Bertacco, &#8220;ARIADNE: Agnostic Reconfiguration In A Disconnected Network Environment,&#8221; In 20th International Conference on Parallel Architectures and Compilation Techniques (PACT), Galveston Island, Texas, October 2011.</p>
<p>Emmanouil Koukoumidis, Li-Shiuan Peh and Margaret Martonosi, &#8220;SignalGuru: Leveraging Mobile Phones for Collaborative Traffic Signal Schedule Advisory,&#8221; In 9th ACM International Conference on Mobile Systems, Applications and Services (MobiSys), Washington, DC, June 2011. Best Paper Award.</p>
<p>Konstantinos Aisopos, Chia-Hsin Owen Chen and Li-Shiuan Peh, &#8220;Enabling System-Level Modeling of Variation-Induced Faults in Networks-on-Chip,&#8221; In 48th Design Automation Conference (DAC), San Diego, CA, June 2011.</p>
<p>Andrew DeOrio, Konstantinos Aisopos, Valeria Bertacco and Li-Shiuan Peh, &#8220;DRAIN: Distributed Recovery Architecture for Inaccessible Nodes in Multi-Core Chips,&#8221; In 48th Design Automation Conference (DAC), San Diego, CA, June 2011.</p>
<p>Emmanouil Koukoumidis, Li-Shiuan Peh and Margaret Martonosi, &#8220;RegReS: Adaptively Maintaining a Target Density of Regional Services in Opportunistic Vehicular Networks,&#8221; In 9th Annual IEEE International Conference on Pervasive Computing and Communications (PerCom), March 2011.</p>
</div>]]></content:encoded>
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