Nitride transistors with current gain cut-off frequencies (f_T) of 300 GHz and power gain cut-off frequencies (f_max) of 394 GHz have been reported ^{[1] [2]} . However, the frequency performance of these devices is still far from the theoretical limit due to poor gate modulation efficiency, short channel effects, high access resistances (R_a), and specific contact resistance (r_c). Nanoribbon (NR)-based nitride HEMTs could overcome many of these limitations by improving the electron confinement thanks to the excellent electrostatics of wrap-around gates ^[3] . Moreover, strong piezoelectric-induced doping can be generated in NR nitride-based semiconductors and increase the maximum operating frequency of nitride devices by reducing the parasitic resistances (Ra and r_c). In this project, we study the use of Ti-induced strain in InAlN/GaN NR HEMTs.

 NR and planar devices are fabricated on the same chip. A Ti/Al/Ni/Au metal stack is then deposited for ohmic contact formation. Electron beam lithography and dry etching are performed in some devices to define NR structures between the ohmic contacts with widths (w) in the w~20-90 ± 10 nm range and a period (p) of p~135 ± 10 nm. An additional Ti strip was deposited between the ohmic contacts (cf. inset of Figure 2) with a width of ~100 mm and a length varying from ~2 to 16 mm and annealed at 870 ^◦C for 30 s in N₂ environment. Figure 1 shows the total resistance R_T in NR and planar devicesas a function of the area coverage of the Ti stripes. A quasi-linear R_T decrease is observed when the Ti surface area increases in the InAlN/GaN NRs samples, unlike in the planar device. The mechanical stress introduced by Ti stripes has a strong effect on the transport properties of InAlN/GaN NRs. Figure 2 shows the decrease of the sheet resistance (R_shTi) underneath the Ti stripe in InAlN/GaN NRs as a function of NR widths. The R_shTi in the NR and planar devices is decreased by ~50-75 % and ~10%, respectively.

1. D. S. Lee, X. Gao, S. Guo, D. Kopp, P. Fay, and T. Palacios, “300-GHz InAlN/GaN HEMTs with InGaN back barrier, IEEE Electron Device Lett., to be published.
2. K. Shinohara, D. Regan, I. Milosavljevic, A. L. Corrion, D. F. Brown, P. J. Willadsen, C. Butler, A. Schmitz, S. Kim, V. Lee, A. Ohoka, P. M. Asbeck, and M. Micovic, “Electron velocity enhancement in laterally scaled GaN DH-HEMTs with f_T of 260 GHz,” IEEE Electron Device Lett., vol. 32, no. 8, pp. 1074-10176, Aug. 2011.
3. W. Lu, P. Xie, and C. M. Lieber, “Nanowire transistor performance,” IEEE Trans. Electron Dev., vol. 55, no 11, pp 2859-2876, Nov. 2008.