The MIT/MTL Center for Graphene Devices and Systems (MIT-CG) brings together, MIT researchers and industrial partners to advance the science and engineering of graphene-based technologies.

The center explores advanced technologies and strategies that enable graphene-based materials, devices and systems to provide discriminating or break-through capabilities for a variety of system applications ranging from energy generation and smart fabrics and materials, to RF communications and sensing. The MIT-CG supports the development of the science, technology, tools and analysis for the creation of a vision for the future of graphene-enabled systems.

Membership privileges for MIT-CG include:

Stay abreast of research developments in graphene
• Webcast of seminars
• Complimentary attendance to meetings
• Facilitated access to IP
Interact with students and faculty at MIT-GC events
• Industry Focus Day
• Resume book of graduating students
Participate in working groups of leading companies and researchers in defining the path forward for graphene
• Timely white papers on key issues
Collaborate with leading researchers on research that addresses today’s challenges
• Direct student projects on modeling in support of working group activities
• Pre-competitive teaming

GaN-based high electron mobility transistors (HEMTs) are an important platform for the realization of high-power, high-frequency devices.  Nanoribbon (NR) HEMT structures represent a novel route towards piezodoping by allowing external stresses to be applied in the plane of the active layer and have been shown to enhance carrier transport properties ^[1] .  This work uses transmission electron microscopy (TEM) and finite element analysis (FEA) to investigate the stress state of InAlN/GaN NR HEMT devices and explore the role of Al₂O₃ in stress generation.

NR structures were fabricated using top-down techniques and passivated with varying thicknesses of Al₂O₃.  TEM samples were obtained from the device structures by using focused ion beam techniques.  Using convergent beam electron diffraction, strain relaxation profiles were obtained by analyzing the splitting of higher order Laue zone lines contained in the [5 4 0] zone axis pattern.  Splitting profiles were also generated from FEA models of the HEMT structure for comparison.  Finally, device-sized structures were simulated to investigate the stress state of the active HEMT layers as a function of the oxide thickness.

Comparison of the experimental and simulated splitting profiles in Figure 1 shows not only that the FEA model correctly replicates overall splitting behavior and the dependence on sample thickness, but that it also consistently under-estimates the experimental results, suggesting an additional source of stress not present in the current model.  Models of device structures showed a compressive stress generated in the active HEMT layer upon the creation of a NR structure that becomes tensile when a layer of Al₂O₃ is applied, as shown in Figure 2.  The magnitude of the tensile stress approaches that of the planar structure as the thickness of the oxide increases.  This data correlates well with earlier published ^[1] electrical characterization of these structures considering the decrease in carrier concentration observed for a compressive strain ^[2] .

1. M. Azize, A. L. Hsu, O. I. Saadat, M. Smith, X. Gao, S. P. Guo, S. Gradečak, and T. Palacios, “High-electron-mobility transistors based on InAlN/GaN nanoribbons,” IEEE Electron Device Letters, vol. 32, pp. 1680-1682, Dec 2011.
2. J. Kuzmik, “InAlN/(In)GaN high electron mobility transistors: Some aspects of the quantum well heterostructure proposal,” Semiconductor Science and Technology, vol. 17, pp. 540-544, June 2002.

Hexagonal boron nitride (h-BN) is very attractive for many applications, particularly as a protective coating, dielectric layer/substrate, transparent membrane, or deep ultraviolet emitter. In this work, we carried out a detailed investigation of h-BN synthesis on Cu substrate using chemical vapor deposition (CVD) with two heating zones under low pressure (LP). Previous atmospheric pressure (AP) CVD syntheses were able to obtain only a few layers of h-BN without a good control on the number of layers ^{[1] [2]} .  In contrast, under LPCVD growth, monolayer h-BN was synthesized, and time-dependent growth was investigated (Figure 1).  It was also observed that the morphology of the Cu surface affects the location and density of the h-BN nucleation (Figure 2).  Ammonia borane, which is easily accessible and more stable under ambient conditions than borazine, is used as a BN precursor. The h-BN films are characterized by atomic force microscopy, transmission electron microscopy and electron energy loss spectroscopy analyses. Our results suggest that the growth here occurs via surface-mediated growth, which is similar to graphene growth on Cu under LP. These atomically thin layers are particularly attractive for use as atomic membranes or dielectric layers/substrates for graphene devices ^[3] .

1. Y. Shi, C. Hamsen, X. Jia, K. K. Kim, A. Reina, M. Hofmann, A. L. Hsu, K. Zhang, H. Li, Z.-Y. Juang, M. S. Dresselhaus, L.-J. Li, and J. Kong, “Synthesis of few-layer hexagonal boron nitride thin film by chemical vapor deposition,” Nano Letters, vol. 10, pp. 4134-4139, Oct. 2010.
2. L. Song, L. Ci, H. Lu, P. B. Sorokin, C. Jin, J. Ni, A. G. Kvashnin, D. G. Kvashnin, J. Lou, B. I. Yakobson, and P. M. Ajayan, “Large scale growth and characterization of atomic hexagonal boron nitride layers,” Nano Letters, vol. 10, pp. 3209-15, Aug. 2010.
3. K. K. Kim, A. Hsu, X. Jia, S. M. Kim, Y. Shi, M. Hofmann, D. Nezich, J. F. Rodriguez-Nieva, M. Dresselhaus, T. Palacios, and J. Kong, “Synthesis of monolayer hexagonal boron nitride on Cu foil using chemical vapor deposition,” Nano Letters, vol. 12, pp. 161-166, Jan. 2012.

The unique combination of high electron velocity and high breakdown voltage of GaN makes this material an ideal candidate for high power and high frequency applications. Among the different possible nitride structures, an InAlN/GaN heterostructure is one of the most promising candidates for high frequency applications because the large polarization discontinuity between InAlN and GaN induces an extremely large charge density with barriers thinner than 10 nm.

This work reports lattice-matched In_0.17Al_0.83N/GaN high electron mobility transistors (HEMTs) on a SiC substrate with a record current gain cutoff frequency (f_T) of 300 GHz [1-2]. To suppress short-channel effects (SCEs), an In_0.15Ga_0.85N back-barrier is applied in an InAlN/GaN heterostructure for the first time. The GaN channel thickness is also reduced to 26 nm, which allows a good immunity to SCEs for gate lengths down to 70 nm, even with a relatively thick top barrier (9.4-10.4 nm). In a device with a gate length (L_g) of 30 nm, an on-resistance (R_on) of 1.2 Ω•mm, and an extrinsic transconductance (g_m.ext) of 530 mS/mm, a peak f_T of 300 GHz is achieved. An electron velocity of 1.37-1.45×10⁷ cm/s is extracted by two different delay analysis methods.

1. D. S. Lee, X. Gao, S. Guo, D. Kopp, P. Fay, and T. Palacios, “300-GHz InAlN/GaN HEMTs with InGaN back-barrier,” IEEE Electron Device Letters, vol. 32, no. 11, pp. 1525-1527, Nov. 2011.
2. D. S. Lee, B. Lu, M. Azize, X. Gao, S. Guo, D. Kopp, P. Fay, and T. Palacios, “Impact of GaN channel scaling in InAlN/GaN HEMTs,” IEDM Technical Digest 2011, pp. 457-460, Dec. 2011.

GaN is an excellent material to be used in high-power, high-frequency and high-temperature applications due to its wide band gap, high saturation velocity, etc. The monolithic integration of GaN power and/or high frequency devices with Si CMOS digital ICs would enable a new level of circuit design flexibility ^[1] . However, typically the GaN device fabrication uses different process technologies from the standard CMOS technologies in Si foundries, such as the Au-contained ohmic process. To realize the target of GaN and Si CMOS integration, Si-CMOS compatible process technologies need to be developed. For the first step, we endeavor to find an Au-free ohmic contact recipe with low contact resistance and smooth metal surface.

The samples we used in this work have a 3-nm GaN cap, a 20-nm unintentionally doped AlGaN barrier layer, and a GaN buffer layer grown on a 6-inch Si wafer. Mesa isolation was realized using ICP systems with Cl₂/BCl₃ gases. For the ohmic contact, we tried different metal schemes including Ti/Al, Ti/Al/Ti, Ti/Al/Pt, Ti/Al/Ni/Pt, Ti/Ge/Ti/Al/Ni/Pt, Si/Ti/Al/Ti/Ta, Mo/Al/Mo/Ti, Ta/Al/Ta, Ta/Al/Ni/Ta, etc, with different annealing temperatures varying from 500°C to 975°C using rapid thermal annealing (RTA) in N₂ ambience. We also tried to include a shallow recess using low etch-rate SiCl₄ plasma etch in an ICP system to improve the ohmic contact. Among these recipes, the metal scheme of Ti/Al/Ni/Pt is found to give a relatively low contact resistance with very good metal surface. Lower ohmic contact resistance values together with a smooth metal surface can be obtained if a 20-30-nm recess is added.

Figure 1 shows the optical pictures of the ohmic metal surface after RTA for 30 s for metal schemes of Ti/Al/Ni/Au, Ti/Al/Ni/Pt, and Ti/Al/Ni/Pt with recess. The Au-contained recipe shows a very rough surface even it is annealed at a relatively low temperature of 800°C. The intermixing of Al and Au and the formation of viscous AlAu₄ phase are believed to result in the rough surface ^[2] . Without Au, the metal surface of Ti/Al/Ni/Pt is very smooth even it is annealed at a much high temperature up to 950°C. The recess of 20 nm (and 30 nm, not shown here) has no obvious effect on the metal surface after annealing. Figure 2 shows the typical contact resistance (R_C) values measured using the transition length method (TLM). A low R_C of around 0.45 Ω-mm can be obtained for the normal Ti/Al/Ni/Au recipe. The R_C value of Ti/Al/Ni/Pt metal is higher (~2.0 Ω-mm), and it can decrease to 1.6Ω-mm with the recess of 20 nm. In the future, more work needs to be carried out to further lower the R_C and optimize the Au-free ohmic contact recipes.

1. H. S. Lee, K. Ryu, M. Sun, and T. Palacios, “Wafer-level heterogeneous integration of GaN HEMTs on Si (100) MOSFETs,” IEEE Electron Device Letters, vol. 33, no. 2, pp. 200-202, Feb. 2012.
2. A. N. Bright, P. J. Thomas, M. Weyland, D. M. Tricker, C. J. Humphreys, and R. Davies, “Correlation of contact resistance with microstructure for Au/Ni/Al/Ti/AlGaN/GaN ohmic contacts using transmission electron microscopy,” Journal of Appl. Phys., vol. 89, no. 6, pp. 3143-3150, Mar. 2001.

Wide band-gap III-nitride semiconductors have great potential for the next generation of power electronics. GaN high-electron-mobility transistors (HEMTs) in particular have attracted great interest due to their high breakdown electric field and high electron mobility. With lower conduction loss and higher switching frequency, GaN-based transistors can improve the efficiency and reduce the size of many power electronics systems.

The standard AlGaN/GaN HEMTs are depletion-mode transistors. However, normally-off transistors are preferred in power electronics. Recently, our group has developed a new normally-off tri-gate GaN metal-insulator-semiconductor-field-effect-transistor (MISFET) ^[1] . By using a three-dimensional tri-gate structure and a sub-micron gate recess, we achieve high performance normally-off GaN transistors with a breakdown voltage as high as 565 V at a drain leakage current of 0.6 μA/mm. The new tri-gate normally-off GaN MISFET has a maximum current density of 530 mA/mm and an on/off current ratio of more than 8 orders of magnitude with a sub-threshold slope of 86±9 mV/decade, as Figure 1 shows. We have also demonstrated a new multi-finger technology with higher yield and lower device resistance for InAlN/GaN HEMTs. A multi-finger device with gate width of 39.6 mm has an on-resistance (R_on) of 0.244 Ω and a maximum current of 18.5 A, as in Figure 2(a).

Finally, ion-implantation isolation technology has also been developed. A state-of-the-art 1800 V breakdown voltage with 2.2 mΩcm² specific on-resistance has been achieved on AlGaN/GaN HEMTs on Si substrate (Figure 2(b)). Devices with ion-implantation isolation have higher breakdown voltage than devices using mesa-etching isolation, showing that ion-implantation isolation is a promising candidate for the next-generation high voltage GaN-based HEMT fabrication.

1. B. Lu, E. Matioli and T. Palacios, “Tri-gate normally-off GaN power MISFET,” IEEE Electron Device Letters, vol. 33, no. 3, pp. 360-362, 2012.

Two-dimensional crystals, including graphene, hexagonal boron nitride, and transition metal dichalcogenides (TMD) materials, have outstanding properties for developing the next generation of electronic devices ^{[1] [2]} . Graphene is the first 2D crystal to attract attention. The symmetry of its honeycomb lattice structure confers on it unique transport properties. The advantages of graphene for radio-frequency (RF) applications derive in part from its high electron and hole mobility, which can exceed 200,000 cm²/Vs at T=5 K and 100,000 cm²/Vs at T=240 K ^{[3] [4]} , the highest ever reported for any semiconductor. Moreover, graphene is a zero-bandgap material in which the conduction and valence bands touch at a point called the Dirac point. In addition to zero bandgap, the density of states in graphene is zero at the Dirac point and increases linearly for energies above and below it, which allows for carrier modulation. The carriers in graphene are confined to a one-atom-thick layer, allowing unprecedented electrostatic confinement and making graphene flexible and transparent. The lack of bandgap can be compensated for by integrating it with other 2D materials such as MoS₂from the TMD family ^{[5] [6]} . MoS₂ shares many of graphene’s advantages for electronic applications; its 1.8 eV bandgap makes it ideal for building logic circuits to complement graphene.

This project demonstrates important building blocks for future integrated circuits based on 2D-materials on flexible substrates such as plastics, paper and textiles. These basic analog building blocks include ambipolar frequency multipliers ^{[7] [8]} , graphene RF mixers ^[9] , graphene oscillators, and graphene phased shift keying devices, plus technology for fabricating flexible devices and circuits on plastic substrates. We construct integrated logic circuits based on few-layer MoS₂, including an inverter, a NAND gate, a memory device, and a ring oscillator. Prototypes of these building blocks move towards new technologies that seamlessly integrate electronics into objects of daily life, from plastic and paper cups with integrated temperature sensors and clothing with embedded RF antennas to smart contact lenses that communicate with cell phones to display relevant information to the wearer.

1. A. K. Geim, “Graphene: Status and prospects,” Science, vol. 324, no. 5934, pp. 1530-1534, June 2009.
2. A. H. C. Neto, et. al., “The electronic properties of graphene,” Rev. Mod. Phys., vol. 81, pp. 109–162, 2009.
3. K. I. Bolotin, et al., “Ultrahigh electron mobility in suspended graphene,” Solid State Communications, vol. 146, no. 9, June 2008.
4. K. I. Bolotin, et al., “Temperature-dependent transport in suspended graphene,” Phys. Rev. Lett., vol. 101, 096802, 2008.
5. P. Joensen, R. F. Frindt, and S. R. Morrison, “Single-layer MoS₂” Mat. Res. Bull., vol. 21, pp. 457-461, 1986.
6. B. Radisavljevic, et. al., “Single-layer MoS2 transistors,” Nature Nanotechnology, vol. 6, pp. 147–150, 2011.
7. H. Wang, D. Nezich, J. Kong, and T. Palacios, “Graphene frequency multipliers,” IEEE Electron Device Lett., vol. 30, no. 5, May 2009.
8. H. Wang, et. al., “Gigahertz ambipolar frequency multiplier based on CVD graphene,” IEDM Tech. Digest, vol. 23, no. 6, pp. 572-575, 2010.
9. H. Wang, et. al., “Graphene-based ambipolar RF mixers,” IEEE Electron Device Lett., vol. 31, no. 9, Sept. 2010.

There is an increasing interest in AlGaN/GaN high electron mobility transistors (HEMTs) due to their great potential for high performance at microwave frequencies. However, the performance of these devices is often limited by material reliability issues. Unfortunately, a detailed physical understanding of the degradation mechanisms is still lacking. The objective of this project is to develop that understanding through appropriate testing and failure analysis, so that test methods and models can be developed that will lead to further improvement in the reliability and electrical performance of these devices though optimization their design.

Figure 1: Pits and particles observed at the gate edges of a stressed AlGaN HEMT (top view) ^[1] .

Recent work has focused on the formation of pits at the edge of the gate contact during electrical stressing and performance degradation ^{[1] [2] [3]} . These pits have been observed to form under a variety of stressing conditions and in a range of temperatures.  We have found that in some cases the pits are associated with formation of particles that appear to be an oxide of Ga (Figure 1), and that pit and particle formation is suppressed when samples are properly passivated or when they are stressed in ultra-high vacuum conditions. Also, stressing in the presence of water vapor was found to enhance the rate of degradation ^[1] .  This suggests that this failure mechanism is associated with electrochemically-enhanced oxidation.  We have also observed that the rate of pit formation is affected by temperature, both in isothermal experiments and in experiments in which the temperature within an individual device varies significantly.  This finding indicates that this failure process is thermally activated. We estimate an activation energy of about 0.3eV ^[2] .

Analytical techniques such as scanning electron microscopy (SEM), transmission electron microscopy (TEM), atomic force microscopy (AFM), cathode luminescence (CL), and energy-dispersive X-ray spectroscopy (EDX) will be employed in future studies of this and other degradation processes, with the goal of developing predictive models for failure rates and reliability.

1. P. Makaram, J. Joh, J. A. del Alamo, T. Palacios, and C. V. Thompson, “Evolution of structural defects associated with electrical degradation in AlGaN/GaN high electron mobility transistors,” Appl. Phys. Lett,  Vol. 96, p. 233509, 2010.
2. F. Gao, B. Lu, L. Li, S. Kaun, J. S. Speck, C. V. Thompson, and T. Palacios, “Role of oxygen in the OFF-state degradation of AlGaN/GaN high electron mobility transistors,” Appl. Phys. Lett., vol. 99, p. 223506, 2011.
3. L. Li, J. Joh, J. A. del. Alamo, and C. V. Thompson,“Spatial distribution of structural degradation under high-power stress in AlGaN/GaN HEMTs,” Appl. Phys. Lett., to be published.

Collaborators

• D. Antoniadis, MIT
• J. del Alamo, MIT
• P. Jarillo-Herrero, MIT
• D. Jena, University of Notre Dame
• J. Kong, MIT
• U. K. Mishra, University of California – Santa Barbara
• E. Monroy, CEA-Grenoble, France
• E. Munoz, ETSIT-UPM, Spain
• D. Perreault, MIT
• C. Thompson, MIT
• H. Xing, University of Notre Dame

Postdoctoral Associates

• M. Azize, France
• T. Fujishima, Japan
• T. Imada, Japan
• H.-S. Lee, South Korea
• Z. Liu, Singapore
• E. Matioli, Brazil

Graduate Students

• F. Gao, Research Assistant
• S. Ha, Research Assistant
• A. Hsu, Research Assistant
• D. S. Lee, Research Assistant
• S. Joglekar, Research Assistant
• B. Lu, Research Assistant
• B. Mailly, Research Assistant
• M. Medlock, Research Assistant
• D. Piedra, Research Assistant
• O. I. Saadat, Research Assistant
• M. Sun, Research Assistant
• H. Wang, Research Assistant
• L. Yu, Research Assistant
• X. Zhang, Research Assistant
• Y. Zhang, Research Assistant

Undergraduate Students

• B. Jain
• R. Luo

Support Staff

• J. Baylon, Admin Assistant II

Publications

Wang, H., A. Hsu, J. Kong, D. Antoniadis, and T. Palacios, “A Compact Virtual Source Current-Voltage Model for Top and Back-Gated Graphene Field Effect Transistors,” IEEE Trans. Of Electron Dev., vol. 58 (5), pp. 1523-1533, 11 pages, May 2011.

Lee, H.-S., D. S. Lee, and T. Palacios, “AlGaN/GaN High Electron Mobility Transistors Fabricated Through a Au-free Technology,” Electron Dev. Letts., vol. 32 (5), pp. 623-625, May 2011.

Ryu, K. K., J. Roberts, E. Piner, and T. Palacios, “Thin-body N-face GaN Transistor Fabricated by Direct Wafer Bonding,” Electron Dev. Letts., vol. 32 (7), pp. 895-897, July 2011.

Hsu, A., H. Wang, K. K. Kim, J. Kong, and T. Palacios, “High Frequency Performance of Graphene Transistors Grown by Chemical Vapor Deposition for Mixed Signal Applications,” Jap. J. of Appl. Phys., vol. 50(7), pp. 070114, 4 pages, July 2011.

Hsu, A., H. Wang, K. K. Kim, J. Kong, and T. Palacios, “Impact of Graphene Interface Quality on Contact Resistances and RF Device Performance,” Electron Device Letters, vol. 32(8), pp. 1008-1010, 3 pages, Aug. 2011.

Xiong C., W. Pernice, K. K. Ryu, C. Schuck, K. Y. Fong, T. Palacios, and H. X. Tang, “Integrated GaN photonic circuits on silicon (100) for second harmonic generation,” Optics Express, vol. 19 (11), pp. 10462-10470, 9 pages, 2011

Wang, H., T. Taychatanapat, A. Hsu, P. Jarillo-Herrero, and T. Palacios, “BN/Graphene/BN Transistors for RF Applications,” Electron Device Letters, vol. 32(9), pp. 1209-1211, 3 pages, Sept. 2011.

Lee, D. S., and T. Palacios, “500 GHz transistors based on GaN… when and how?,” Compound Semiconductor Magazine,pp.33-35, August/September 2011. (Invited).

Palacios, T., “Graphene Electronics: Thinking Outside the Si Box,” Nature Nanotechnology, vol. 6, pp. 464-465, 2 pages, 2011. (Invited).

Lee, D. S., X. Gao, S. Gao, D. Kopp, P. Fay, and T. Palacios, “300-GHz InAlN/GaN HEMTs With InGaN Back-Barrier,” IEEE Electron Dev. Letts.,vol. 32(11), pp 1525-1527, Nov. 2011.

Lu, B., T. Palacios, D. Risbud, S. Bahl, and D. I. Anderson, “Extraction of Dynamic On-Resistance in GaN Transistors under Soft- and Hard-switching Conditions,” Compound Semiconductors IC Symposium, Hawaii’s Big Island, HW, 4 pages, October 16-19, 2011. (Oral Presentation).

Lee, D. S., B. Lu, M. Azize, X. Gao, S. Guo, D. Kopp, P. Fay, and T. Palacios, “Impact of GaN Channel Scaling in InAlN/GaN HEMTs,” International Electron Device Meeting, Washington DC, December 5-7, 2011. (Oral Presentation).

Azize, M., O. Saadat, A. Hsu, M. Smith, S. Guo, S. Gradecak, and T. Palacios, “High Electron Mobility Transistors Based on InAlN/GaN Nanoribbons,” Electron Device Letters, vol. 32(12) pp. 1680-1682, Dec. 2011

Hoke, W. E., R. V. Chelakara, J. P. Bettencourt, T. E. Kazior, J. R. LaRoche, T. D. Kennedy, J. J. Mosca, A. Torabi, A. J. Kerr, H.-S. Lee, and T. Palacios, “Monolithic Integration of Silicon CMOS and GaN Transistors in a Current Mirror Circuit,” submitted to J. of Vac. Science and Tech. B, vol. 30(2) pp. 1-6, December 2011.

Palacios, T., “The coming of age of nanowire electronics,” Nature, vol. 481, pp 152-153, Jan 2012 (Invited).

Lee, H. S., K. Ryu, M. Sun, and T. Palacios, “Wafer-level Heterogeneous Integration of GaN HEMTs and Si (100) MOSFETs,” IEEE Electron Dev. Letts.,vol. 33(2), pp 200-202, Feb. 2012.

Lu, B., E. Matioli, and T. Palacios, “Tri-Gate Normally-off GaN Power MISFET,IEEE Electron Dev. Letts.,vol. 33(3), pp 360-366, March 2012.

Graphene, a two-dimensional honeycomb lattice of sp²-hybridized carbon atoms, has attracted tremendous interest in the scientific community. Surface functionalization is a technology to engineer its electronic properties and make it even more desirable and controllable for electronic device applications. For example, chemical functionalization of graphene, especially by hydrogen, fluorine, and chlorine is predicted to enable doping, edge passivation, and opening of its bandgap. Here, we demonstrate that exposure of graphene device to chlorine plasma in an electron cyclotron resonance (ECR) plasma etcher is an effective way to tune the Fermi level of graphene carriers towards p-type direction, without sacrificing its high conductivity.

Figure 1 compares the Raman spectroscopy of graphene before and after chlorine plasma treatment and also shows how it changes after annealing. After chlorine plasma treatment for 30 s, the D band increases substantially while the G band blue shift by about 5 cm^-1. More importantly, the D band decreases significantly after a 30-min annealing at 500 °C, which means little defect creation occurs during the plasma process.  Further transport measurement shows that the carrier concentration in graphene increases considerably. The plasma reaction process tunes the Fermi level of an intrinsic p-type CVD graphene (V_Dirac >0) towards p-type direction further. We notice that the carrier mobility reduces after plasma reaction. However, this reduction should be mainly due to the increase of hole concentration in graphene rather than defect creation, which is confirmed by the decrease of its sheet resistance and increase of conductivity (see Figure 2). In addition, XPS analysis shows that the percentage of chlorine on the surface of graphene is around 20%. This approach indicates an important way to engineer graphene properties for high-performance applications of graphene devices.