Compressed sensing (CS) is a promising method for recovering sparse signals from fewer measurements than ordinarily used in Shannon’s sampling theorem ^{[1] [2]} . One of the interesting applications of CS is in wireless sensors. Based on recent research, CS shows promise as a potential data compression scheme for wireless sensors. The other application of CS is in analog-to-information converters (AIC).  For applications where signal frequencies are high, but information rates are low, AICs have been proposed as a potential solution to overcome the resolution and performance limitations of traditional, Nyquist-rate high-speed analog-to-digital converters (ADC), whose performance and resolution are often limited by circuit impairments such as sampling jitter and aperture ^[3] .

In this project, we have examined the energy-performance design space for CS in the context of both practical wireless sensor systems and AIC. We have shown that a CS-based sensor system can be an efficient and robust source encoding/compression algorithm for wireless sensor applications where the signal of interest is sparse. As an ADC does, CS provides a flexible and general interface yet still enables data compression proportional to the signal information content, which is consistent with the performance of source coding. CS can enable over 10X reduction in transmission energy when compared to raw quantized data. Furthermore, CS is robust to channel errors and amenable to error control schemes (e.g. CRC error detection) that enable 4X energy reduction and yet have simple hardware realizations ^[4] . In the context of AIC, we have shown that the currently proposed AICs have no advantage over high-speed ADCs. Figure 1 shows an example of AIC architecture that facilitates slower ADCs (i.e. sub-Nyquist ADCs). However, the signal encoding, typically realized with a mixer-like circuit, still needs to occur at the Nyquist frequency of the input to avoid aliasing. The jitter and aperture in the mixer stage of AICs is found to similarly limit the resolution of AICs. Although the evaluation shows that this AIC architecture has limited resolution similar to high-speed ADCs, it has the potential to enable roughly a 2-10X reduction in power for applications where low amplifier gain  is acceptable and the input signal is very sparse (see Figure 2) ^[5] .

1. E. Candes and T. Tao, “Decoding by linear programming,” IEEE Transactions on Information Theory, vol. 51, pp. 4203-4215, 2005.
2. D. L. Donoho, “Compressed sensing,” IEEE Transactions on Information Theory, vol. 52, no. 4, pp. 1289–1306, 2006.
3. X. Chen , Z. Yu, S. Hoyos, B. M. Sadler, and J. Silva-Martinez, “A sub-Nyquist rate sampling receiver exploiting compressive sensing signals,” IEEE Transactions on Circuits and Systems I, vol. 58, no. 3, pp. 507–520, 2010.
4. F. Chen, F. Lim, O. Abari, A. P. Chandrakasan, and V. Stojanovic, “Energy-aware design of compressed sensing systems for wireless sensors under performance and reliability constraints,” IEEE Transactions on Circuits and Systems I, to be published.
5. O. Abari, F. Chen, F. Lim, and V. Stojanovic, “Performance trade-offs and design limitation on analog-to-information converter front-ends,” presented at International Conference on Acoustics, Speech and Signal Processing, Kyoto, Japan, March 2012.

Silicon CMOS circuits have a well-defined lower limit on their achievable energy efficiency due to sub-threshold leakage. Once this limit is reached, power constrained applications will face a cap on their maximum throughput independent of their level of parallelism. Avoiding this roadblock requires an alternative device with steeper sub-threshold slope – i.e., lower V_DD/I_on for the same I_on/I_off. One promising class of such devices is electro-statically actuated nano-electro-mechanical (NEM) switches with nearly ideal I_on/I_off characteristics. Although mechanical movement makes NEM switches significantly slower than CMOS, they can be useful for a wide range of VLSI applications by reexamining traditional system- and circuit-level design techniques to take advantage of the electrical properties of the device. NEM relay circuits with pass-transistor logic design combine as many propagating electrical delays into as few mechanical delays as possible, parallelizing the tasks to do more operations in less time.

Basic circuit design techniques and functionality of some main building blocks of VLSI systems, such as logic, memory, and clocking structures, have been successfully demonstrated in our previous works ^{[1] [2] [3]} .

Recently, complex arithmetic units such as relay-based multipliers have been developed (Figure 1b-c) ^[4] . Simulation results of an optimized 16-bit relay multiplier built in a scaled relay process predicts ~10x improvement in energy-efficiency over optimized CMOS designs in the 10-100 MOPS performance range. The relative performance of the multiplier enhancements are in line with what was previously predicted by a NEM relay 32-bit adder ^[3] , suggesting that complete VLSI systems (e.g., a microprocessor or an ASIC) would expect to see similar energy/performance improvements from adopting NEM relay technology ^{[3] [4]} . The operation of the main building block of the MEM-relay based multiplier, the (7:3) compressor, is experimentally demonstrated. This circuit, consisting of 98 MEM-relays, is the largest MEM-relay based circuit successfully tested to date (Figure 2) ^[4] .

1. F. Chen, M. Spencer, R. Nathanael, C. Wang, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J. Jeon, T.K. Liu, D. Marković,V. Stojanović, E. Alon, “Demonstration of Integrated Micro-electro-mechanical Switch Circuits for VLSI Applications,” IEEE International Solid-State Circuits Conference Technical Digest, Feb. 2010, pp. 150-151.
2. H. Fariborzi, M. Spencer, V. Karkare, J. Jeon, R. Nathanael, C. Wang, F. Chen, H. Kam, V. Pott, T.K. Liu, E. Alon, V. Stojanović, D. Marković, “Analysis and Demonstration of MEM-relay Power Gating,” presented at IEEE Custom Integrated Circuits Conference, San Jose, CA, 2010.
3. M. Spencer, F. Chen, C.C. Wang, R. Nathanael, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J. Jeon, T.K. Liu, D. Marković, E. Alon, V. Stojanović, “Demonstration of Integrated Micro-electro-mechanical Relay Circuits for VLSI Applications,” IEEE Journal of Solid State Circuits, Jan. 2011.
4. H. Fariborzi, F. Chen, R. Nathanael, J. Jeon, T.K. Liu, V. Stojanović, “Design and Demonstration of Micro-electro-mechanical Relay Multipliers,” presented at IEEE Asian Solid State Circuit Conference, Jeju, S. Korea, 2011.

Integrated photonic interconnects present a disruptive alternative to electrical I/O for many VLSI applications, with potential for superior bandwidth density through dense-wavelength-division-multiplexing (DWDM) and energy-efficient operation through both monolithic integration and lower transmission losses. There are two main paths toward an integrated platform. Hybrid designs ^{[1] [2] [3]} enable each component to be custom-tailored but penalize energy efficiency due to large parasitic and packaging capacitance. Manufacturing costs can also increase due to requisite process flows and costly 3D integration or microbump packaging. Monolithic integration offers reduced power and cost but has not penetrated deeply scaled technologies due to necessary process customizations. The platform in Figure 1 monolithically integrates all necessary photonic components (vertical grating couplers, ring filters, modulators, and photodiodes) with electronics in a commercial state-of-the-art 45-nm SOI process with no foundry changes. High-speed electrical and optical components are placed with micron-scale proximity on the same die, minimizing interface parasitics without sacrificing performance or commercial scalability. The eye diagram represents the first fully monolithic electro-optic modulation in 45-nm technology, driven by an on-chip double-data-rate modulator driver. The driver is a configurable all-digital push-pull circuit with sub-bit-time pre-emphasis and split supplies. Due to long carrier lifetimes in silicon and relatively long intrinsic region of these particular modulator designs, the rate is limited to 600Mb/s, achievable in both 1280-nm and 1550-nm bands.  Further device design and biasing optimization will improve performance into the multi-Gb/s range. Figure 2 shows an 8-ring filter bank with 30-GHz bandwidth wavelength-channels fabricated in order and distributed across a 2.04-THz free spectral range. Integrated sigma-delta heater drivers thermally tune rings to a 250-GHz grid with an efficiency of 2.6mW/nm, compensating for ring-resonance mismatch due to process variation and enabling high bandwidth density through DWDM.

1. I. Young, E. Mohammed, J. Liao, A. Kern, S. Palermo, B. Block, M. Reshotko, and P. Chang, “Optical I/O technology for tera-scale computing,” IEEE Int. Solid-State Circuits Conf. Dig., Feb. 2009, pp. 468-469a.
2. A. Rylyakov, C. Schow, B. Lee, W. Green, J. Van Campenhout, Y. Min, F. Doany, S. Assefa, C. Jahnes, J. Kash, and Y. Vlasov, “A 3.9ns 8.9mW 4×4 silicon photonic switch hybrid integrated with CMOS driver,” IEEE Int. Solid-State Circuits Conf. Dig., Feb. 2011, pp. 222-224.
3. F. Liu, D. Patil, J. Lexau, P. Amberg, M. Dayringer, J. Gainsley, H. Moghadam, X. Zheng, J. Cunningham, A. Krishnamoorthy, E. Alon, and R. Ho, “10 Gbps, 530 fJ/b optical transceiver circuits in 40nm CMOS,” IEEE Symp. VLSI Circuits, pp. 290-291, June 2011.

Outphasing power amplifier architectures such as linear amplification with nonlinear components (LINC) have been used to improve the power efficiency of higher-order modulation formats by utilizing more efficient, nonlinear power amplifiers (PA) ^[1] . The asymmetric multilevel outphasing (AMO) has been recently proposed to further improve the average power efficiency of traditional LINC PA by introducing multiple supply levels ^[2] . Figure 1 shows the overall AMO system architecture, where each transmitted sample is decomposed into two vector signals with different phases and restricted amplitude choices. Each decomposed vector signal is first modulated by the phase modulator. Then the high-efficiency switching PA amplifies the signal with appropriate amplitudes. Finally the two vectors are combined to deliver the final output. One bottleneck for both LINC and AMO architectures is the signal component separation (SCS) task, whose functionality is shown on the right side of Figure 1. SCS involves complex functional computations, such as square-root and trigonometric functions, which degrade the overall power-added efficiency, especially at high system throughputs and moderate output powers.

Traditional digital SCS implementations are usually based on look–up-table (LUT) designs ^[3] and are therefore limited by accuracy and area while their analog counterparts are usually limited by speed ^[4] . To overcome these limitations, we propose to simplify the function computations by using a piece-wise linear spline approximation for each function, as shown in Figure 2(b).  With careful design of the constant and slope terms, each function computation only involves a small LUT, one multiplication, and two additions. This approach achieves a 6-10x energy efficiency improvement over the traditional CORDIC ^[5] for trigonometric functions and polynomial fittings. The overall SCS system’s micro-architecture is shown in Figure 2(a), where all the functional computations are implemented with our approximation approach. This system is fabricated in a 45-nm SOI process. The chip runs up to 1.7GHz (3.4 Gsamples/s) at 1.1V supply. Figure 2(c) shows the energy efficiency for different throughput. The minimum-energy point is 74pJ per sample at 800Msamples/s throughput.

1. D. Cox, “Linear amplification with nonlinear components,” IEEE Trans. on Communications, vol. 22, no. 12, pp. 1942-1945, Dec. 1974.
2. S. Chung, P. A. Godoy, T. W. Barton, E. W. Huang, D. J. Perreault, and J. L. Dawson, “Asymmetric multilevel outphasing architecture for multi-standard transmitters,” IEEE Radio Frequency Integrated Circuits Symposium, pp. 237-240, June 2009.
3. C. P. Conradi, J. G. McRory, and R. H. Johnston, “Low-memory digital signal component separator for LINC transmitters,” Electronics Letters, vol. 36, no. 7, pp. 460-461, Mar. 2001.
4. L. Panseri, L. Romano, S. Levantino, C. Samori, and A. L. Lacaita, “Low-power signal component separator for a 64-QAM 802.11 LINC transmitter,” IEEE Journal of Solid-State Circuits, vol. 43, no. 5, pp. 1274-1286, May 2008.
5. P. K. Meher, J. Valls, J. Tso-Bing, K. Sridharan, and K. Maharatna, “50 Years of CORDIC: Algorithm, architectures, and applications,” IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 56, no. 9, pp. 1893-1907, Sept. 2009.

Figure 1: Magnetization as a function of applied field.

Numerical algorithms are the basis of many important technologies employed in industry and academia. Their efficient implementation is key in achieving good performance of simulation software, DSP for communication systems, multimedia, machine learning, and mission-critical real-time navigation and control. Unsurprisingly significant effort is still spent researching hardware and software acceleration of basic building blocks for numerical computation ^{[1] [2] [3]} . However, most of the previous work is based within one implementation layer of a computation system. Such layers include the algorithm to perform the computation, the software implementation, and the target hardware. Here we consider the entire abstraction layer of a system implementation, as shown in Figure 1, providing tight design-time coupling between them, with the ultimate goal of exploring numerical hardware platform tradeoffs at both limits of performance: high speed and low power.

For tight coupling of algorithm and processor physical layer constraints, our project focuses on the link between these layers: an optimizing compiler.  Underneath the compiler, we use data abstraction and polymorphism in advanced HDLs to design a very flexible, extendable VLIW-style processor template. The design is fixed at the protocol level while the actual micro-architectural configuration (number of units, pipeline depth of every unit, etc.) is postponed through parameterization. Processor basic building blocks (crossbars, floating-point units, memories, etc.) are prototyped in the target technology to characterize maximum clock frequency as a function of pipeline depth for each unit. On top of the compiler, the algorithm evaluation graph is optimized through constant-folding, dead-code elimination, and similar compiler techniques. Finally, the link between the algorithm-side computational requirement and achievable performance is established through extensive compiler sweeps determining the optimal processor configuration for a given algorithm and technology tradeoffs.

We chose Model Predictive Control (MPC) of linear systems ^{[1] [2]} as a motivation and test vehicle for our design. It is an advanced control algorithm using many standard numerical blocks, e.g., as matrix-vector multiplications, matrix decompositions, linear system solvers. It has been extensively studied ^{[1] [2]} in embedded systems and hardware and software implementations.

Our results show that reductions of up to 4x in overall latency can be obtained by proper processor configuration. Furthermore, we show that the optimal latency point is not at any of the intuitive points, the minimum cycle count or the highest clock frequency, but depends on topological features of the computation graph. Currently, we are working on validating our predictions that even at ~20x clock penalty for FPGA implementations, we should expect ~8x improvement in latency from highly optimized implementations running on multi-GHz processors ^[1] , validating our cross-layer approach.

1. J. Mattingley and S. Boyd, ” Real-time convex optimization in signal processing,” IEEE Signal Processing Magazine, vol. 27, no. 3, pp. 50-61.
2. K. V. Ling, S. P. Yue, and J. M. Maciejowski, “An FPGA implementation of model predictive control,” in American Control Conference, 2006, pp. 1930-1935.
3. Leung, B. et al., “An interior point optimization solver for real time inter-frame collision detection: Exploring resource-accuracy-platform tradeoffs,” in International Conference on Field Programmable Logic and Applications, 2010, pp. 113-118.

Demand for bandwidth in chip-to-chip communication has been increasing as the industry demands a higher quantity and quality of information. Serial links are a suitable architecture for this kind of transmission because of speed, power, and area limitations on parallel links. Figure 1 shows an example of basic serial link components. This research focuses on the design of a power-efficient transmitter and receiver circuits for backplane serial links targeting link speeds of hundreds of Gb/s in the specifications for the next generation of links.

Several challenges face such high speeds. Link rates are increasing to the point where they are running into the bandwidth limitation of the cables or backplanes. This bandwidth limitation is caused by dielectric loss, skin-effect, and impedance discontinuities ^[1] . Additionally, in many applications the wires within a system can have significantly different channel characteristics, as shown in Figure 2. Different equalization techniques are used to compensate for channel response and achieve a bigger eye at the receiver ^[2] . Clocking in both the transmitter and receiver is another problem, with low supply voltages and low power requirements. Transmitter and receiver must be synchronous, to correctly sample the received data at the maximum eye opening. Besides, targeting such speeds pushes current CMOS technologies to their limits. As a result, new ideas and circuit tricks are desired.

This research concentrates on the transmitter side. Work is now being done on a new transmitter equalizer technique, which introduces about double the eye opening of conventional FIR feed-forward equalizers. A behavioral model for the whole serial link system was developed last year, and more work is being dedicated to improving its accuracy and accounting for different transistor technologies and circuit architectures. The project is done in collaboration with UC Berkeley, UCLA, and OSU.

1. S. V. Stojanović, A. Ho, B. W. Garlepp, F. Chen, J. Wei,  G. Tsang, E. Alon, R. T. Kollipara,  C. W. Werner, J. L. Zerbe, and M. A. Horowitz, “Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery,” IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 1012-1026, Apr. 2005.
2. R. Sredojević and V. Stojanović, “Fully digital transmit equalizer with dynamic impedance modulation,”  IEEE Journal of Solid-State Circuits, vol. 46, no. 8, pp. 1857-1869, Aug. 2011.

With the rise of many-core chips that require substantial bandwidth from the network-on-chip (NoC), integrated photonic links have been investigated as a promising alternative to traditional electrical interconnects. While numerous opto-electronic NoCs have been proposed, evaluations of photonic architectures have thus far had to use a number of simplifications, reflecting the need for modeling tools and methodologies that accurately capture the tradeoffs for the emerging technology and its impacts on the overall network. To solve these issues, we developed circuit-level models for photonic interconnects ^[1] and DSENT ^[2] , a NoC modeling tool for rapid design space exploration of electrical and opto-electrical networks. Using the framework shown in Figure 1, we identified the most profitable opportunities for improvement in the context of an entire opto-electronic network system, emphasizing the impact of photonics technology parameters on the networks at different loads. We find that non-data-dependent laser and tuning power added by photonic components represent a serious source of power inefficiency at lower link utilizations (Figure 2). This inefficiency is problematic as NoCs are typically provisioned to operate well below saturation throughput to achieve low contention delays. We use these results to motivate electrically-assisted tuning strategies ^{[1] [2]} and influence photonic network proposals ^[3] to better address the non-data-dependent power problem of photonics.

1. M. Georgas, J. Leu, B. Moss, C. Sun, V. Stojanovic, “Addressing link-level design tradeoffs for integrated photonic interconnects,” in Proc. Custom Integrated Circuits Conference, 2011, pp. 1-8.
2. C. Sun, C-H. Chen, G. Kurian, J. Miller, L. Wei, A. Agarwal, L-S. Peh, V. Stojanovic, “DSENT – A tool connecting emerging photonics with electronics for opto-electronic networks-on-chip modeling,” in Proc. International Symposium of Networks on Chip, 2012. Pp. 201-210.
3. G. Kurian, C. Sun, C-H. Chen, J. Miller, L. Wei, J. Michel, D. Antoniadis, L-S. Peh, L. Kimerling, V. Stojanovic, A. Agarwal. “Cross-layer energy and performance evaluation of a nanophotonic manycore processor system using real application workloads,” in Proc. International Parallel and Distributed Processing Symposium, 2012.

Silicon photonics is poised to meet the increasing demand for high-bandwidth, low-power, and densely integrated optical communications in CMOS-compatible environments. Microring resonators in particular have become ubiquitous photonic building blocks that have already been utilized to demonstrate modulators, filters, and switches. However, the large frequency dependence with geometry (~100GHz/nm) and thermo-optic coefficient (~10GHz/°C) innate to silicon microrings threatens to preclude their use in dense wavelength division multiplexed (DWDM) applications, where the channel spacings are tight and temperatures may vary by as much as 15°C. Several promising solutions to address this challenge have come in the form of low-power (4.4µW/GHz) and high-speed thermal tuning, sensor-based thermal compensation, and athermal devices. However, while temperature sensor and athermal solutions address the thermal stability issue, they do not address fabrication based frequency variations. A recent study has leveraged scattering of the microring filters for wavelength locking; however, scattered light based techniques are insufficiently reliable to enable large-scale implementations.

In our work ^[1] , we experimentally demonstrated the first high-speed and scalable on-chip optical wavelength recovery capable of compensating both fabrication and thermal induced frequency variations on a silicon photonic chip. Using a thermally tunable adiabatic resonant microring (ARM) resonator, shown in Figure 1a, combined with a unique wavelength recovery algorithm implemented using a field-programmable gate array (FPGA), we demonstrate low-power (less than 1mW for ±10°C) and high-speed (as low as 200 µs) wavelength recovery. Furthermore, this approach is capable of being implemented using advanced CMOS electronics, hybrid or monolithically integrated with silicon photonics. The implemented algorithm and the experimental results are depicted in Figure 1. Using the algorithm, the recovery time is experimentally reduced from 4.3ms to 200µs.

Figure 1: A) Diagram of the experimental setup for wavelength recovery using the ARM resonator and top-view scanning electron microscope (SEM) image of the device. B) Measured frequency shift and calibrated temperature shift as a function of heater power. C) Coarse and fine loop flow charts for wavelength recovery decision-making for thru port where P_H(t) is real-time power dissipated in the heater; ΔP_H(t) is real-time power variation in the heater; P_MAX/MIN is maximum/minimum heater power; ΔP_C/F is coarse/fine minimum power variation in the heater; I(t) is real time output intensity; I₀ is the threshold intensity; e(t) is the error signal; and I_T(t) is the target intensity, which is constantly updating for global minima locking. Drop port decision-making algorithm can be implemented by changing comparison statements and using the rest of the algorithm. D) Microring wavelength recovery results as a function of increasing minimum power variation in the heater and stability of the recovered signal is investigated as a function of loop speed (inset).

1. E. Timurdogan, A. Biberman, D. C. Trotter, C. Sun, M. Moresco, V. Stojanović, and M. R. Watts, “Automated wavelength recovery for microring resonators,” in Proc. Conference on Lasers and Electro-Optics, CM2M.1 2012.

Collaborators

• E. Alon, UC Berkeley
• K. Asanović, UC Berkeley
• T.-J. King Liu, UC Berkeley
• D. Marković, UC Los Angeles
• C-K. K. Yang, UC Los Angeles

Graduate Students

• Y-H. Chen, Research Assistant, EECS
• S. Dutta, Research Assistant, EECS
• H. Fariborzi, Research Assistant, EECS
• M. Georgas, Research Assistant, EECS
• J. Leu, Research Assistant, EECS
• Y. Li, Research Assistant, EECS
• Z. Li, Research Assistant, EECS
• B. Moss, Research Assistant, EECS
• O. Salehi-Abari, Research Assistant, EECS
• R. Sredojević, Research Assistant, EECS
• A. Suleiman, Research Assistant, EECS
• C. Sun, Research Assistant, EECS
• S. Urosević, Research Assistant, EECS

Publications

M. Georgas, J. Orcutt, R. J. Ram, and V. Stojanović, “A Monolithically-Integrated Optical Receiver in Standard 45-nm SOI [Invited],“ IEEE Journal of Solid-State Circuits, vol. 47, no. 7, 10 pages, July 2012.

J.S. Orcutt, B. Moss, C. Sun, J. Leu, M. Georgas, J. Shainline, E. Zgraggen, H. Li, J. Sun, M. Weaver, S. Urosevic, M. Popovic, R. J. Ram and V. Stojanović, “An Open Foundry Platform for High-Performance Electronic-Photonic Integration,” Optics Express, vol. 20, no. 11, pp. 12222-12232, May 2012.

T.-J. Liu, K., D. Marković, V. Stojanović and E. Alon, “The Relay Reborn,” [Invited] IEEE Spectrum, vol. 49, no. 4, pp. 40-43, April 2012.

J. S. Orcutt, J. S., S. D. Tang, S. Kramer, H. Li, V. Stojanović, and R. J. Ram, “Low-loss polysilicon waveguides fabricated in an emulated high-volume electronics process,” Optics Express, vol. 20, no. 7, pp. 7243–7254, March 2012.

F. Chen, A.P. Chandrakasan, and V. Stojanović “Design and Analysis of a Hardware-Efficient Compressed Sensing Architecture for Data Compression in Wireless Sensors,” IEEE Journal of Solid-State Circuits, vol. 47, no. 3, pp. 744-756, March 2012.

F. Lim and V. Stojanović “Non-Asymptotic Analysis of Compressed Sensing Random Matrices : An U-Statistics Approach,” accepted for publication at the IEEE International Conference on Communications, Ottawa, Canada, 6 pages, June 2012.

J.S. Orcutt, B. Moss, C. Sun, J. Leu, M. Georgas, J. Shainline, H. Li, J. Sun, M. Weaver, E. Zgraggen, M. Popovic, R. J. Ram and V. Stojanović, “Low Loss Waveguide Integration within a Thin-SOI CMOS Foundry,” to be presented at IEEE Optical Interconnects Conference, Santa Fe, NM, 2 pages, May 2012.

E. Timurdogan, A. Biberman, D. Trotter, C. Sun, M. Moresco, V. Stojanovic, M. Watts, “Automated Wavelength Recovery for Microring Resonators,” accepted for publication at the Optical Society of America – CLEO/QELS Conference, San Jose, CA, 2 pages, May 2012.

G. Kurian, C. Sun, O. Chen, J. Miller, L. Wei, J. Michel, D. Antoniadis, L-S. Peh, L. C. Kimerling, V. Stojanović and A. Agarwal, “Cross-layer Energy and Performance Evaluation of a Nanophotonic Manycore Processor System using Real Application Workloads,” accepted for publication at the 26th IEEE International Parallel & Distributed Processing Symposium, Shanghai, China, 12 pages, May 2012.

C. Sun, O. Chen, G. Kurian, L. Wei, J. Miller, A. Agarwal, L.-S. Peh, and V. Stojanović, “DSENT – A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling,” accepted for publication at the 6th ACM/IEEE International Symposium on Networks-on-Chip, Lyngby, Denmark, 26 pages, May 2012.

O. Salehi-Abari, F. Chen, F. Lim, and V. Stojanović,”Performance Trade-offs and Design Limitations of Analog-to-Information Converter Front-Ends,” IEEE International Conference on Acoustics, Speech and Signal Processing, Kyoto, Japan, 4 pages, March 2012.

J.C. Leu and V. Stojanović, “Injection-Locked Clock Receiver for Monolithic Optical Link in 45nm, “Asian Solid-State Circuits Conference, Jeju, Korea, pp. 149-152, November 2011.

H. Fariborzi, F. Chen, R. Nathanael, J. Jeon, T-J. K. Liu, and V. Stojanović, “Design and Demonstration of Micro-Electro-Mechanical Relay Multipliers,“ Asian Solid-State Circuits Conference, Jeju, Korea, pp. 117-120, November 2011.

M. Georgas, J.C. Leu, B. Moss, C. Sun, and V. Stojanović, “Addressing Link-Level Design Tradeoffs for Integrated Photonic Interconnects,” [Invited] IEEE Custom Integrated Circuits Conference, San Jose, CA, 8 pages, September 2011.

M. Georgas, J. Orcutt, R. J. Ram, and V. Stojanović, “A Monolithically-Integrated Optical Receiver in Standard 45-nm SOI,“ European Solid-State Circuits Conference, Helsinki, Finland, pp. 407 – 410, September 2011.