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	<title>MTL Annual Research Report 2012 &#187; yu-chung hsiao</title>
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		<title>Compact Modeling of “Nonlinear” Analog Circuits using System Identification with Incremental Stability Certification</title>
		<link>http://www-mtl.mit.edu/wpmu/ar2012/compact-modeling-of-nonlinear-analog-circuits-using-system-identification-with-incremental-stability-certification/</link>
		<comments>http://www-mtl.mit.edu/wpmu/ar2012/compact-modeling-of-nonlinear-analog-circuits-using-system-identification-with-incremental-stability-certification/#comments</comments>
		<pubDate>Wed, 18 Jul 2012 22:28:21 +0000</pubDate>
		<dc:creator>MTL WP admin</dc:creator>
				<category><![CDATA[Circuits & Systems]]></category>
		<category><![CDATA[luca daniel]]></category>
		<category><![CDATA[yu-chung hsiao]]></category>

		<guid isPermaLink="false">http://www-mtl.mit.edu/wpmu/ar2012/?p=5505</guid>
		<description><![CDATA[During recent years, researchers in the Electronic Design Automation community have made great efforts to develop new techniques to automatically...]]></description>
				<content:encoded><![CDATA[<div class="page-restrict-output"><p>During recent years, researchers in the Electronic Design Automation community have made great efforts to develop new techniques to automatically generate accurate compact models of <span style="text-decoration: underline;">“<em>nonlinear”</em></span>system blocks. The majority of the existing methods for creating stable reduced models of nonlinear systems, such as<sup> [<a href="http://www-mtl.mit.edu/wpmu/ar2012/compact-modeling-of-nonlinear-analog-circuits-using-system-identification-with-incremental-stability-certification/#footnote_0_5505" id="identifier_0_5505" class="footnote-link footnote-identifier-link" title="B. Bond and L. Daniel, &ldquo;Stabilizing schemes for piecewise-linear reduced order models via projection and weighting functions,&rdquo; in Proc. of the IEEE Conference on Computer-Aided Design, San Jose, CA, Nov. 2007, pp. 860-867.">1</a>] </sup>, require knowledge of the internal structure of the system, as well as access to the exact model formulation for the original system.  Unfortunately, this information may not be easily available if a designer is using a commercial design tool or may not even exist if the system to be modeled is a physical fabricated device.</p>
<p>As an alternative approach to the standard nonlinear model reduction, we propose a system-identification procedure.  This procedure requires only data available from simulation or measurement of the original system, such as input-output training data pairs. However, simply fitting an arbitrary nonlinear model to the training data does not guarantee that the solution is a valid dynamic model. A valid dynamic model must be stable when evaluated in a time domain simulator. The challenge is to search for a nonlinear dynamic model that simultaneously satisfies the stability requirement and optimally matches the training data. We have managed to formulate such problem as a semi-definite convex optimization problem. The proposed optimization formulation, explained in detail in<sup> [<a href="http://www-mtl.mit.edu/wpmu/ar2012/compact-modeling-of-nonlinear-analog-circuits-using-system-identification-with-incremental-stability-certification/#footnote_1_5505" id="identifier_1_5505" class="footnote-link footnote-identifier-link" title="B. Bond, Z. Mahmood, Y. Li, R. Sredojevic, A. Megretski, V. Stojanovic, Y. Avniel, and L. Daniel, &ldquo;Compact modeling of nonlinear analog circuits using system identification via demi-definite programming and incremental stability certification,&rdquo; IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 29, issue 8, pp. 1149-1162, Aug. 2010.">2</a>] </sup> as an efficient extension of<sup> [<a href="http://www-mtl.mit.edu/wpmu/ar2012/compact-modeling-of-nonlinear-analog-circuits-using-system-identification-with-incremental-stability-certification/#footnote_2_5505" id="identifier_2_5505" class="footnote-link footnote-identifier-link" title="A. Megretski, &ldquo;Convex optimization in robust identification of nonlinear feedback,&rdquo; in Proc. of the IEEE Conference on Decision and Control, Cancun, Mexico, Dec. 2008, pp. 1370-1374.">3</a>] </sup>, allows us to specify completely the complexity of the identified reduced model through the choice of both model order and nonlinear function complexity.</p>
<p>Applications for the proposed modeling technique include analog circuit building blocks such as operational amplifiers and power amplifiers, and individual circuit elements such as transistors.  The resulting compact models may then be used in a higher-level design optimization process of a larger system.  One such example of an analog circuit block is the low-noise amplifier shown in Figure 1; it contains both nonlinear and parasitic elements.  For this example, input-output training data was generated from a commercial circuit-simulator and used to identify a compact nonlinear model. Figure 2 compares the output responses of the original system and the identified model.</p>

<a href='http://www-mtl.mit.edu/wpmu/ar2012/compact-modeling-of-nonlinear-analog-circuits-using-system-identification-with-incremental-stability-certification/hsiao_analogmodeling_01/' title='hsiao_analogmodeling_01'><img width="300" height="197" src="http://www-mtl.mit.edu/wpmu/ar2012/files/2012/07/hsiao_analogmodeling_01-300x197.png" class="attachment-medium" alt="Figure 1" /></a>
<a href='http://www-mtl.mit.edu/wpmu/ar2012/compact-modeling-of-nonlinear-analog-circuits-using-system-identification-with-incremental-stability-certification/hsiao_analogmodeling_02/' title='hsiao_analogmodeling_02'><img width="300" height="262" src="http://www-mtl.mit.edu/wpmu/ar2012/files/2012/07/hsiao_analogmodeling_02-300x262.png" class="attachment-medium" alt="Figure 2" /></a>

<ol class="footnotes"><li id="footnote_0_5505" class="footnote">B. Bond and L. Daniel, “Stabilizing schemes for piecewise-linear reduced order models via projection and weighting functions,” in <em>Proc. of the IEEE Conference on Computer-Aided Design</em>, San Jose, CA, Nov. 2007, pp. 860-867.</li><li id="footnote_1_5505" class="footnote">B. Bond, Z. Mahmood, Y. Li, R. Sredojevic, A. Megretski, V. Stojanovic, Y. Avniel, and L. Daniel, “Compact modeling of nonlinear analog circuits using system identification via demi-definite programming and incremental stability certification,” <em>IEEE Trans. on CAD of Integrated Circuits and Systems</em>, vol. 29, issue 8, pp. 1149-1162, Aug. 2010.</li><li id="footnote_2_5505" class="footnote">A. Megretski, “Convex optimization in robust identification of nonlinear feedback,” in<em> Proc. of the IEEE Conference on Decision and Control</em>, Cancun, Mexico, Dec. 2008, pp. 1370-1374.</li></ol></div>]]></content:encoded>
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		</item>
		<item>
		<title>Modeling and Simulation of Blood Flow in Arterial Networks</title>
		<link>http://www-mtl.mit.edu/wpmu/ar2012/modeling-and-simulation-of-blood-flow-in-arterial-networks/</link>
		<comments>http://www-mtl.mit.edu/wpmu/ar2012/modeling-and-simulation-of-blood-flow-in-arterial-networks/#comments</comments>
		<pubDate>Wed, 18 Jul 2012 22:28:21 +0000</pubDate>
		<dc:creator>MTL WP admin</dc:creator>
				<category><![CDATA[Medical Electronics]]></category>
		<category><![CDATA[healthcare]]></category>
		<category><![CDATA[luca daniel]]></category>
		<category><![CDATA[yu-chung hsiao]]></category>

		<guid isPermaLink="false">http://www-mtl.mit.edu/wpmu/ar2012/?p=5510</guid>
		<description><![CDATA[Understanding certain medical conditions requires understanding specific aspects of the arterial blood flow. For instance, diagnosing atherosclerosis requires capturing detailed...]]></description>
				<content:encoded><![CDATA[<div class="page-restrict-output"><p>Understanding certain medical conditions requires understanding specific aspects of the arterial blood flow. For instance, diagnosing atherosclerosis requires capturing detailed flow inside an arterial segment. Such study requires developing accurate solvers for the detailed equations describing both the blood flow and the elastic behavior of the arteries. At the other end of the spectrum, studying hypertension requires computing pressure and averaged flow over a larger arterial network. Such analysis requires developing compact computationally inexpensive models of complex segments of the arterial network. These models relate the pressure and average flow at the terminals of the arterial segments and must be easily interconnected to form complex and large arterial networks.</p>
<p>In this project we are developing a 2-D fluid-structure interaction solver to accurately simulate blood flow in arteries with bends and bifurcations. Such blood flow is mathematically modeled using the incompressible Navier-Stokes equations. The arterial wall is modeled using a linear elasticity model<sup> [<a href="http://www-mtl.mit.edu/wpmu/ar2012/modeling-and-simulation-of-blood-flow-in-arterial-networks/#footnote_0_5510" id="identifier_0_5510" class="footnote-link footnote-identifier-link" title="A. Quarteroni, M. Tuveri, and A. Veneziani &ldquo;Computational vascular fluid dynamics: problems, models and methods,&rdquo; Computing and Visualization in Science, vol. 2, no. 4, pp. 163-97, 2000.">1</a>] </sup>. Our solver is based on an enhanced immersed boundary method (IBM)<sup> [<a href="http://www-mtl.mit.edu/wpmu/ar2012/modeling-and-simulation-of-blood-flow-in-arterial-networks/#footnote_1_5510" id="identifier_1_5510" class="footnote-link footnote-identifier-link" title="C. Peskin and D. McQueen &ldquo;A three-dimensional computational method for blood flow in the heart I. Immersed elastic fibers in a viscous incompressible fluid.&rdquo; Journal of Computational Physics, vol. 81, issue 2, pp. 372-405, 1989.">2</a>] </sup>. As a second step we are developing system identification techniques<sup> [<a href="http://www-mtl.mit.edu/wpmu/ar2012/modeling-and-simulation-of-blood-flow-in-arterial-networks/#footnote_2_5510" id="identifier_2_5510" class="footnote-link footnote-identifier-link" title="B. Bond, T. Moselhy, and L. Daniel, &ldquo;System identification techniques for modeling of the human arterial system,&rdquo; in Proc. SIAM Conference on the Life Sciences, Pittsburgh, PA, July 2010, p. 12-15. (invited) ">3</a>] </sup> to generate passive models for complex arterial segments such as large arteries, arterial bends, and bifurcations. We have validated our solver results versus reference results obtained from MERCK Research Laboratories for a straight vessel of length 10 cm and diameter 2 cm. Our results for pressure, flow, and radius variations are within 3% of those obtained from MERCK. Furthermore, we are validating our model results by cascading different models and comparing the results of the resulting network to those predicted by our solver. Our preliminary results for pressure and flow at the terminals of the models are within 10% of those obtained from the full simulator. In addition, with our models we reduce the computational time by more than 100,000 times.</p>

<a href='http://www-mtl.mit.edu/wpmu/ar2012/modeling-and-simulation-of-blood-flow-in-arterial-networks/hsiao_cardio_01/' title='hsiao_cardio_01'><img width="300" height="227" src="http://www-mtl.mit.edu/wpmu/ar2012/files/2012/07/hsiao_cardio_01-300x227.png" class="attachment-medium" alt="Figure 1" /></a>
<a href='http://www-mtl.mit.edu/wpmu/ar2012/modeling-and-simulation-of-blood-flow-in-arterial-networks/hsiao_cardio_02/' title='hsiao_cardio_02'><img width="300" height="230" src="http://www-mtl.mit.edu/wpmu/ar2012/files/2012/07/hsiao_cardio_02-300x230.png" class="attachment-medium" alt="Figure 2" /></a>

<ol class="footnotes"><li id="footnote_0_5510" class="footnote">A. Quarteroni, M. Tuveri, and A. Veneziani “Computational vascular fluid dynamics: problems, models and methods,” <em>Computing and Visualization in Science</em>, vol. 2, no. 4, pp. 163-97, 2000.</li><li id="footnote_1_5510" class="footnote">C. Peskin and D. McQueen “A three-dimensional computational method for blood flow in the heart I. Immersed elastic fibers in a viscous incompressible fluid.” <em>Journal of Computational Physics</em>, vol. 81, issue 2, pp. 372-405, 1989.</li><li id="footnote_2_5510" class="footnote">B. Bond, T. Moselhy, and L. Daniel, “System identification techniques for modeling of the human arterial system,” in <em>Proc.</em> <em>SIAM Conference on the Life Sciences,</em> Pittsburgh, PA, July 2010, p. 12-15. (invited) </li></ol></div>]]></content:encoded>
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		<title>CAPLET: A Parallelized Boundary Element Method for VLSI Capacitance Extraction with Instantiable Basis Functions</title>
		<link>http://www-mtl.mit.edu/wpmu/ar2012/caplet-a-parallelized-boundary-element-method-for-vlsi-capacitance-extraction-with-instantiable-basis-functions/</link>
		<comments>http://www-mtl.mit.edu/wpmu/ar2012/caplet-a-parallelized-boundary-element-method-for-vlsi-capacitance-extraction-with-instantiable-basis-functions/#comments</comments>
		<pubDate>Wed, 18 Jul 2012 22:28:21 +0000</pubDate>
		<dc:creator>MTL WP admin</dc:creator>
				<category><![CDATA[Circuits & Systems]]></category>
		<category><![CDATA[luca daniel]]></category>
		<category><![CDATA[yu-chung hsiao]]></category>

		<guid isPermaLink="false">http://www-mtl.mit.edu/wpmu/ar2012/?p=5515</guid>
		<description><![CDATA[Traditional interconnect capacitance extraction tools usually employ 2D scanning and table look-up methods for fast extraction.  For some structures, e.g.,...]]></description>
				<content:encoded><![CDATA[<div class="page-restrict-output"><p>Traditional interconnect capacitance extraction tools usually employ 2D scanning and table look-up methods for fast extraction.  For some structures, e.g., partially overlapping wires and comb capacitors, 2D scanning methods fail to generate accurate results (i.e. within 5% error), therefore using 3D field solvers becomes necessary despite the much slower performance. Accelerated field solvers have been proposed, such as FastCap<sup> [<a href="http://www-mtl.mit.edu/wpmu/ar2012/caplet-a-parallelized-boundary-element-method-for-vlsi-capacitance-extraction-with-instantiable-basis-functions/#footnote_0_5515" id="identifier_0_5515" class="footnote-link footnote-identifier-link" title="K. Nabors and J. White, &ldquo;Fast-Cap: A multipole-accelerated 3-D capacitance extraction program,&rdquo; IEEE Transactions on Computer-Aided Design, vol. 10, no. 10, pp. 1447-1459, Nov. 1991.">1</a>] </sup> and Precorrected FFT<sup> [<a href="http://www-mtl.mit.edu/wpmu/ar2012/caplet-a-parallelized-boundary-element-method-for-vlsi-capacitance-extraction-with-instantiable-basis-functions/#footnote_1_5515" id="identifier_1_5515" class="footnote-link footnote-identifier-link" title="J. R. Phillips and J. K. White, &ldquo;A precorrected-FFT method for electrostatic analysis of complicated 3-D structures,&rdquo; IEEE Transaction on Computer-Aided Design, vol. 16, no. 10, pp. 059-1072, Oct. 1997.">2</a>] </sup> whose accelerations are effective only for large, semi-global structures of hundreds of wires. More importantly,<sup> [<a href="http://www-mtl.mit.edu/wpmu/ar2012/caplet-a-parallelized-boundary-element-method-for-vlsi-capacitance-extraction-with-instantiable-basis-functions/#footnote_2_5515" id="identifier_2_5515" class="footnote-link footnote-identifier-link" title="Y. Yuan and P. Banerjee, &ldquo;A parallel implementation of a fast multipole-based 3-d capacitance extraction program on distributed memory multicomputers,&rdquo; Journal of Parallel and Distributed Computing, vol. 61, no. 12, pp. 1751&ndash;1774, 2001.">3</a>] </sup> and<sup> [<a href="http://www-mtl.mit.edu/wpmu/ar2012/caplet-a-parallelized-boundary-element-method-for-vlsi-capacitance-extraction-with-instantiable-basis-functions/#footnote_3_5515" id="identifier_3_5515" class="footnote-link footnote-identifier-link" title="N. R. Aluru, V. B. Nadkarni, and J. White, &ldquo;A parallel precorrected FFT based capacitance extraction program for signal integrity analysis,&rdquo; in Proceedings of the 33rd Annual Design Automation Conference, 1996, pp. 363-366.">4</a>] </sup> demonstrated that such two acceleration methods are not efficiently parallelizable, showing rapid degradation of parallel efficiency with the number of parallel nodes (40% to 60% at eight nodes).</p>
<p>We propose an efficiently parallelizable acceleration method for local, small-to-medium structures of tens of wires, targeting errors within 5%. We adopt our instantiable basis functions<sup> [<a href="http://www-mtl.mit.edu/wpmu/ar2012/caplet-a-parallelized-boundary-element-method-for-vlsi-capacitance-extraction-with-instantiable-basis-functions/#footnote_4_5515" id="identifier_4_5515" class="footnote-link footnote-identifier-link" title="Y.-C. Hsiao, T. El-Moselhy, and L. Daniel, &ldquo;Efficient capacitance solver for 3d interconnect based on template-instantiated basis functions,&rdquo; IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, 2009, pp. 179&ndash;182.">5</a>] </sup> as a compact charge distribution representation in the boundary element method. Our instantiable basis functions are usually 30 times more compact than traditional piecewise constant (PWC) basis functions<sup> [<a href="http://www-mtl.mit.edu/wpmu/ar2012/caplet-a-parallelized-boundary-element-method-for-vlsi-capacitance-extraction-with-instantiable-basis-functions/#footnote_0_5515" id="identifier_5_5515" class="footnote-link footnote-identifier-link" title="K. Nabors and J. White, &ldquo;Fast-Cap: A multipole-accelerated 3-D capacitance extraction program,&rdquo; IEEE Transactions on Computer-Aided Design, vol. 10, no. 10, pp. 1447-1459, Nov. 1991.">1</a>] </sup><sup> [<a href="http://www-mtl.mit.edu/wpmu/ar2012/caplet-a-parallelized-boundary-element-method-for-vlsi-capacitance-extraction-with-instantiable-basis-functions/#footnote_1_5515" id="identifier_6_5515" class="footnote-link footnote-identifier-link" title="J. R. Phillips and J. K. White, &ldquo;A precorrected-FFT method for electrostatic analysis of complicated 3-D structures,&rdquo; IEEE Transaction on Computer-Aided Design, vol. 16, no. 10, pp. 059-1072, Oct. 1997.">2</a>] </sup><sup> [<a href="http://www-mtl.mit.edu/wpmu/ar2012/caplet-a-parallelized-boundary-element-method-for-vlsi-capacitance-extraction-with-instantiable-basis-functions/#footnote_2_5515" id="identifier_7_5515" class="footnote-link footnote-identifier-link" title="Y. Yuan and P. Banerjee, &ldquo;A parallel implementation of a fast multipole-based 3-d capacitance extraction program on distributed memory multicomputers,&rdquo; Journal of Parallel and Distributed Computing, vol. 61, no. 12, pp. 1751&ndash;1774, 2001.">3</a>] </sup><sup> [<a href="http://www-mtl.mit.edu/wpmu/ar2012/caplet-a-parallelized-boundary-element-method-for-vlsi-capacitance-extraction-with-instantiable-basis-functions/#footnote_3_5515" id="identifier_8_5515" class="footnote-link footnote-identifier-link" title="N. R. Aluru, V. B. Nadkarni, and J. White, &ldquo;A parallel precorrected FFT based capacitance extraction program for signal integrity analysis,&rdquo; in Proceedings of the 33rd Annual Design Automation Conference, 1996, pp. 363-366.">4</a>] </sup> in terms of required basis functions for the same capacitance accuracy (Figure 1). Such compactness not only accelerates the single-node execution (six times in Figure 2.a) but also greatly improves the parallel efficiency (Figure 2.b) by redistributing the computation between the hard parallelizable system solving part (from 90% of total execution to less than 5%) and the embarrassingly parallelizable matrix filling part (from 10% to more than 95%)<sup> [<a href="http://www-mtl.mit.edu/wpmu/ar2012/caplet-a-parallelized-boundary-element-method-for-vlsi-capacitance-extraction-with-instantiable-basis-functions/#footnote_5_5515" id="identifier_9_5515" class="footnote-link footnote-identifier-link" title="Y.-C. Hsiao and L. Daniel, &ldquo;A highly scalable parallel boundary element method for capacitance extraction,&rdquo; Proceedings of the 48th Annual Design Automation Conference, DAC 2011.">6</a>] </sup>. We will release the complete tool set, from input gds2 layout files to capacitance matrices, in the public domain.</p>

<a href='http://www-mtl.mit.edu/wpmu/ar2012/caplet-a-parallelized-boundary-element-method-for-vlsi-capacitance-extraction-with-instantiable-basis-functions/hsiao_fastcaplet_01/' title='hsiao_fastcaplet_01'><img width="300" height="225" src="http://www-mtl.mit.edu/wpmu/ar2012/files/2012/07/hsiao_fastcaplet_01-300x225.png" class="attachment-medium" alt="Figure 1" /></a>
<a href='http://www-mtl.mit.edu/wpmu/ar2012/caplet-a-parallelized-boundary-element-method-for-vlsi-capacitance-extraction-with-instantiable-basis-functions/hsiao_fastcaplet_02/' title='hsiao_fastcaplet_02'><img width="300" height="256" src="http://www-mtl.mit.edu/wpmu/ar2012/files/2012/07/hsiao_fastcaplet_02-300x256.png" class="attachment-medium" alt="Figure 2" /></a>

<ol class="footnotes"><li id="footnote_0_5515" class="footnote">K. Nabors and J. White, “Fast-Cap: A multipole-accelerated 3-D capacitance extraction program,” <em>IEEE Transactions on Computer-Aided Design</em>, vol. 10, no. 10, pp. 1447-1459, Nov. 1991.</li><li id="footnote_1_5515" class="footnote">J. R. Phillips and J. K. White, “A precorrected-FFT method for electrostatic analysis of complicated 3-D structures,” <em>IEEE Transaction on Computer-Aided Design</em>, vol. 16, no. 10, pp. 059-1072, Oct. 1997.</li><li id="footnote_2_5515" class="footnote">Y. Yuan and P. Banerjee, “A parallel implementation of a fast multipole-based 3-d capacitance extraction program on distributed memory multicomputers,” <em>Journal of Parallel and Distributed Computing</em>, vol. 61, no. 12, pp. 1751–1774, 2001.</li><li id="footnote_3_5515" class="footnote">N. R. Aluru, V. B. Nadkarni, and J. White, “A parallel precorrected FFT based capacitance extraction program for signal integrity analysis,” in <em>Proceedings of the 33<sup>rd</sup> Annual Design Automation Conference</em>, 1996, pp. 363-366.</li><li id="footnote_4_5515" class="footnote">Y.-C. Hsiao, T. El-Moselhy, and L. Daniel, “Efficient capacitance solver for 3d interconnect based on template-instantiated basis functions,” <em>IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, </em>2009, pp. 179–182.</li><li id="footnote_5_5515" class="footnote">Y.-C. Hsiao and L. Daniel, “A highly scalable parallel boundary element method for capacitance extraction,” <em>Proceedings of the 48<sup>th</sup> Annual Design Automation Conference, DAC 2011</em>.</li></ol></div>]]></content:encoded>
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