category » Circuits & Systems

Figure 1: Circuit diagram of a 1-2 unipolar stacked switching capacitor energy buffer.
Efficient, Reliable Energy Buffer for Grid-interface Power Conversion with Switched Capacitor Architecture
  • A buffering strategy that utilizes the ability of a capacitor to efficiently operate over a wide voltage range allows increasing…


Figure 1: Block diagram of the proposed time-interleaved SAR ADC.
A 10-b, 1GS/s Time-interleaved SAR ADC with a Background Timing-skew Calibration
  • Figure 1 shows the block diagram of the proposed time-interleaved analog digital converter (ADC) with the associated timing diagram. The…


Figure 1: The design process for optimized hardware and software for computation applications.
Numerical Computation Platform Designed for Optimization
  • Significant effort is spent researching hardware and software acceleration of basic building blocks for numerical computation[1][2][3]; however, the majority of…


Figure 1: Receiver signal processing chain of (a) a traditional receiver system and (b) a bandpass delta sigma modulator system.
A Continuous-Time Bandpass Delta-Sigma Modulator
  • Bandpass delta-sigma modulators (BPDSMs) are a good solution for modern receiver systems. They digitize analog signals directly from the intermediate…


Figure 2: Final driver segments and 2.5 Gb/s eye diagram at 1.23 pJ/b and extinction ratio of 3 dB.  An off-chip tunable laser provides the incoming 1550-nm-band light.
A Monolithically-integrated Optical Carrier-injection Ring Modulator and All-digital Driver Circuit in Commercial 45-nm SOI
  • A monolithically integrated photonic modulator and driver circuit is a key building block toward realizing a dense and energy-efficient communication…


Figure 1: Split system pipeline for HEVC decoder to save 24KB of Coeff SRAM and address variable DRAM latency.
4K Ultra HD Video Decoder for H.265/HEVC
  • High Efficiency Video Coding (HEVC)[1], the latest video standard, uses larger and variable-sized coding units and longer interpolation filters than…


Figure 2: Optical response of the ring filter at minimum and maximum heater power settings (left) and tuning cost per gigahertz, with driver cost included, to reach a specific tuning offset (right).
Integrated Microring Tuning in Deep-trench Bulk CMOS
  • Wavelength-division multiplexed (WDM) silicon-photonic links form a promising alternative to traditional electrical interconnects. However, the essential component of these WDM…


Figure 2: Experimental measurement of input voltage and current waveforms from ac-line operation line (x: 5ms/div (top): 150V/div, (bottom): 100mA/div).
Two-stage Power Conversion Architecture for an LED Driver Circuit
  • LED lighting promises unprecedented reductions in energy consumption, but it comes with an as-yet unmet demand for high power density,…


Figure 1: Electrical double-layer transistor (EDLT) implemented using monolayer MoS2. MoS2 can be grown on a variety of substrates through chemical vapor deposition using S8 and MoO3 at 650°C. MoS2 channel regions are isolated via oxygen plasma etch. Ti/Au source-drain contacts are subsequently deposited using electron beam evaporation.
Flexible High-Density MoS2 Sensor Arrays for Monitoring Action Potentials
  • Monolayer MoS2, a transition metal dichalcogenide, is a novel flexible semiconducting material with a 1.8 eV direct band gap.  Recent…


Figure 1: Block diagram of a time-interleaved (TI) A/D.
Time-interleaved A/D Converters
  • There is an ever-increasing demand for high-resolution and high-accuracy A/D converters in communication systems. In order to raise the sampling…


Figure 1b: Output curves for the device shown in Figure 1a. Dotted lines correspond to experimental data, while solid lines correspond to the VS model.
A Unified Charge-current VS Compact Model for Graphene Transistors Applicable in Analog Circuit Simulations
  • With its rich physics, graphene has properties that make it a viable candidate for implementing electronic devices. For example, graphene…


Figure 1: Modeling the equalization problem: (a) channel state-space representation, (b) block diagram for MPC algorithm. Note that the MPC controller is a function of input bits (horizon) and channel current state.
Beyond Equalization: Model Predictive Control
  • As CMOS technology scales down and the need for higher data rates increases, non-ideal channel characteristics play a critical role…


Figure 2: Block diagram of a CT MASH ΔƩ ADC.
Continuous-time Delta-sigma Analog-to-digital Converters for Application to Multiple-input Multiple-output Systems
  • As wireless communication technology is rapidly advancing, new wireless applications are continuously developed. Figure 1 shows each application space and…


Figure 1: (a) Chip block diagram. (b) Measured EOP under different read operation to write operation ratios and temperatures. EOP changes by more than 2× across different conditions.
Low-power Memory Circuits
  • Transistor scaling has resulted in integration of more functionality on a single die. On-chip memories are responsible for a large…


Figure 2: Chip micrograph.
A 93% Efficiency Reconfigurable Switched-Capacitor DC-DC Converter Using On-Chip Ferroelectric Capacitors
  • Switched-Capacitor (SC) DC-DC converters have gained significant interest as promising candidates for  integrated power conversion solution that eliminates the need…


Figure 1: Block diagram of the planned sensor node.  Optimized, energy-efficient sensor front end and radio components will allow the entire node to be powered from ambient energy harvested from solar, vibration, or thermal sources.
Self-powered Long-range Wireless Microsensors for Industrial Applications
  • Improved monitoring of industrial equipment through the use of vast networks of small, easily installed, long-lasting, reliable wireless sensor nodes…


Figure 1: Block diagram of LED driver.
A 90.6%, 11-MHz, 22-W LED Driver using GaN FETs and a Burst Mode Controller
  • With the advent of reliable, high-brightness and high-efficacy LEDs, the lighting industry is expected to see a significant growth in…


Figure 1: Topology of the proposed resistance compression network converter.
High-efficiency Resonant dc/dc Converter Utilizing a Resistance Compression Network
  • This project presents a new topology for a high-efficiency dc/dc resonant power converter that utilizes a resistance compression network[1],[2].  Unfortunately,…


Figure 2: Test chip in 45-nm SOI for various asynchronous on-chip interconnects.
Single-cycle On-chip Traversal Using SMART Networks-on-chip
  • High-performance chips nowadays use multiple processing cores on the same die, connected by a network-on-chip (NoC). The NoC is a…


Figure 1: WCE pills (PillCam SB and PillCam ESO) from Given Imaging, Inc. The pill contains small cameras, electronics, a radio and batteries.
An Ingestible Pill for Ultrasound Imaging of Small Intestine
  • The small intestine is one of the most difficult organs to image because of its length and narrow winding path….


Figure 1: A diagram of the ESPIOR oscillator, which utilizes the low phase noise properties of a continuous-wave laser as a master oscillator and a mode-locked laser as a frequency divider.
Erbium Silicon Photonic Integrated Oscillators and Radar (ESPIOR)
  • A novel device, erbium silicon photonic integrated oscillators and radar (ESPIOR), is composed of state-of-the-art silicon photonics and erbium-ytterbium based…


Figure 1: Minimum energy versus percent RMS difference (PRD). Compared average (PRDavg) and worst (PRDnet) distortions, 
optimized over compression rate (M) and quantization (QCS).
Building Compressed Sensing Systems
  • Compressed sensing (CS) is a sub-Nyquist sampling technique[1] with under-explored implementation potential. In this multi-disciplinary project, we analyze CS circuit…


Figure 1: (a) The 4T NEM relay and its operating states, (b) a 6-bit relay multiplier built with full and half adders, and (c) an alternative design built with (7:3) and smaller compressors.
Designing Complex Digital Systems with Scaled Nano-electro-mechanical Relays
  • Silicon CMOS circuits have a well-defined lower limit on their achievable energy efficiency due to sub-threshold leakage. Once this limit…


Figure 1: The processor-DRAM interface platform, which consists of a DRAM memory chip and a processor chip with an on-chip Megacell structure and off-chip optical links.
Photonic Processor-DRAM Interface
  • Integrated photonic interconnects enable new possibilities for bandwidth and energy-efficiency driven VLSI applications, such as many-core processor systems, by removing…


Figure 1: The wearable, long-term cardiac monitor is attached to the chest with conventional 3M electrodes. In this configuration, the cardiac monitor measures a lead that mimics a standard Lead II ECG.
A Wearable, Long-term Cardiac Monitor
  • We have developed an experimental cardiac monitor for long-term data acquisition and analysis. The monitor consists of a central printed…


Figure 2: Top view of the floor plan of a wide spectrum image sensor IC.
Graphene-based Wide-spectrum CMOS Image Sensor
  • CMOS image sensors are widely used in digital multimedia applications, and its performance ramps up every year with denser integration,…


Figure 1: (a) Charge distribution represented by 572 piecewise constant basis functions (left) and 17 instantiable basis functions (right). Capacitance errors for both cases are 2% w.r.t. a reference capacitance value extracted by standard BEM with fine discretization. (b) CAPLET GUI and NAND gate visualization.
CAPLET: Field-solver Accurate Real-time Capacitance Extraction Toolkit using Instantiable Basis Functions
  • Traditional capacitance extraction for VLSI interconnects usually adopts 2D scanning and table look-up methods for fast extraction at acceptable accuracy….


Figure 2: Delay probability density comparison between BSIM and VS model for an NAND2 gate (fanout of 3) with a supply voltage of (a) 0.9V, (b) 0.7V and (c) 0.55V. The quantile-quantile plot for delay variation under each
supply voltage in (d) 0.9V, (e) 0.7V and (f) 0.55V shows a strongly nonlinear
pattern in low-power application.
Statistical Modeling with the Virtual Source MOSFET Model
  • In this work, a statistical extension of the ultra-compact virtual source (VS) MOSFET model is developed here for the first…


Figure 1: The architecture of a 3D ultrasound imaging system with CMUT devices.
Analog Front-end Design for Wearable Ultrasound Systems
  • The capacitive micromachined ultrasound transducer (CMUT) is an alternative to traditional piezoelectric transducers. The CMUT technology provides an opportunity for…


Figure 2: Wearable system prototype.
A Subdermal EEG Monitor for Seizure Detection
  • Epilepsy is a common chronic neurological disorder that affects about 1% of the world population[1]. It is characterized by repeated…


Figure 1: The three dimensions of research development for a universal village.
Universal Village: Our Desired Living Conditions
  • Due to the growing populations in cities, resources for city and village residents have become scare while costs for public…


Figure 2: Concept of a wearable TCD monitoring system.
An Electronically Steered, Wearable Transcranial Doppler Ultrasound System
  • The central objective of critical care for patients affected by neurotrauma, cerebrovascular accident (i.e., stroke), and other neurovascular pathologies is…


Figure 2: Left - The vital signs monitor being worn at the ear with ECG electrodes attached. Center - The wearable vital signs monitor.  Right - A PC USB wireless receiver.
A Wearable Vital-signs Monitor at the Ear
  • Vital signs such as heart rate, blood pressure, blood oxygenation, cardiac output, and respiratory rate are necessary in determining the…


Figure 2:  (a) The dominant current path for T-BCC.  (b) The dominant current path for W-BCC.
Body Coupled Communication
  • Body coupled communication (BCC) uses the conductive tissues in the body as a channel to form a body area network…


Figure 2: Small-signal gain of a BJT feedback amplifier, obtained by proposed ST method versus Monte Carlo simulation.
Stochastic Testing Method for Transistor-level Uncertainty Quantification
  • Design and fabrication uncertainties have become an important issue in nano-scale integrated circuit design. Such uncertainties are typically randomly distributed,…


Figure 1: Density function of the total harmonic distortion (THD) and power consumption of a low-noise amplifier (LNA) from our proposed solver.
Uncertainty Quantification for the Periodic Steady State of Forced and Autonomous Circuits
  • Designers are particularly interested in periodic steady-state (PSS) analysis when designing analog/RF circuits or power electronic systems. Such circuits include…


Figure 1: Comparison with the state-of-the-art (data adopted from B. Murmann, “ADC Performance Survey 1997-2012,'' http://www. stanford.edu/~murmann/adcsurvey.html).
Low-power High-performance SAR ADC with Redundancy and Digital Background Calibration
  • A. H. Chang, H.-S. Lee, D. S. Boning Sponsorship: Masdar Institute of Science and Technology There is a growing demand…