Dr. Duane S. Boning is the Clarence J. LeBel Professor in Electrical Engineering, and Professor of Electrical Engineering and Computer Science in the EECS Department at MIT. He is affiliated with the MIT Microsystems Technology Laboratories, and serves as MTL Associate Director for Computation and CAD. He is also the Engineering Faculty Co-Director of the MIT Leaders for Global Operations (LGO) program, serving in that role since September 2016. From 2004 to 2011, he served as Associate Head of the EECS Department at MIT. From 2011 through 2013 he was the Director/Faculty Lead of the MIT Skoltech Initiative, and from 2011 through July 2018, he was the faculty Director of the MIT/Masdar Institute Cooperative Program.
Dr. Boning received his S.B. degrees in electrical engineering and in computer science in 1984, and his S.M. and Ph.D. degrees in electrical engineering in 1986 and 1991, respectively, all from the Massachusetts Institute of Technology. He was an NSF Fellow from 1984 to 1989, and an Intel Graduate Fellow in 1990. From 1991 to 1993 he was a Member Technical Staff at the Texas Instruments Semiconductor Process and Design Center in Dallas, Texas, where he worked on semiconductor process representation, process/device simulation tool integration, and statistical modeling and optimization.
Dr. Boning is a Fellow of the IEEE, and has served as Editor in Chief for the IEEE Transactions on Semiconductor Manufacturing, and as chairman of the CFI/Technology CAD Framework Semiconductor Process Representation Working Group. He is a member of the IEEE, Electrochemical Society, Eta Kappa Nu, Tau Beta Pi, Materials Research Society, Sigma Xi, and the Association of Computing Machinery.
His research interests include the modeling and control of variation in IC, photonics, and MEMS processes, devices, and circuits. Particular emphasis is on statistical characterization and design for manufacturing of devices and circuits in advanced technologies, and the modeling of chemical mechanical polishing (CMP), spin-on coatings, plasma etch, and nanoimprint/embossing processes.
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