A new video standard enables a fourfold increase in the resolution of TV screens, and an MIT chip was the first to handle it in real time. Read more
Undergrad (Fall, Spring)
Involves choosing and developing a research topic, surveying previous work and publications, research topics in EECS, industry best practices, design for robustness, technical presentation, authorship and collaboration, and ethics. Registered students must submit an approved proposal for an Advanced Research Project before Add Date. Forms and instructions are available in the EECS Undergraduate Office. May be repeated for credit for a maximum of 12 units.
A. P. Chandrakasan, D. M. Freeman
Lectures and labs on digital logic, sequential building blocks, finite-state machines, timing and synchronization, and FPGA-based design prepare students for the design and implementation of a final project of their choice: games, music, digital filters, wireless communications, video, or graphics. Extensive use of Verilog for describing and implementing digital logic designs on a state-of-the-art FPGA (see labkit). Students engage in extensive written and oral communication exercises. 12 Engineering Design Points.
Graduate (Fall) H-Level Grad Credit
Prereq: 6.012, 6.004
Device and circuit level optimization of digital building blocks. MOS device models including Deep Sub-Micron effects. Circuit design styles for logic, arithmetic and sequential blocks. Estimation and minimization of energy consumption. Interconnect models and parasitics; device sizing and logical effort; timing issues (clock skew and jitter) and active clock distribution techniques. Memory architectures, circuits (sense amplifiers) and devices. Testing of integrated circuits. Extensive use of circuit layout and SPICE in design projects and software labs. 4 Engineering Design Points.
A. P. Chandrakasan
Researchers at MIT have taken a significant step toward battery-free monitoring systems – which could ultimately be used in biomedical devices, environmental sensors in remote locations and gauges in hard-to-reach spots, among other applications. Read more
MIT EECS Department Head is the 2013 recipient of the IEEE Donald O. Pederson Award in Solid-State Circuits. The citation for the award reads "For pioneering techniques in low-power digital and analog CMOS design." Read more