Recent Publications

Journal articles:

  1. K.N. Chen, S.M. Chang, L.C. Shen, C.S. Tan, A. Fan, and R. Reif, “Process Development of Silicon Layer Stacking Using Copper Wafer Bonding”, to appear in Applied Physics Letters.
  2. K.N. Chen, C.S. Tan, A. Fan, and R. Reif, “Effect of Wafer Bow on Cu wafer Bonding”, submitted to Electrochemical and Solid-State Letters.
  3. C.S. Tan, and R. Reif, “Silicon Multilayer Stacking Based on Copper Wafer Bonding,” Electrochemical and Solid-State Letters8 (6) G147-G149, 2005.
  4. K.N. Chen, C.S. Tan, A. Fan and R. Reif, “Bonding Parameters of Blank Copper Wafer Bonding,” submitted to Journal of Electronic Materials.
  5. K.N. Chen, S.M. Chang, L.C. Shen and R. Reif, “Investigations of Strength of Copper Bonded Wafers with Several Quantitative and Qualitative Tests,” submitted to Journal of Electronic Materials.
  6. K.N. Chen, A. Fan, C.S. Tan and R. Reif, “Effects of Surface Condition and Clean Techniques on Cu Films for the Quality of Cu wafer bonding,” submitted to Journal of Electronic Materials.
  7. C.S. Tan, K.N. Chen, A. Fan and R. Reif, “The effect of forming gas anneal on the oxygen content in bonded Cu layer,” submitted to Electrochemical and Solid-State Letters.
  8. C.S. Tan and R. Reif, “Thin Film Attachment to Silicon Carrier Using Low Temperature Oxide Wafer Bonding,” submitted to Electrochemical and Solid-State Letters.
  9. C.S. Tan, R. Reif, D. Theodore, and S. Pozder, “Observation of Interfacial Voids Formation in Bonded Copper Layer,” submitted to Applied Physics Letters.
  10. K.N. Chen, A. Fan, C.S. Tan and R. Reif, “Abnormal Contact Resistance Reduction of Bonded Copper Interconnects in Three-Dimensional Integration during Current Stressing”, Applied Physics Letters, 86, 011903, 2005.
  11. C.S. Tan, K.N. Chen, A. Fan and R. Reif, “Low temperature direct chemical-vapor-deposition (CVD) oxides to thermal oxide wafer bonding in silicon layer transfer”, Electrochemical and Solid-State Letters, 8(1), pp. G1-G4, 2005.
  12. S. Das, A. Chandrakasan, and R. Reif. "Calibration of Rent's-Rule Models for Three-Dimensional Integrated Circuits." IEEE Trans. on VLSI Systems, vol. 12, no. 4, pp. 359-366, Apr. 2004.
  13. Kuan-Neng Chen, Mauro Kobrinsky, Brandon Barnett and Rafael Reif, “Comparisons of Conventional, 3D, Optical and RF Interconnect for Clock Distribution,” IEEE Trans. on Electron Devices, 51(2), pp 233-239, 2004.
  14. K.N. Chen, A. Fan, C.S. Tan, and R. Reif, “Contact Resistance Measurement of Bonded Copper Interconnects for Three-Dimensional Integration Technology”, IEEE Electron Devices Letters, 25(1), pp 10-12, 2004.
  15. K.N. Chen, C.S. Tan, A. Fan and R. Reif, “Morphology and bond strength of copper wafer bonding”, Electrochemical and Solid-State Letters, 7(1), pp G14-G16, 2004.
  16. K.N. Chen, A. Fan, C.S. Tan, and R. Reif, “Temperature and Duration Effect on Microstructure Evolution During Copper Wafer Bonding”, Journal of Electronic Materials 32(12), pp 1371-1374, 2003.
  17. C.S. Tan, A. Fan, K.N. Chen, and R. Reif, “Low temperature thermal oxide to Plasma Enhanced Chemical Vapor Deposition oxide wafer bonding for thin film transfer application,” Applied Physics Letters, 82(16), pp 2649-2651, 2003.
  18. Arifur Rahman, Shamik Das, Anantha Chandrakasan, and Rafael Reif, “Wiring Requirement and Three-Dimensional Integration Technology for Field Programmable Gate Arrays,” IEEE Trans. on VLSI systems 11(1), pp 44-54, 2003.
  19. K.N. Chen, A. Fan, C.S. Tan and R. Reif, “Microstructure evolution and abnormal grain growth during copper wafer bonding,” Applied Physics Letters, 81(20), pp 3774-3776, 2002.
  20. K.N. Chen, A. Fan, and R. Reif, "Interfacial Morphologies and Possible Mechanisms of Copper Wafer Bonding," Journal of Materials Science, 37(16), pp 3441-3446, 2002.
  21. Kuan-Neng Chen, Andy Fan, and Rafael Reif, "Microstructure Examination of Copper Wafer Bonding," Journal of Electronic Materials 30, 331-335, April 2001.
  22. J.A. Davis, R. Venkatesan, A. Kaloyeros, M. Bylansky, S.J. Souri, K. Banerjee, K.C. Saraswat, A. Rahman, R. Reif, and J.D. Meindl, “Gigascale Integration (GSI) Interconnect Limits in the 21st Century,” invited paper, Special Issue on The Limits of Semiconductor Technology, IEEE Proceedings, vol. 89(3), pp 305-324, 2001.
  23. Arifur Rahman and Rafael Reif, “System Level Performance Evaluation of Three-Dimensional Integrated Circuits,” Special Issue on System Level Interconnect Prediction (SLIP), IEEE Trans. on VLSI, vol. 8(6), pp 671-678, 2000.
  24. A. Fan, A. Rahman, and R. Reif, “Copper Wafer Bonding,” Electrochemical and Solid-State Letters 2(10), 534-536, October 1999