Recent Publications

List of patents filed:

  1. R. Reif, T.J. Donahue, and W.R. Burger, “Growth of Epitaxial Films by Chemical Vapor Deposition Utilizing a Surface Cleaning Step Immediately Before Deposition,” U.S. Patent No. 4,579,609, April 1, 1986.
  2. R. Reif and C.G. Fonstad, “Growth of Epitaxial Films by Plasma Enhanced Chemical Vapor Deposition (PE-CVD),” U.S. Patent No. 4,659,401, April 21, 1987.
  3. R. Reif, P.K. Tedrow, and V. Ilderem, “Low Pressure Chemical Vapor Deposition of Refractory Metal Silicides,” U.S. Patent No. 4,668,530, May 26, 1987.
  4. R. Reif, C.G. Fonstad, and A.D. Huelsman, “Growth of Epitaxial Films by Chemical Vapor Deposition,” U.S. Patent No. 4,773,355, September 27, 1988.
  5. V. Ilderem, R. Reif, and P.K. Tedrow, “Very Low Pressure Chemical Vapor Deposition Process for Deposition of Titanium Silicide Films,” U.S. Patent No. 4,957,777, September 18, 1990.
  6. K.K. O, H-S. Lee, and R. Reif, “Merged Bipolar and Insulated Gate Transistors,” U.S. Patent No. 5,028,977, July 2, 1991.
  7. T. Noguchi, R. Reif, J.A. Tsai, and A.J. Tang, “High Performance Poly SiGe Thin Film Transistor,” U.S. Patent No. 5,828,084, October 27, 1998.
  8. T. Noguchi, R. Reif, J.A. Tsai, and A.J. Tang, “High Performance Poly SiGe Thin Film Transistor and a Method of Fabricating such a Thin Film Transistor,” U.S. Patent No. 6,638,797, October 28, 2003.
  9. S. Karecki, L. Pruette, and R. Reif, “Use of Non-Perfluoro Fluorocarbons for Etching and Cleaning, filed December 4, 1998 (provisional application filed December 4, 1997)
  10. N. Yamauchi, J-J. J. Hajjar, and R. Reif, “Thin Film Transistor,” Serial No. 07/367,446, filed on June 16, 1989.
  11. R. Reif, A. Fan, S. Das, N. Checka, K-N. Chen, C.S. Tan, “Three Dimensional Integration,” provisional application filed December 31, 2002.
  12. R. Reif, S. Das, and A. Fan, “Multi-Layer Integrated Semiconductor Structure,” U.S. Patent Application No. 10/655,854, filed on September 5, 2003.
  13. R. Reif and A. Fan, “Method of Forming a Multi-Layer Semiconductor Structure Having a Seam-Less Bonding Interface,” U.S. Patent ApplicationNo. 10/655,670, filed on September 5, 2003.
  14. R. Reif, N. Checka, and A. Chandrakasan, “Multi-Layer Integrated Semiconductor Structure Having an Electrical Shielding Portion,” U.S. Patent Application No. 10/749,096, filed on December 30, 2003.
  15. R. Reif, A. Fan, K-N. Chen, and C.S. Tan, “Method of Forming a Multi-Layer Semiconductor Structure Incorporating a Processing Handle Member,” U.S. Patent Application No. 10/749,103, filed on December 30, 2003.