Current Research

Three-Dimensional Integration: Analysis, Modeling and Technology Development

Students

Sponsorship

As the critical dimensions in VLSI circuits continue to diminish, system performance of Integrated Circuits (IC) will be increasingly dominated by interconnect's performance. For the technology generations approaching 100-nm, innovative circuit designs and new interconnect materials and architecture will be required to meet the projected system performance. New interconnect materials solutions such as copper and low-k dielectric offer only a limited improvement in system performance. Significant and scalable solutions to interconnect delay problem will require fundamental changes in system architecture, design, and fabrication technologies.

Three dimensional (3-D) IC, devices are allowed to exist on more than one device layer, and they can be contacted from both top and bottom device layers. Flexibility to place devices along the third dimension allows higher device density and smaller chip area in 3-D IC. The critical interconnect paths that limit system performance can also be shortened by 3-D integration to achieve faster clock speed. By 3-D integration, active layers fabricated with different front-end processes can be stacked to form systems on a chip. A cross section of a proposed 3-D integrated circuit/system is shown below.

Recent Publications

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Journal articles:

  1. K. N. Chen, C. S. Tan, A. Fan, and R. Reif, “Effect of Wafer Bow on Cu wafer Bonding”, submitted to Electrochemical and Solid-State Letters.
  2. K. N. Chen, A. Fan, C. S. Tan and R. Reif, “Abnormal Contact Resistance Reduction of Bonded Copper Interconnects in Three-Dimensional Integration during Current Stressing”, Applied Physics Letter, Jan 2005. 
  3. C. S. Tan, K. N. Chen, A. Fan and R. Reif, “Low temperature direct chemical-vapor-deposition (CVD) oxides to thermal oxide wafer bonding in silicon layer transfer”, Electrochemical and Solid-State Letters, 8(1), 2005.
  4. S. Das, A. Chandrakasan, and R. Reif. "Calibration of Rent's-Rule Models for Three-Dimensional Integrated Circuits." IEEE Trans. on VLSI Systems, vol. 12, no. 4, pp. 359-366, Apr. 2004.
  5. Kuan-Neng Chen, Mauro Kobrinsky, Brandon Barnett and Rafael Reif, “Comparisons of Conventional, 3D, Optical and RF Interconnect for Clock Distribution,” IEEE Trans. on Electron Devices, 51(2), pp 233-239, 2004.
  6. K.N. Chen, A. Fan, C.S. Tan, and R. Reif, “Contact Resistance Measurement of Bonded Copper Interconnects for Three-Dimensional Integration Technology”, IEEE Electron Devices Letters, 51(2), pp 10-12, 2004.
  7. K.N. Chen, C.S. Tan, A. Fan and R. Reif, “Morphology and bond strength of copper wafer bonding”, Electrochemical and Solid-State Letters, 7(1), pp G14-G16, 2004.
  8. K.N. Chen, A. Fan, C.S. Tan, and R. Reif, “Temperature and Duration Effect on Microstructure Evolution During Copper Wafer Bonding”, Journal of Electronic Materials 32(12), pp 1371-1374, 2003.
  9. C. S. Tan, A. Fan, K. N. Chen, and R. Reif, “Low temperature thermal oxide to Plasma Enhanced Chemical Vapor Deposition oxide wafer bonding for thin film transfer application,” Applied Physics Letters, 82(16), pp 2649-2651, 2003.
  10. Arifur Rahman, Shamik Das, Anantha Chandrakasan, and Rafael Reif, “Wiring Requirement and Three-Dimensional Integration Technology for Field Programmable Gate Arrays,” IEEE Trans. on VLSI systems 11(1), pp 44-54, 2003.
  11. K. N. Chen, A. Fan, C. S. Tan and R. Reif, “Microstructure evolution and abnormal grain growth during copper wafer bonding,” Applied Physics Letters, 81(20), pp 3774-3776, 2002.
  12. K.N. Chen, A. Fan, and R. Reif, "Interfacial Morphologies and Possible Mechanisms of Copper Wafer Bonding," Journal of Materials Science, 37(16), pp 3441-3446, 2002.
  13. Kuan-Neng. Chen, Andy Fan, and Rafael Reif, "Microstructure Examination of Copper Wafer Bonding," Journal of Electronic Materials 30, 331-335, April 2001.
  14. J. A. Davis, R. Venkatesan, A. Kaloyeros, M. Bylansky, S. J. Souri, K. Banerjee, K. C. Saraswat, A. Rahman, R. Reif, and J. D. Meindl, “Gigascale Integration (GSI) Interconnect Limits in the 21st Century,” invited paper, Special Issue on The Limits of Semiconductor Technology, IEEE Proceedings, vol. 89(3), pp 305-324, 2001.
  15. Arifur Rahman and Rafael Reif, “System Level Performance Evaluation of Three-Dimensional Integrated Circuits,” Special Issue on System Level Interconnect Prediction (SLIP), IEEE Trans. on VLSI, vol. 8(6), pp 671-678, 2000.
  16. A. Fan, A. Rahman, and R. Reif, “Copper Wafer Bonding,” Electrochemical and Solid-State Letters 2 (10), 534-536, October 1999.   

Conference articles:

  1. K.N. Chen, A. Fan, C.S. Tan and R. Reif, “Effects of surface roughness and oxide formation of Cu film on the quality of Cu wafer bonding”, accepted to present in 2005 TMS meeting.
  2. K.N. Chen, A. Fan, C.S. Tan and R. Reif, “Bonding parameters of Cu wafer bonding for 3D Integration”, accepted to present in 2005 TMS meeting.
  3. K.N. Chen, S.M. Chang, L.C. Shen and R. Reif, “Using different test techniques to investigate the bond strength of Cu wafer bonding”, accepted to present in 2005 TMS meeting.
  4. Rafael Reif, Chuan Seng Tan, Andy Fan, Kuan-Neng Chen, Shamik Das, and Nisha Checka, “ Technology and Applications of Three-Dimensional Integration”, Proceedings of 2004 ECS meeting, Honolulu Hi, October 2004.
  5. S. Das, A. Fan, K.-N. Chen, C.S. Tan, N. Checka, and R. Reif. "Technology, Performance, and Computer-Aided Design of Three-Dimensional Integrated Circuits." To appear in Proc. ISPD, Apr. 2004
  6. K.N. Chen, A. Fan, C.S. Tan and R. Reif, “Abnormal Contact Resistance Reduction in Bonded Cu Interconnects Using Pre-Bonding HCl Cleaning",  MRS Fall Meeting, Boston, December 2003.
  7. K.N. Chen, A. Fan, C.S. Tan and R. Reif, “Relation of Contact Resistance Reduction and Process Parameters of Bonded Copper Interconnects in Three-Dimensional Integration Technology”, Proceedings of 2003 ECS meeting, Orlando FL, October 2003.
  8. Kuan-Neng Chen, Andy Fan, Chuan Seng Tan, and Rafael Reif, “Temperature and Duration Effect on Microstructure Evolution During Copper Wafer Bonding”, 2003 TMS meeting, San Diego CA, March 2003.  
  9. S. Das, A. Chandrakasan, and R. Reif. "Three-Dimensional Integration: Performance, Design Methodology, and CAD Tools," Proc. ISVLSI, 2003.
  10. S. Das, A. Chandrakasan, and R. Reif. "Design Tools for 3-D Integrated Circuits," Proc. ASP-DAC, pp. 53-56, Jan. 2003.
  11. R. Reif, C.S.Tan, A.Fan, K.N. Chen, S. Das, and N. Checka, “3-D Interconnects Using Cu Wafer Bonding : Technology and Applications,” Advanced Metallization Conference, San Diego, October 1-3, 2002.
  12. A. Fan, S. Das, K.N. Chen, and R. Reif, ”Fabrication Technologies for Three-Dimensional Integrated Circuits,” IEEE International Symposium on Quality Electronic Design, pp. 33-37, 2002.
  13. A. Rahman, A. Fan and R. Reif, "Thermal Analysis of Three-Dimensional (3-D) Integrated Circuits (ICs)," Proceedings IITC, pp. 157-159, June 2001.
  14. A. Rahman, S. Das, A. Chandrakasan, and R. Reif, "Wiring Requirement and Three-Dimensional Integration of Field-Programmable Gate Arrays," Proc. ACM/IEEE Intl. Workshop. on SLIP, 107-113, April 2001.
  15. A. Fan, K.N. Chen, and R. Reif, “Three-Dimensional Integration with Copper Wafer Bonding”, Electrochemical Society Spring Meeting, ULSI Process Integration Symposium, pp. 124-132, Proceedings Volume 2001-2, Washington, D.C., March 25-29, 2001.  Also, Proceedings of the 199th Meeting of The Electrochemical Society, Volume 2001-1, Abstract 404,Washington, D.C., March 25-29, 2001.
  16. Rafael Reif, Andy Fan, and Arifur Rahman, Material Challenges and Opportunities of Monolithic Three-Dimensional Integration in Microelectronics (keynote talk), Minerals, Metals and Material Society (TMS) Fall Meeting 2000, St. Louis, Missouri.
  17. A. Rahman, A. Fan and R. Reif, "Comparison of Key Performance Metrics in Two- and Three-Dimensional Integrated Circuits," Proceedings IITC, pp.18-20, June 2000.
  18. A. Rahman, A. Fan, J. Chung and R. Reif, "Wire length distribution of Three-Dimensional Integrated Circuits," Proceedings IITC, pp.233-235, June 1999.     
  19. Arifur Rahman, Dimitri Antoniadis, and Anant Agarwal, Study of 3-D Integration of High Performance Logic, SRC/SEMATECH/MARCO Workshop on Interconnects for Systems on a Chip, May 22, 1999, Stanford University, CA.
  20. Arifur Rahman, Andy Fan, and Rafael Reif, Wire-Length Distribution of Three-Dimensional Integrated Circuit, 1999 Workshop on System-Level Interconnect Prediction (SLIP), April 10-11, Monterey, CA.

PFC Alternatives

Personnel

Principal Investigator:

Graduate Students:

Objectives

The goal is to identify possible alternatives for perfluorocompound chemistries for wafer patterning and PECVD (plasma enhanced chemical vapor deposition) chamber cleaning of silicon dioxide and silicon nitride films that do not pose long term environmental problems.  The etch viability of a variety of alternatives will be determined, and the most promising candidates from the etch viability study will be further tested to define both an alternative chamber clean and an alternative wafer patterning process.  The effluents of both processes will be identified with Fourier Transform Infrared Spectroscopy (FTIR) and quadrupole mass spectrometry (QMS) to assess their potential ESH impact.  Finally, beta testing of both alternative processes will be performed at the facilities of industrial collaborators.

Background

Gases such as fully fluorinated alkanes - CF4, C2F6, C3F8 - as well as inorganic compounds like NF3 and SF6, collectively termed as perfluorocompounds (PFCs), are used heavily by the semiconductor industry for the etching of dielectric films in wafer patterning and plasma-enhanced chemical vapor deposition (PECVD) chamber cleaning applications.  Their use and emission is problematic, however, from an environmental standpoint because of the global warming nature of these substances.

Work is being carried out to identify and develop alternative dielectric etch chemistries to be used in wafer patterning and PECVD chamber cleaning processes.  A large pool of candidate chemistries was initially drawn up.  Molecular structure and environmental, safety, and health considerations were used as the selection criteria.  The compounds in this pool were then screened for etch performance in generic tests, so that the development of wafer patterning and PECVD chamber cleaning processes would proceed with a smaller subset of the most promising chemistries.  This report will highlight recent work done in the development of etch processes with alternative chemistries, specifically the unsaturated fluorocarbons (UFCs) for etch.

Method of Approach

The experimental work for this phase of the project has taken place on one of two commercially available etch reactors: an HDP high density plasma etch chamber and an eMax medium density chamber.  Diagnostic tools include optical emission spectroscopy for plasma analysis and FTIR spectroscopy and RGA for effluent analysis. 

Highlights of Recent Results and Accomplishments

Tetrafluoroethylene was used to etch oxide lag wafers on the HDP high density etch chamber.  Good profiles and etch rates were achievable.  The C2F4 processes were harsh on the photoresist.  The best emissions reductions for this chemistry was 55.9% compared to the C3F8 process of comparison.  Better process performance conditions, however, resulted in greater global warming emissions.  The best process performance point displayed only a marginal improvement in global warming emissions compared to a C3F8 based process and an increase in emissions compared to a c-C4F8 process of comparison.  The destruction efficiency of the C2F4 was high for all of the process conditions examined.  The largest component of the total global warming emissions was C2F6.

Hexafluorobenzene was used to etch oxide lag, FTEOS lag, and FTEOS stop-on-nitride wafers.  The best oxide lag process produced an emissions reduction of 96.3% compared to the C3F8 process of comparison.  CHF3 accounted for 75% of the total emissions.  FTEOS lag and FTEOS stop-on-nitride wafers were etched to examine the etch selectivity to a nitride stop layer.  There was virtually no intrusion into the nitride layer, indicating a very high selectivity.  The via profiles, selectivity to photoresist, and etch rates were also good.  Since these film stacks had an ARC layer on top of the FTEOS, a breakthrough step was required.  This ARC breakthrough step used C4F6 as the process gas.  The emissions reduction of this process compared to the C3F8 based process of comparison was 96.7%.  Oxide and FTEOS etch processes based on C6F6 remain the lowest emissions processes of any chemistry or films examined to date.  In addition to exploring a wider process space and determining the selectivity to nitride, the addition of O2 during the etch process was also investigated.  The results of this study were surprising as the addition of O2 resulted in increased polymer deposition on the wafer surface.  This is likely due to increased F scavenging due to liberated H from the photoresist for processes where O2 is added.
The three OSG process conditions that were examined on the eMax medium density etch chamber are listed in Table A-1.  The film stack had a thin antireflective coating (ARC) layer on top of the OSG.  A two-step etch process was required to etch these film stacks: ARC breakthrough and main etch.

Process Name ARC BT
Power (Watts) 		ARC BT
Gas Flows 		ARC BT
Time (s)		 Main Etch
Power (Watts) 		Main Etch
Gas Flows		 Main Etch
Time(s)
eMax-OSG-1 1800 27 sccm C4F8
16 sccm O2
700 sccm Ar		 20 700 10 sccm C4F8
20 sccm O2
100 sccm Ar		 60
eMax-OSG-2 1800 30 sccm C4F6
20 sccm O2
700 sccm Ar		 20 700 10 sccm C4F6
30 sccm O2
100 sccm Ar		 60
eMax-OSG-3 1800 30 sccm C4F6
20 sccm O2
700 sccm Ar		 20 700 10 sccm C4F6
30 sccm O2
100 sccm Ar		 120
Table A-1: OSG film etch conditions examined on the eMax etch chamber.

The eMax-OSG-1 condition is the c-C4F8 reference process.  The via cross sections from this process are shown as Figure A-1.  The etch rate was 2480 Å/min (center) and 2670 Å/min (edge).  The resist remaining is 3870 Å and 3350 Å at the center and edge of the wafer, respectively.  The global warming emissions from this process were 0.339 kgCE.  The majority of the global warming emissions (59.7%) were due to unutilized c-C4F8 process gas.

pfc.ht1pfc.ht2
Figure A-1:  0.20 mm CD via cross sections at center (left) and edge (right) for the eMax C4F8 based process of comparison (eMax-OSG-1 process condition).

The via cross sections from eMax-OSG-2 process condition, using C4F6 as the etch gas for both the ARC breakthrough and the main etch step, is shown as Figure A-2.  This process shows lower photoresist erosion of 4010 Å (center) and 3740 Å (edge) and greater etch rate of 3140 Å/min (center) and 4180 Å/min (edge).  The total global warming emissions from this process were 0.119 kgCE.  This is a reduction of 65.1% compared to the c-C4F8 process.

pfc.ht3pfc.ht4
Figure A-2:  0.20 mm CD via cross sections at center (left) and edge (right) for the eMax C4F6 based process condition eMax-OSG-2.

Process condition eMax-OSG-3 is the same as eMax-OSG-2 except for a longer (120 s vs. 60 s) main etch time.  The via cross sections at this process condition is shown as Figure A-3.  This process displays more photoresist erosion than the shorter process.  The via depths are greater with good etch profiles.  This process had total global warming emissions of 0.195 kgCE, which is a reduction of 42.5% compared to the shorter c-C4F8 process.

pfc.ht5pfc.ht6
Figure A-3:  0.20 mm CD via cross sections at center (left) and edge (right) for the eMax C4F6 based process condition eMax-OSG-3.

The quantity of effluents emitted for all three of the OSG processes is shown as Figure A-4.  It is interesting to note that eMax-OSG-3, for which the main etch step is twice the time of eMax-OSG-2, does not simply have twice the emissions of each of the effluents, as some of the effluents were released during the breakthrough step.  For four of the compounds (CF4, CO, COF2, and HF), the emissions for the long process nearly doubles.  The reason is because the emissions of these effluents are dominated by the main etch step.  The C4F6 destruction efficiency was near complete.  For the c-C4F8 process, the process gas was not completely destroyed.  Since c-C4F8 is a high-GWP gas, this results in significant global warming emissions.  Switching to a C4F6 process allows for lower global warming emissions with similar etch process performance.

pfc.ht7
Figure A-4:  Quantity of each effluent emitted for all three eMax OSG processes.