Transistor design is becoming exciting again. FinFETs will take us to 7nm technology node. Beyond that, we tailor semiconductor bandstructure to optimize transistor behavior. Design-Technology Co-Optimization suggests that perfecting a single transistor is not enough to get a good Power-Performance-Area trade-off. We employ standard library cells as a vehicle for benchmarking transistor and interconnect architectures.
Victor Moroz grew up in Siberia. After getting Ph.D. and doing semiconductor technology development there, he joined a Stanford spin-off Technology Modeling Associates in 1995. Now Victor is a Synopsys Scientist, leading the effort on modeling advanced CMOS transistor design and manufacturing.