From lewin at illinois.edu Wed Jun 3 12:04:46 2015 From: lewin at illinois.edu (Reinhart, Leslie Lewin) Date: Wed, 3 Jun 2015 16:04:46 +0000 Subject: [labnetwork] University of Illinois Urbana-Champaign - RESEARCH ENGINEER POSITION In-Reply-To: <0B48381248D4954CBEE4C4CC8FD100BD64067E23@chimbx3.ad.uillinois.edu> References: <0B48381248D4954CBEE4C4CC8FD100BD64067E23@chimbx3.ad.uillinois.edu> Message-ID: <0B48381248D4954CBEE4C4CC8FD100BD640944A0@chimbx3.ad.uillinois.edu> Greetings, I am an HR Specialist at the University of Illinois at Urbana-Champaign. The Micro and Nanotechnology Laboratory at the University of Illinois at Urbana-Champaign seeks applicants for a Research Engineer to promote research related activities by managing equipment involving semiconductor device fabrication, processes, and some applications in nano-biotechnology. To apply for this position, please visit http://jobs.illinois.edu. Please see the attached posting for more information. Thank you, Leslie Leslie Lewin Reinhart, EdM Human Resources Specialist University of Illinois at Urbana-Champaign College of Engineering | HR Shared Services 203 Engineering Hall, MC-266 1308 W. Green Street Urbana, Illinois 61801 phone 217.300.3872 | fax 217.333.3832 email lewin at illinois.edu | HRSS Wiki Under the Illinois Freedom of Information Act (FOIA), any written communication to or from University employees regarding University business is a public record and may be subject to public disclosure. -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: RESEARCH ENGINEER POSITION.pdf Type: application/pdf Size: 305873 bytes Desc: RESEARCH ENGINEER POSITION.pdf URL: From thejohnnicholson at gmail.com Wed Jun 3 15:42:54 2015 From: thejohnnicholson at gmail.com (John Nicholson) Date: Wed, 3 Jun 2015 15:42:54 -0400 Subject: [labnetwork] Dektak3 configuration(?) problem Message-ID: We have two Dektak3 profilometers with the same problem which I'm hoping is a software or bios configuration problem. It's possible both of these had the bios battery backup die and lost the bios settings or have user induced calibration issues. Both show the error message "Timeout waiting for AD PORT C BIT to SET" when a measurement run is started. The stylus will not lower onto the sample. It's also possible both suffered the same mechanical or electrical failure but I'm hoping someone here can point to an easier fix. Any help would be appreciated. Regards, -- John Nicholson Nanofabrication Laboratories Manager MassNanoTech Nanofabrication Facility Center for Hierarchical Manufacturing University of Massachusetts, Amherst -------------- next part -------------- An HTML attachment was scrubbed... URL: From fouad.karouta at anu.edu.au Thu Jun 4 03:32:29 2015 From: fouad.karouta at anu.edu.au (Fouad Karouta) Date: Thu, 4 Jun 2015 07:32:29 +0000 Subject: [labnetwork] GaP in sputter Message-ID: Dear colleagues, In our multi-users facility in Canberra we do have a sputter with multiple targets used by our users. One suer would like to sputter GaP on Si to be used for solar cells applications. Looking at the MSDS, it stated a certain toxicity related to the element P. I would like to know if anyone is sputtering GaP and what safety rules are taken for example to clean the chamber or just change targets and if there is any potential of forming PH3. Best regards, Fouad Karouta ********************************* Manager ANFF ACT Node Australian National Fabrication Facility Research School of Physics and Engineering Australian National University ACT 0200, Canberra, Australia Tel: + 61 2 6125 7174 Mob: + 61 451 046 412 Email: fouad.karouta at anu.edu.au http://anff-act.anu.edu.au/ -------------- next part -------------- An HTML attachment was scrubbed... URL: From nclay at upenn.edu Thu Jun 4 09:21:09 2015 From: nclay at upenn.edu (Noah Clay) Date: Thu, 4 Jun 2015 09:21:09 -0400 Subject: [labnetwork] GaP in sputter In-Reply-To: References: Message-ID: <8AA4DF1A-BD35-4674-A29D-BB252C2E5B88@upenn.edu> Fouad, We have sputtered GaP at the University of Pennsylvania. We let the researchers run on the system for three days and then tore down all shielding and gun hardware, replacing it with spares. We also foil wrapped any exposed surfaces. It was time consuming and costly and the researchers did not try this work again, thankfully. We did fingerprint the chamber before and after this with RGA. The shielding and hardware changes indicated no P carry after the work was completed. We also sputtered silver and sent it out for SIMS before and after. Afterwards, this indicated a 1e12 cm-3 level of P in the chamber, up from 1e11 cm-3 beforehand. From a safety perspective, we wore cartridge respirators during shielding change. Our assumption was that, as an open load system, P on the chamber walls would be substantially oxidized between runs. <- unlike MBE where the P accumulates and is substantially unreacted. I haven't taken Stat Mech in twenty years, but would guess that P has a greater affinity for O than H. Best, Noah Clay Quattrone Nanofabrication Facility University of Pennsylvania Philadelphia, PA Sent from my iPhone > On Jun 4, 2015, at 03:32, Fouad Karouta wrote: > > Dear colleagues, > > In our multi-users facility in Canberra we do have a sputter with multiple targets used by our users. One suer would like to sputter GaP on Si to be used for solar cells applications. > Looking at the MSDS, it stated a certain toxicity related to the element P. > > I would like to know if anyone is sputtering GaP and what safety rules are taken for example to clean the chamber or just change targets and if there is any potential of forming PH3. > > Best regards, > Fouad Karouta > > ********************************* > Manager ANFF ACT Node > Australian National Fabrication Facility > Research School of Physics and Engineering > Australian National University > ACT 0200, Canberra, Australia > Tel: + 61 2 6125 7174 > Mob: + 61 451 046 412 > Email: fouad.karouta at anu.edu.au > http://anff-act.anu.edu.au/ > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork Sent from my iPhone > On Jun 4, 2015, at 03:32, Fouad Karouta wrote: > > Dear colleagues, > > In our multi-users facility in Canberra we do have a sputter with multiple targets used by our users. One suer would like to sputter GaP on Si to be used for solar cells applications. > Looking at the MSDS, it stated a certain toxicity related to the element P. > > I would like to know if anyone is sputtering GaP and what safety rules are taken for example to clean the chamber or just change targets and if there is any potential of forming PH3. > > Best regards, > Fouad Karouta > > ********************************* > Manager ANFF ACT Node > Australian National Fabrication Facility > Research School of Physics and Engineering > Australian National University > ACT 0200, Canberra, Australia > Tel: + 61 2 6125 7174 > Mob: + 61 451 046 412 > Email: fouad.karouta at anu.edu.au > http://anff-act.anu.edu.au/ > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From kamal.yadav at gmail.com Fri Jun 5 05:33:05 2015 From: kamal.yadav at gmail.com (Kamal Yadav) Date: Fri, 5 Jun 2015 15:03:05 +0530 Subject: [labnetwork] Chamber Cleaning With Gold Contamination Message-ID: Dear All, Though may not make much sense, but would wanted to know if there are any successful cleaning procedures for chamber to remove affect of gold usage/contamination in that chamber. We want to use the chamber with gold pads exposed to the plasma, but at the same time, need to allow those whose devices may get affected from gold [in CMOS]. Any intermediate cleaning/deposition that could significantly (?) reduce the affect. Our chamber [ICPCVD] has been used [5+ years] with gold pads [exposed to plasma] and so far other groups have not reported any issues with their devices, so its working out fine till now. But we want to take precautionary measures if any. Thanks a lot! -- Thanks, Kamal Yadav Sr. Process Technologist Electrical Engineering IIT Bombay Mobile: 7506144798 -------------- next part -------------- An HTML attachment was scrubbed... URL: From myoung6 at nd.edu Fri Jun 5 08:51:09 2015 From: myoung6 at nd.edu (Mike Young) Date: Fri, 5 Jun 2015 08:51:09 -0400 Subject: [labnetwork] Chamber Cleaning With Gold Contamination In-Reply-To: References: Message-ID: Hi Kamal. At risk of being misunderstood, experience in this field motivates me to respond with a blatant, old Americanism: --> If it ain't broke, don't fix it! <-- Having said that, you probably already know that most groups/labs segregate CMOS and compound semiconductor processing equipment for this very reason. Best of luck, --Mike > On Jun 5, 2015, at 5:33 AM, Kamal Yadav wrote: > > Dear All, > > Though may not make much sense, but would wanted to know if there are any successful cleaning procedures for chamber to remove affect of gold usage/contamination in that chamber. > > We want to use the chamber with gold pads exposed to the plasma, but at the same time, need to allow those whose devices may get affected from gold [in CMOS]. Any intermediate cleaning/deposition that could significantly (?) reduce the affect. > > Our chamber [ICPCVD] has been used [5+ years] with gold pads [exposed to plasma] and so far other groups have not reported any issues with their devices, so its working out fine till now. > > But we want to take precautionary measures if any. > > Thanks a lot! > > -- > Thanks, > Kamal Yadav > Sr. Process Technologist > Electrical Engineering > IIT Bombay > Mobile: 7506144798 > -- Michael P. Young (574) 631-3268 (office) Nanofabrication Specialist (574) 631-4393 (fax) Department of Electrical Engineering (765) 637-6302 (cell) University of Notre Dame mike.young at nd.edu B-38 Stinson-Remick Hall Notre Dame, IN 46556-5637 -------------- next part -------------- An HTML attachment was scrubbed... URL: From rvanduse at doe.carleton.ca Fri Jun 5 09:21:49 2015 From: rvanduse at doe.carleton.ca (Rob Vandusen) Date: Fri, 5 Jun 2015 09:21:49 -0400 Subject: [labnetwork] Chamber Cleaning With Gold Contamination In-Reply-To: References: Message-ID: <001801d09f92$9496d960$bdc48c20$@doe.carleton.ca> Hi Kamal. Here at Carleton University our main annual undergrad project is a CMOS device chip. For what it worth our Aluminum evaporation system is also deposits quite a bit of gold for bio sensor type projects. We do try to keep anything that touches the substrates or source material (ie wafer holder jigs, tweezers etc) separate but the chamber and shielding itself just gets coated over and over with no special cleaning. Sodium of course is the one big contaminate we are most concerned with. To my knowledge we have not have had any issues with gold contamination since we started the CMOS/NMOS process more than 15years ago. Though I?m not sure if the same would hold true for your ICP CVD system. Depositing a nitride or polysilicon layer would probably help. Regards Robert Vandusen Technical Officer, Microfabrication Lab Electronics Department Carleton University room: 4184 Mackenzie Building 613-520-5761 rvanduse at doe.carleton.ca From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Kamal Yadav Sent: June-05-15 5:33 AM To: labnetwork at mtl.mit.edu Subject: [labnetwork] Chamber Cleaning With Gold Contamination Dear All, Though may not make much sense, but would wanted to know if there are any successful cleaning procedures for chamber to remove affect of gold usage/contamination in that chamber. We want to use the chamber with gold pads exposed to the plasma, but at the same time, need to allow those whose devices may get affected from gold [in CMOS]. Any intermediate cleaning/deposition that could significantly (?) reduce the affect. Our chamber [ICPCVD] has been used [5+ years] with gold pads [exposed to plasma] and so far other groups have not reported any issues with their devices, so its working out fine till now. But we want to take precautionary measures if any. Thanks a lot! -- Thanks, Kamal Yadav Sr. Process Technologist Electrical Engineering IIT Bombay Mobile: 7506144798 -------------- next part -------------- An HTML attachment was scrubbed... URL: From bcord at umn.edu Fri Jun 5 10:18:04 2015 From: bcord at umn.edu (bryan cord) Date: Fri, 05 Jun 2015 09:18:04 -0500 Subject: [labnetwork] Atomic-layer etching Si in a standard ICP reactor Message-ID: <5571AF9C.1050107@umn.edu> Hi Everyone, I was wondering if anybody had experience with running a basic Cl-based atomic-layer etching process of silicon in a standard plasma etcher. I'm thinking of trying to add it to our Oxford ICP tool as a standard process; if anyone's done or is doing something similar, could you post some process specifics? I've got a basic outline worked out from literature references but it will probably need a lot of tweaking to actually work in our tool. Thanks! -bryan -- Bryan Cord Minnesota Nano Center (MNC) University of Minnesota 115 Union St SE, Rm 153 Minneapolis, MN 55455 612.626.3287 (work) 857.891.6820 (cell) bcord at umn.edu http://wiki.umn.edu/EBPG From bob.henderson at etchedintimeinc.com Fri Jun 5 12:01:07 2015 From: bob.henderson at etchedintimeinc.com (Bob Henderson) Date: Fri, 5 Jun 2015 09:01:07 -0700 Subject: [labnetwork] Chamber Cleaning With Gold Contamination In-Reply-To: References: Message-ID: <000001d09fa8$d5859d10$8090d730$@henderson@etchedintimeinc.com> Kamal: Cleaning a chamber that has been subjected to gold deposition is problematic. Gold as you probably know has no volatile byproducts with which to etch or clean it away after it adheres to a chamber sidewall or even shielding. The re-deposition of gold that is already within your chamber can occur when subjected to ion bombardment from subsequent depositions using various plasma sources like RF or magnetron deposition. This is why when making CMOS circuits even a small amount of gold deposited at the wrong process step like polysilicon deposition on top of gate oxide can cause substantial changes to the resistivity of the gate oxide which is the on/off switch for the transistor within the circuit. Most fabs have strict rules regarding gold in their fabrication areas. As for cleaning you could replace all of your shielding and cover any exposed gold pads with aluminum foil or Kapton tape if temperature is not going to be a problem and hope for the best results. We typically dedicate a chamber to gold use only after it has been used once. Better to separate by process than to have dead circuits at the end of your fabrication. Bob Henderson From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Kamal Yadav Sent: Friday, June 05, 2015 2:33 AM To: labnetwork at mtl.mit.edu Subject: [labnetwork] Chamber Cleaning With Gold Contamination Dear All, Though may not make much sense, but would wanted to know if there are any successful cleaning procedures for chamber to remove affect of gold usage/contamination in that chamber. We want to use the chamber with gold pads exposed to the plasma, but at the same time, need to allow those whose devices may get affected from gold [in CMOS]. Any intermediate cleaning/deposition that could significantly (?) reduce the affect. Our chamber [ICPCVD] has been used [5+ years] with gold pads [exposed to plasma] and so far other groups have not reported any issues with their devices, so its working out fine till now. But we want to take precautionary measures if any. Thanks a lot! -- Thanks, Kamal Yadav Sr. Process Technologist Electrical Engineering IIT Bombay Mobile: 7506144798 -------------- next part -------------- An HTML attachment was scrubbed... URL: From kamal.yadav at gmail.com Sat Jun 6 08:44:34 2015 From: kamal.yadav at gmail.com (Kamal Yadav) Date: Sat, 6 Jun 2015 18:14:34 +0530 Subject: [labnetwork] Chamber Cleaning With Gold Contamination In-Reply-To: References: Message-ID: Dear Mike and Others, Thanks for your reply. We also have strict policies to promote anti contamination. Policies are structured as per SNF policies. Mitigation experiment/procedure of any type is not possible, in this case I suppose. Thanks a lot!. On Fri, Jun 5, 2015 at 6:21 PM, Mike Young wrote: > Hi Kamal. At risk of being misunderstood, experience in this field > motivates me to respond with a blatant, old Americanism: > > --> If it ain't broke, don't fix it! <-- > > Having said that, you probably already know that most groups/labs > segregate CMOS and compound semiconductor processing equipment for this > very reason. > > Best of luck, > > --Mike > > > On Jun 5, 2015, at 5:33 AM, Kamal Yadav wrote: > > Dear All, > > Though may not make much sense, but would wanted to know if there are any > successful cleaning procedures for chamber to remove affect of gold > usage/contamination in that chamber. > > We want to use the chamber with gold pads exposed to the plasma, but at > the same time, need to allow those whose devices may get affected from gold > [in CMOS]. Any intermediate cleaning/deposition that could significantly > (?) reduce the affect. > > Our chamber [ICPCVD] has been used [5+ years] with gold pads [exposed to > plasma] *and so far other groups have not reported any issues with their > devices, so its working out fine till now.* > > But we want to take precautionary measures if any. > > Thanks a lot! > > -- > Thanks, > Kamal Yadav > Sr. Process Technologist > Electrical Engineering > IIT Bombay > Mobile: 7506144798 > > > -- > Michael P. Young (574) 631-3268 (office) > Nanofabrication Specialist (574) 631-4393 (fax) > Department of Electrical Engineering (765) 637-6302 (cell) > University of Notre Dame mike.young at nd.edu > B-38 Stinson-Remick Hall > Notre Dame, IN 46556-5637 > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork > > -- Thanks, Kamal Yadav Sr. Process Technologist Electrical Engineering IIT Bombay Mobile: 7506144798 -------------- next part -------------- An HTML attachment was scrubbed... URL: From vamsinittala at gmail.com Mon Jun 8 00:14:48 2015 From: vamsinittala at gmail.com (N P VAMSI KRISHNA) Date: Mon, 8 Jun 2015 09:44:48 +0530 Subject: [labnetwork] Atomic-layer etching Si in a standard ICP reactor In-Reply-To: <5571AF9C.1050107@umn.edu> References: <5571AF9C.1050107@umn.edu> Message-ID: Dear Bryan, Here is a recipe which we used to etch few nano meters of 200 nm SOI in our OXFORD Plasmalab System 100 tool. BCl3 -15 Cl2 - 10 Chamber Pressure: 9 mT He-10 T Process Temp-10 C ICP- 600-700 W RF-70-80 W ETCH RATE - ~60-75 nm/min You may need to play with pressure and power to lower down the etch rate further. Thanks & best regards, vamsi On Fri, Jun 5, 2015 at 7:48 PM, bryan cord wrote: > Hi Everyone, > > I was wondering if anybody had experience with running a basic Cl-based > atomic-layer etching process of silicon in a standard plasma etcher. I'm > thinking of trying to add it to our Oxford ICP tool as a standard process; > if anyone's done or is doing something similar, could you post some process > specifics? I've got a basic outline worked out from literature references > but it will probably need a lot of tweaking to actually work in our tool. > > Thanks! > > -bryan > > -- > Bryan Cord > Minnesota Nano Center (MNC) > University of Minnesota > 115 Union St SE, Rm 153 > Minneapolis, MN 55455 > 612.626.3287 (work) > 857.891.6820 (cell) > bcord at umn.edu > http://wiki.umn.edu/EBPG > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork > -- -- Thanks & Best Regards, ----------------- *N.P.Vamsi Krishna* Center for Nano Science and Engineering (CeNSE), Indian Institute of Science(IISc), Bangalore. INDIA-560012 ?Educating the mind without educating the heart is no education at all.? -Aristotle -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at stanford.edu Mon Jun 8 14:39:22 2015 From: mtang at stanford.edu (Mary Tang) Date: Mon, 08 Jun 2015 11:39:22 -0700 Subject: [labnetwork] Chamber Cleaning With Gold Contamination In-Reply-To: References: Message-ID: <5575E15A.4080806@stanford.edu> Hi Kamal -- At Stanford, we've been trying to evolve a materials policy that is more accommodating of non-CMOS processing. Even our most die-hard electronics researchers are demanding more flexible processing policies. We try to take special processing requests on a case-by-case basis with the goal of evolving our policies. The 3-tier system we have of clean (front end CMOS), semiclean (backend CMOS) and gold (catch all for everything else, with different classes of "gold") has served us well for many years, but is overly simplistic. We have certainly stretched the definitions when it comes to Litho, for example, where we don't have dedicated clean, semiclean or gold tools. The approach we are trying to take now is to assess where the real transfer risks are (i.e., wafer handling, volatility, ion bombardment, etc.) and what kind of engineering controls might mitigate them. In fact, this has been the underlying rationale for our Litho policy -- contamination risk is minimized because there will always be wet cleans before wafers undergo any high temp processing steps. But back to your question. Our ICP PECVD system is defined as a "flexible" or "all" system, which means that it can be used for CMOS-clean processing, but also for processes that might otherwise be classified as "gold" in our old nomenclature. By default, it is non-CMOS, but can be considered "clean" once a short plasma clean and coat process is performed. The rationale is that any potentially contaminated films previously deposited are removed with the plasma clean and any non-volatiles are covered up by the nitride precoat process. It is also the responsibility of the user to perform this clean and coat if he/she wants a CMOS-compatible process. This doesn't mean that everything can be processed in this system, but would not currently exclude wafers with gold pads. Dr. Jim McVittie, our resident expert in many areas, especially plasma processing, has described an experiment in which he placed a gold sample in a PECVD system (our legacy STS dual frequency, non-ICP, dep system). With an Ar plasma, he found gold deposited on an adjacent sample (analyzed by TXRF). After doing a plasma clean and nitride coat, gold was no longer detectable. Argon sputter probably presents the worst-case situation for carry-over -- most processes would be deposition-only so that gold would be exposed to plasma for minimal time. This result makes us reasonably confident that our PECVD policy is not damaging to the typical electronic devices processed in our lab. We are also trying to evolve our policy with regard to ICP etchers. If you or anyone else has guidelines that accommodate more materials but without significant risk to CMOS devices, I'd really like to learn more. Thanks, Mary -- Mary X. Tang, Ph.D. Stanford Nanofabrication Facility Paul G. Allen Bldg 141, Mail Code 4070 Stanford, CA 94305 (650)723-9980 mtang at stanford.edu http://snf.stanford.edu On 6/5/2015 2:33 AM, Kamal Yadav wrote: > Dear All, > > Though may not make much sense, but would wanted to know if there are > any successful cleaning procedures for chamber to remove affect of > gold usage/contamination in that chamber. > > We want to use the chamber with gold pads exposed to the plasma, but > at the same time, need to allow those whose devices may get affected > from gold [in CMOS]. Any intermediate cleaning/deposition that could > significantly (?) reduce the affect. > > Our chamber [ICPCVD] has been used [5+ years] with gold pads [exposed > to plasma] and so far other groups have not reported any issues with > their devices, so its working out fine till now. > > But we want to take precautionary measures if any. > > Thanks a lot! > > -- > Thanks, > Kamal Yadav > Sr. Process Technologist > Electrical Engineering > IIT Bombay > Mobile: 7506144798 > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From kamal.yadav at gmail.com Thu Jun 11 13:25:45 2015 From: kamal.yadav at gmail.com (Kamal Yadav) Date: Thu, 11 Jun 2015 22:55:45 +0530 Subject: [labnetwork] Chamber Cleaning With Gold Contamination In-Reply-To: <5575E15A.4080806@stanford.edu> References: <5575E15A.4080806@stanford.edu> Message-ID: Dear Mary, Your response is extremely helpful. So Nitride coat in a gold chamber, prior to device process in which gold is a threat can be done. I have emailed you requesting more details on the steps followed to prove this. For the anti-contamination efforts here at IIT Bombay, last year, I have processed clean samples in different equipment, at different stages. New, RCA cleaned, processed without gas/etc. Followed by SR-TXRF. But the synchrotron based TXRF set up is in non-clean room, so after collecting data from different equipment, I paused a bit cauz not sure if results would be reliable. But samples from gold contaminated, For Ex: Ti coated sample in gold contaminated clearly shows peaks of Au, Zn, Cu at TXRF, while these peaks are absent in non processed wafers or RCA cleaned wafers. In fact the ICPCVD I am talking about also does not show any metal peaks for a oxide coated sample in the ICPCVD, while gold pads are allowed in that equipment parallely. I am having little difficulty in quantifying the TXRF results mostly because standards are needed to made in house and in class 10 or so cleanroom, and our SR-TXRF is also situated in non clean room. I am trying to figure out if our TXRF set up could lead to some reasonable conclusion in the E10/E11 atoms/sq. cm. Metal contaminants could be minimal in non clean room area and may be non clean room works. This should help in structuring the anti contamination policy in more optimized way, in fact that was the idea when we started this activity. But it will take sometime. Thanks a lot! On Tue, Jun 9, 2015 at 12:09 AM, Mary Tang wrote: > Hi Kamal -- > > At Stanford, we've been trying to evolve a materials policy that is more > accommodating of non-CMOS processing. Even our most die-hard electronics > researchers are demanding more flexible processing policies. We try to take > special processing requests on a case-by-case basis with the goal of > evolving our policies. The 3-tier system we have of clean (front end CMOS), > semiclean (backend CMOS) and gold (catch all for everything else, with > different classes of "gold") has served us well for many years, but is > overly simplistic. We have certainly stretched the definitions when it > comes to Litho, for example, where we don't have dedicated clean, semiclean > or gold tools. The approach we are trying to take now is to assess where > the real transfer risks are (i.e., wafer handling, volatility, ion > bombardment, etc.) and what kind of engineering controls might mitigate > them. In fact, this has been the underlying rationale for our Litho policy > -- contamination risk is minimized because there will always be wet cleans > before wafers undergo any high temp processing steps. > > But back to your question. Our ICP PECVD system is defined as a "flexible" > or "all" system, which means that it can be used for CMOS-clean processing, > but also for processes that might otherwise be classified as "gold" in our > old nomenclature. By default, it is non-CMOS, but can be considered "clean" > once a short plasma clean and coat process is performed. The rationale is > that any potentially contaminated films previously deposited are removed > with the plasma clean and any non-volatiles are covered up by the nitride > precoat process. It is also the responsibility of the user to perform this > clean and coat if he/she wants a CMOS-compatible process. This doesn't mean > that everything can be processed in this system, but would not currently > exclude wafers with gold pads. > > Dr. Jim McVittie, our resident expert in many areas, especially plasma > processing, has described an experiment in which he placed a gold sample in > a PECVD system (our legacy STS dual frequency, non-ICP, dep system). With > an Ar plasma, he found gold deposited on an adjacent sample (analyzed by > TXRF). After doing a plasma clean and nitride coat, gold was no longer > detectable. Argon sputter probably presents the worst-case situation for > carry-over -- most processes would be deposition-only so that gold would be > exposed to plasma for minimal time. This result makes us reasonably > confident that our PECVD policy is not damaging to the typical electronic > devices processed in our lab. > > We are also trying to evolve our policy with regard to ICP etchers. If > you or anyone else has guidelines that accommodate more materials but > without significant risk to CMOS devices, I'd really like to learn more. > > Thanks, > > Mary > > > -- > Mary X. Tang, Ph.D. > Stanford Nanofabrication Facility > Paul G. Allen Bldg 141, Mail Code 4070 > Stanford, CA 94305 > (650)723-9980 > mtang at stanford.edu > http://snf.stanford.edu > > > > > On 6/5/2015 2:33 AM, Kamal Yadav wrote: > > Dear All, > > Though may not make much sense, but would wanted to know if there are > any successful cleaning procedures for chamber to remove affect of gold > usage/contamination in that chamber. > > We want to use the chamber with gold pads exposed to the plasma, but at > the same time, need to allow those whose devices may get affected from gold > [in CMOS]. Any intermediate cleaning/deposition that could significantly > (?) reduce the affect. > > Our chamber [ICPCVD] has been used [5+ years] with gold pads [exposed to > plasma] and so far other groups have not reported any issues with their > devices, so its working out fine till now. > > But we want to take precautionary measures if any. > > Thanks a lot! > > -- > Thanks, > Kamal Yadav > Sr. Process Technologist > Electrical Engineering > IIT Bombay > Mobile: 7506144798 > > > _______________________________________________ > labnetwork mailing listlabnetwork at mtl.mit.eduhttps://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork > > > -- Thanks, Kamal Yadav Sr. Process Technologist Electrical Engineering IIT Bombay Mobile: 7506144798 -------------- next part -------------- An HTML attachment was scrubbed... URL: From IRHarvey at eng.utah.edu Fri Jun 12 17:53:03 2015 From: IRHarvey at eng.utah.edu (Ian Harvey) Date: Fri, 12 Jun 2015 15:53:03 -0600 Subject: [labnetwork] Call for Participation - UGIM '16 References: Message-ID: <92BD6BCC-D213-4D83-91C2-A464785E9231@eng.utah.edu> Call for Participation - UGIM '16 Hosted by the University of Utah Nanofab in Salt Lake City, UT: June 12-14, 2016 (optional workshops on 15th, 16th) http://ugim.nanofab.utah.edu Dear Colleagues, This note marks the one year start of countdown to UGIM, 2016 in Salt Lake City. The first part of this note briefly describes the draft conference plan. Please let us know at our website if you think you may be attending. Registration will come later. This just helps us with pre-planning. The second part of the note covers Help Wanted! Also see the Call for Participation tab at our website! looking forward to seeing all of you in Utah! Thanks, Ian Harvey, Amy Vanroosendaal and the Utah crew http://ugim.nanofab.utah.edu Quick Conference Overview: Thanks to terrific organizing by the Harvard crew collecting feedback from UGIM'14 attendees, we kept the basic format and experiment with some tweaks ? Registrants will be able to download the presentations as voluntarily provided by the speakers ? There is a great opportunity for active participation and interaction in this conference, versus passive attendance, via panel discussions, topical and role-based working lunches, and institutional poster sessions ? Working sessions will be documented with summaries distributed to UGIM participants Quick Site Overview: ? SLC is a major Delta Airlines hub ? EZ 30 min access from Salt Lake International Airport by car ? Light rail: door-to-door from airport to guest house, conference venue and Utah Nanofab (also downtown area and shopping, including Trader Joe's) Sunday June 12th (not Father's day): ? Bootie Camp concurrent with NNCI coordination meeting ? Evening reception at Utah Nanofab (UGIM Steering Committee meets separately) ? Station-based tours of Utah Nanofab: gowned, nether spaces, integrated surface analysis and nano-scale imaging (experts at each of 16 locations to provide specific information, Q&A) Integrated symposium and exhibition in a single location for two days Vendor Exhibition Integrated with break food tables. Four half-hour breaks plus two working lunches (same room) UGIM'18 announced prior to first break so vendor/host coordination can begin early Monday June 13th: ? Keynotes from the Semiconductor Industry, NNIN/NNCI Reboot ? Cutting edge fabrication techniques (invited) -Working lunch, hot topics by table ? After lunch de-briefing session by facilitators from each table ? Panel Session: Safety / Panelists to briefly talk about specific issues (24/7, buddy system, HF protocols, user discipline, PI involvement, other?), followed by open questions -Evening: sponsored tour/dinner: buses, dinner, tour of Intel-Micron Flash Technologies (IMFT) 12" wafer fab, 45 minutes away Tuesday June 14th: ? Tool Selection: submitted papers on topics ranging through budgeting, evaluating, comparing, acquiring, accepting tools, managing import and customs issues. ? Outreach and educational role of User Facilities: Submitted papers describing role in teaching scaling engineering, participation in or availability of MEMS competitions, survey of peer best practices and bibliography of shared media for micro/nano outreach, education and safety training - Working lunch: Roles by table ? Fab efficiency and continuous improvement: submitted papers describing best practices. Looking for at least one paper describing issues unique to international facilities. Looking for at least one paper describing the nature of integrated facilities (integrating "bio" function inside cleanrooms, and/or integrating analytical microscopy with cleanroom administration). ? Panel Session: Financial management - the forbidden "S" word (subsidy), monitoring, success metrics, appeasing stakeholders, ROI, more-so than billing models and cost management, covered in previous symposia. Closing Banquet in the mountains, 30-45 minutes away Wednesday and TBD Thursday June 15th, 16th: Optional workshops on specific topics TBD. (Added fee) ? Additional guided tours of Utah Nanofab Cleanroom ? Two hours per workshop for sufficient detail, including demonstrations ? Expert presenters (propose topics) ? May extend to two days if interest dictates Help Wanted: Program Committee members - Set questions that establish the scope of the presentation sessions. Select session chairs, accept papers, and serve as session chair Panel Coordination Committee members - Participate in preparing and administering a formal survey on the topic, and present results in the panel pre-discussion. Formulate questions for speakers to answer, and manage brief introductions to each panelist and their question(s). Facilitate discussion among the panel and questions to the panel from the audience. Collect notes from the discussion for distribution to attendees. Possible panelist. Possible Panel Moderator. Sponsorship committee members - Set sponsorship levels and recruit exhibitors and post-UGIM workshop instructors, per the sponsor/exhibitor page Working lunch (topical - M, role - Tu) committee members - Prioritize topics, organize tables and topics with facilitators, manage topical debriefing discussion in session following Monday lunch, correlate and distribute summary results to all attendees, coordinate any follow-up, serve as topical facilitators Working lunch (topical - M, role - Tu) discussion facilitators - Research lab network related topics in advance and prepare a bibliographic summary of key points related to that topic. Frame relevant questions on the topic for review by the committee and for copying by UGIM staff prior to the lunch. Summarize key discussion points and any action items verbally during debriefing session, and then include any feed-back from debrief in written summary for distribution to attendees. Institutional Cleanroom Poster Session Committee Members - Prepare a PowerPoint or other template containing basic information to be solicited from all attending institutions (e.g., basic metrics, basic facts, how the institution manages basic issues like tool pricing, 24/7, safety buddy, etc.). Invite the institution to provide this info plus 3-4 other slides of their own choosing to be printed by UGIM staff in advance of the exhibition. Posters will be displayed along with the vendor exhibition both days. Organizing Committee Members - Assist with logistics and organization Weds/Thurs post-UGIM Workshop Instructor or co-Panelist - For vendors or topical experts to provide orientation-style information and detailed expert information on one of the topics listed on the website workshop survey page. The intent is to be informational without being a commercial sales pitch. The shared knowledge should be generalized, and not specific to a product or product line. (See sponsorship tab on this website) -------------- next part -------------- An HTML attachment was scrubbed... URL: From swolcott at uchicago.edu Wed Jun 17 16:06:29 2015 From: swolcott at uchicago.edu (Sally J. Wolcott) Date: Wed, 17 Jun 2015 20:06:29 +0000 Subject: [labnetwork] Equipment Engineer Positon Available Message-ID: The University of Chicago Pritzker Nanofabrication Facility is actively recruiting for an Equipment Engineer. To view the posting please visit UChicago jobs at https://jobopportunities.uchicago.edu/applicants/jsp/shared/Welcome_css.jsp and search for posting 098428. To be considered for this positon you must apply via UChicago Jobs. Sally Wolcott Business Manager, Pritzker Nanofabrication Facility Institute for Molecular Engineering University of Chicago 5555 South Ellis Avenue Young 006D Chicago, IL 60637 Office: 773-834-3548 Mobile: 773-332-1196 swolcott at uchicago.edu ime.uchicago.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From xiaojin.wang at louisville.edu Wed Jun 17 17:05:25 2015 From: xiaojin.wang at louisville.edu (xiaojin.wang at louisville.edu) Date: Wed, 17 Jun 2015 21:05:25 +0000 Subject: [labnetwork] help on MVD100 Message-ID: Dear colleagues: We have a MVD100 system from Applied microstructure. The system cannot be powered on lately and the issue has been identified as a bad AC/DC converter. We need to replace that part. Does anyone know how to take it out properly? Thank you. [cid:image001.png at 01D0A91F.CCD6BD90] Best wishes Xiaojin Wang Senior process engineer Micro/nano technology center University of Louisville -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.png Type: image/png Size: 247819 bytes Desc: image001.png URL: From shott at stanford.edu Thu Jun 18 00:08:54 2015 From: shott at stanford.edu (John Shott) Date: Wed, 17 Jun 2015 21:08:54 -0700 Subject: [labnetwork] help on MVD100 In-Reply-To: References: Message-ID: <55824456.4010008@stanford.edu> Xiaojin: Let me start by saying that I know nothing about the MVD100 from Applied microstructure. However, for what you are asking, that may not matter ... This appears to be a system that is mounted on a top and bottom DIN rail ... although it it hard to tell for certain from the picture. I think that you are asking how to remove the AC/DC converter from the row of devices on the lower DIN rail and then later replace it. Do I have that right? If so, I think that I can help ... but, I should ask you to confirm that before either wasting your time or that of the other members of this community. Are you asking how to remove components from DIN rail (also known as top hat rail)? Thanks, John On 6/17/2015 2:05 PM, xiaojin.wang at louisville.edu wrote: > > Dear colleagues: > > We have a MVD100 system from Applied microstructure. The system cannot > be powered on lately and the issue has been identified as a bad AC/DC > converter. We need to replace that part. Does anyone know how to take > it out properly? Thank you. > > Best wishes > > Xiaojin Wang > > Senior process engineer > > Micro/nano technology center > > University of Louisville > > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: image/png Size: 247819 bytes Desc: not available URL: From mmoneck at andrew.cmu.edu Thu Jun 25 14:15:47 2015 From: mmoneck at andrew.cmu.edu (Matt Moneck) Date: Thu, 25 Jun 2015 14:15:47 -0400 Subject: [labnetwork] Employment Opportunity - Process Engineer - Carnegie Mellon University Nanofabrication Facility Message-ID: <558C4553.6040703@andrew.cmu.edu> Hello All, The Carnegie Mellon University Nanofabrication Facility is currently looking for a Cleanroom Process Engineer on the Pittsburgh, PA campus. Qualified individuals are encouraged to apply at https://cmu.taleo.net/careersection/2/jobdetail.ftl?job=2001281 Please feel free to pass this message along to interested colleagues. Thank you for your time. Best Regards, Matt Moneck -- *Matthew T. Moneck, Ph.D.* Executive Manager, Carnegie Mellon Nanofabrication Facility Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.5430 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From fouad.karouta at anu.edu.au Fri Jun 26 00:48:56 2015 From: fouad.karouta at anu.edu.au (Fouad Karouta) Date: Fri, 26 Jun 2015 04:48:56 +0000 Subject: [labnetwork] Problem with a Dektak XT profiler Message-ID: Dear all, We have a problem with our Dektak XT surface profiler: when we click on "Tower Down" the stylus goes down, touch the sample and shortly after it goes all the way up. Hence no measurements can be performed. We had a service visit but the problem is not yet solved. Has anyone encounter a similar problem? If yes, how was it solved? Thanks, Fouad Karouta ********************************* Manager ANFF ACT Node Australian National Fabrication Facility Research School of Physics and Engineering Australian National University ACT 0200, Canberra, Australia Tel: + 61 2 6125 7174 Mob: + 61 451 046 412 Email: fouad.karouta at anu.edu.au http://anff-act.anu.edu.au/ -------------- next part -------------- An HTML attachment was scrubbed... URL: From mmoneck at andrew.cmu.edu Fri Jun 26 11:47:40 2015 From: mmoneck at andrew.cmu.edu (Matt Moneck) Date: Fri, 26 Jun 2015 11:47:40 -0400 Subject: [labnetwork] Correction: Employment Opportunity - Process Engineer - Carnegie Mellon University Nanofabrication Facility Message-ID: <558D741C.6050307@andrew.cmu.edu> Hello All, I apologize for the spam, but it has been brought to my attention that the embedded link in my previous email was not functioning properly. The Carnegie Mellon University Nanofabrication Facility is currently looking for a Cleanroom Process Engineer on the Pittsburgh, PA campus. Qualified individuals are encouraged to apply at the updated link: https://cmu.taleo.net/careersection/2/jobdetail.ftl?job=2001281 Please feel free to pass this message along to interested colleagues. Thank you for your time. Best Regards, Matt Moneck -- *Matthew T. Moneck, Ph.D.* Executive Manager, Carnegie Mellon Nanofabrication Facility Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.5430 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu -- *Matthew T. Moneck, Ph.D.* Executive Manager, Carnegie Mellon Nanofabrication Facility Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.5430 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: