[labnetwork] Need help with RIE process

[Michael Khbeis]

Rick

I second Mac on adding a dechuck step. You can use N2 plasma too. 

Dr. Michael Khbeis
Washington Nanofab Facility
University of Washington
Fluke Hall, Box 352143
(O) 206.543.5101
(C) 443.254.5192
khbeis at uw.edu

> On Mar 4, 2015, at 9:38 AM, Mac Hathaway <hathaway at cns.fas.harvard.edu> wrote:
> 
> Hi Rick,
> 
> That's definitely arcing.  Question is, when is it occurring...  It's been a while since I worked with electrostatic chucks, but as I recall, you can build up static charges on fully covered wafers, during plasma processes.  The problems we used to see were that the wafer would stick along one edge when the lifter pins came up, and I think we could even see the arcing at the point of contact when the wafer finally "unstuck".  
> 
> Do these wafers have oxide on both sides?.... Also, is there a window where you can watch the wafer during de-chucking?
> 
> What we used to do, if I remember correctly, was to run a weak argon (?) plasma at the end of the etch, which we called the "dechuck" step.  It took a bit of tuning to get it right.  You could even try keeping it on while the pins are coming up, to allow a discharge path behind the wafer, but that will be a function of your software, and hardware interlocks.  Lastly, sometimes this problem goes away if you just give the dechuck step more time, to allow excess static charge to bleed off.
> 
> As I say, it was a while ago, so there may be more recent approaches to incomplete dechucking that I'm not aware of.
> 
> 
> Mac
> 
> Mac Hathaway
> Senior Process and Systems Engineer
> Harvard Center for Nanoscale Systems
> 11 Oxford St.
> Cambridge, MA  02138
> 617-495-9012
>  
> 
>> On 3/4/2015 7:08 AM, Morrison, Richard H., Jr. wrote:
>> Hi everyone,
>>  
>> I have a strange problem that I need some help with. We have an  Ulvac NE-550 RIE system with an electrostatic chuck. The wafer is a double sided polish with 1um of SiO2. One side has an AZ4620 resist pattern 8um thick to etch the 1um of oxide. Because the process runs hot we break the etch into 9 different steps and move into the LL after every step. On the polished side that is down on the ESC check we have craters on the surface that look like a lightning strike or meteor strike, this is fairly deep several microns.
>>  
>> I have attached a photo of the damage. Have any of you seen anything like this? I need to fix the issue because the side that is down ends up being the frontside of the wafer and that is a killer defect. We think the oxide is charging and when the lift pins come up (at ground potential)           we get a discharge.
>>  
>> Rick
>>  
>>  
>> Draper Laboratory
>> Principal  Member of the Technical Staff
>> Group Leader Microfabrication Operations
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>>  
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>> rmorrison at draper.com
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>>  
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