From bob at eecs.berkeley.edu Mon Nov 2 12:35:26 2015 From: bob at eecs.berkeley.edu (Robert M. HAMILTON) Date: Mon, 2 Nov 2015 09:35:26 -0800 Subject: [labnetwork] Question re: parylene processing Message-ID: I am forwarding a query from a colleague to see if someone reading the labnetwork has experience and recommendations about this parylene issue: *Papers show paryleneC becomes crystalline, tensile & cracks when baked above 80C in atmosphere, simple tests on hot plates confirm this finding. Does anyone have experience when paryleneC is exposed to a resist bake after resist is coated on top of the parylene? * *If you do have this experience, with a resist coating and bake on a parylene substrate, what was the temperature exposure and ambient? Did the parylene crack or change properties during the bake?* *Or, was the resist bake done in an N2 or Ar or vacuum environment & what was the temperature exposure of the bake?* Regards, Bob Hamilton Robert Hamilton University of CA, Berkeley Marvell NanoLab Equipment Manager Rm 520 Sutardja Dai Hall, MC 1754 Berkeley, CA 94720 Phone 510-809-8618 (desk - preferred) Mobile 510-325-7557 (my personal mobile) E-mail preferred: bob at eecs.berkeley.edu http://nanolab.berkeley.edu/ -------------- next part -------------- An HTML attachment was scrubbed... URL: From vito.logiudice at uwaterloo.ca Fri Nov 6 13:42:33 2015 From: vito.logiudice at uwaterloo.ca (Vito Logiudice) Date: Fri, 6 Nov 2015 18:42:33 +0000 Subject: [labnetwork] Sapphire substrates: precision scribe & break Message-ID: Dear Colleagues, I would appreciate hearing from anyone whom might be able to share some insights on how to reliably scribe & break sapphire substrates. We?re attempting to help out a couple of research groups here with such a requirement. We?ve had success with our water-cooled dicing saw but it appears this approach leads to unacceptable materials issues. We thus find ourselves having to resort to some sort of precision (& repeatable) scribe and break technique/setup which will result in consistently smooth sidewalls. Thank you for any insights on procedures you may be using or equipment vendors you have worked with whom might be able to help. Best regards, Vito -- Vito Logiudice P.Eng. Director of Operations, Quantum NanoFab University of Waterloo Lazaridis QNC 1207 200 University Avenue West Waterloo, ON Canada N2L 3G1 Tel.: (519) 888-4567 ext. 38703 Email: vito.logiudice at uwaterloo.ca Website: https://fab.qnc.uwaterloo.ca -------------- next part -------------- An HTML attachment was scrubbed... URL: From kevin.walsh at louisville.edu Fri Nov 6 18:02:06 2015 From: kevin.walsh at louisville.edu (kevin.walsh at louisville.edu) Date: Fri, 6 Nov 2015 23:02:06 +0000 Subject: [labnetwork] 2 open faculty positions at UofL Message-ID: <0D1ABD6DF2541B42A05BD6E6D36954110141A7466A@exmbx18> I please to announce 2 open faculty positions at the University of Louisville in the research thrust areas of Advanced Manufacturing and/or Sustainability. These are interdisciplinary research areas and the successful candidate will be comfortably placed in their most appropriate engineering academic department. The University of Louisville just became part of the NSF next generation NNIN, which is called the NNCI (National Nanotechnology Coordinated Infrastructure). Our site's theme is advanced multi-scale manufacturing, consistent with this search. I encourage candidates to consider this opportunity in the fine City of Louisville. Two Faculty Positions in Advanced Manufacturing and Sustainability at J.B. Speed School of Engineering, U of Louisville J.B. Speed School of Engineering invites applications from exceptional candidates with proven track record to strengthen the 21st century university research initiatives in advanced manufacturing and sustainability. The positions are expected at a rank of associate professor and will be housed in the appropriate discipline based on the candidate's educational qualifications and research interests. The following list of topics represent our preference but are not exclusive in nature. Sustainability: Renewable energy (solar, biomass, energy storage, advanced energy materials), energy efficiency (lighting and catalysis), nitrogen/phosphorous cycles, accelerated materials discovery, and advanced application and design. Advanced Manufacturing: Additive manufacturing and 3D printing; digital manufacturing and digital design; multi-scale manufacturing and integration; novel high throughput, low cost processes such as roll-to-roll, inkjet printing and micro-embossing, next generation micro and nano fabrication; smart materials for advanced manufacturing; bio-integrated and bio-compatible manufacturing. The chosen faculty candidates are expected to leverage resources and facilities available at our existing centers of excellence including Conn Center for Renewable Energy Research, and the Micro/NanoTechnology Center (www.louisville.edu/micronano), Additive Manufacturing Research Center. The candidates must have an earned Ph.D degree in an engineering discipline, and outstanding records of scientific research, doctoral student mentoring, and continuous research funding. The successful candidates will develop an imaginative research program that is both transformational and translational in nature and contribute to both undergraduate and graduate teaching. Applicants should apply online for Job ID 463 at (https://highereddecisions.com/uofl/current_vacancies.asp). The letter of application should indicate their qualifications, a current curriculum vitae, a short description of research and teaching plans along with a contact list of three or more references. Applications will be reviewed beginning December 1st, 2015 and applications will be received until the positions are filled. The expected start date is August 15, 2016. The University of Louisville is a state-supported metropolitan research university located in Kentucky's largest urban area. The J.B. Speed School of Engineering is located in the 177 acre Belknap campus. Louisville has world-class performing arts, great sports, a nationally acclaimed parks system and is home to the Kentucky Derby. It was named one of America's Breakout Cities for 2014 by CNN Money, the top travel destination for 2013 by Lonely Planet and the Most Livable City in America (large city category) in 2012 by the U.S. Conference of Mayors. The University of Louisville is an Affirmative Action, Equal Opportunity, Americans with Disabilities Employer, committed to diversity, and encourages applications from minorities and under-represented groups. Thanks, Kevin Dr. Kevin M. Walsh Ky nanoNET Director Samuel T. Fife Professor of Electrical and Computer Engineering Founding Director of the UofL Micro/Nanotechnology Center Fellow of the National Academy of Inventors 2210 South Brook St Shumaker Research Building, Room 234 Louisville, KY 40292 Office # (502) 852-0826 Fax # (502) 852-8128 http://kynanonet.org/ [Description: Capture for email signature] -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.jpg Type: image/jpeg Size: 14485 bytes Desc: image001.jpg URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: UofL 21st_Univ_faculty_ad_Final.pdf Type: application/pdf Size: 61446 bytes Desc: UofL 21st_Univ_faculty_ad_Final.pdf URL: From crraum at gmail.com Fri Nov 6 22:26:15 2015 From: crraum at gmail.com (Christopher Raum) Date: Fri, 6 Nov 2015 19:26:15 -0800 Subject: [labnetwork] Sapphire substrates: precision scribe & break In-Reply-To: References: Message-ID: Hi Vito, I've had success scribing across the length of the desired cleave location and then using the length of a hex key (1 to 2 mm) to provide a fulcrum under the scribe line. Then by placing finger tips on either side of the scribe (freshly trimmed fingernails help), push down evenly over the hex key edge. By placing a gentle but steadily increasing pressure I've been able to successfully cleave fused quartz wafers (100 to 500 um thick) this way. This technique is heavily operator dependent and not suitable for large volume, but if you just need some experimental samples prepared it's a useful technique. Good luck! -Chris -- Christopher Raum, PhD. R&D Engineer Experimental Cosmology Group Radio Astronomy Lab University of California, Berkeley 151 LeConte Hall Berkeley, CA, 94720 Work: (510) 642-7801 Cell: (949) 677-1905 Fax: (510) 643-5204 Email: craum at berkeley.edu Alt Email: crraum at gmail.com On Fri, Nov 6, 2015 at 10:42 AM, Vito Logiudice wrote: > Dear Colleagues, > > I would appreciate hearing from anyone whom might be able to share some > insights on how to reliably scribe & break sapphire substrates. We?re > attempting to help out a couple of research groups here with such a > requirement. > > We?ve had success with our water-cooled dicing saw but it appears this > approach leads to unacceptable materials issues. We thus find ourselves > having to resort to some sort of precision (& repeatable) scribe and break > technique/setup which will result in consistently smooth sidewalls. > > Thank you for any insights on procedures you may be using or equipment > vendors you have worked with whom might be able to help. > > Best regards, > Vito > -- > Vito Logiudice P.Eng. > Director of Operations, Quantum NanoFab > University of Waterloo > Lazaridis QNC 1207 > 200 University Avenue West > Waterloo, ON Canada N2L 3G1 > Tel.: (519) 888-4567 ext. 38703 > Email: vito.logiudice at uwaterloo.ca > Website: https://fab.qnc.uwaterloo.ca > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From espen.rogstad at ntnu.no Sat Nov 7 12:16:55 2015 From: espen.rogstad at ntnu.no (Espen Rogstad) Date: Sat, 7 Nov 2015 17:16:55 +0000 Subject: [labnetwork] Sapphire substrates: precision scribe & break In-Reply-To: References: , Message-ID: <34771ACF-F9AD-4E86-9C9F-5CEA898370AA@ntnu.no> Hi Vito, A couple of years ago we scribed and cleaved a few 2" sapphire wafers that were around 300um thick. This was done with a dynatex II scribe & break machine that I guess is around 15 years old. Had to use quite high scribing and breaking force (I can check numbers if interested) but it worked fine. The diamond scribe tool would probably not last very long but since we only scribed a few wafers we didn't have any issues with that. Also, never checked sidewalls so don't know if they were smooth or not... Hope this helps anyway! Regards, Espen Rogstad Senior Engineer NTNU NanoLab ------------------------- Sem Saelands vei 14, K1-113 NO-7491 Trondheim, Norway Tlf: +47 95285642 http://www.ntnu.no/nanolab Den 7. nov. 2015 kl. 15.17 skrev Christopher Raum >: Hi Vito, I've had success scribing across the length of the desired cleave location and then using the length of a hex key (1 to 2 mm) to provide a fulcrum under the scribe line. Then by placing finger tips on either side of the scribe (freshly trimmed fingernails help), push down evenly over the hex key edge. By placing a gentle but steadily increasing pressure I've been able to successfully cleave fused quartz wafers (100 to 500 um thick) this way. This technique is heavily operator dependent and not suitable for large volume, but if you just need some experimental samples prepared it's a useful technique. Good luck! -Chris -- Christopher Raum, PhD. R&D Engineer Experimental Cosmology Group Radio Astronomy Lab University of California, Berkeley 151 LeConte Hall Berkeley, CA, 94720 Work: (510) 642-7801 Cell: (949) 677-1905 Fax: (510) 643-5204 Email: craum at berkeley.edu Alt Email: crraum at gmail.com On Fri, Nov 6, 2015 at 10:42 AM, Vito Logiudice > wrote: Dear Colleagues, I would appreciate hearing from anyone whom might be able to share some insights on how to reliably scribe & break sapphire substrates. We're attempting to help out a couple of research groups here with such a requirement. We've had success with our water-cooled dicing saw but it appears this approach leads to unacceptable materials issues. We thus find ourselves having to resort to some sort of precision (& repeatable) scribe and break technique/setup which will result in consistently smooth sidewalls. Thank you for any insights on procedures you may be using or equipment vendors you have worked with whom might be able to help. Best regards, Vito -- Vito Logiudice P.Eng. Director of Operations, Quantum NanoFab University of Waterloo Lazaridis QNC 1207 200 University Avenue West Waterloo, ON Canada N2L 3G1 Tel.: (519) 888-4567 ext. 38703 Email: vito.logiudice at uwaterloo.ca Website: https://fab.qnc.uwaterloo.ca _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From fouad.karouta at anu.edu.au Sun Nov 8 18:06:15 2015 From: fouad.karouta at anu.edu.au (Fouad Karouta) Date: Sun, 8 Nov 2015 23:06:15 +0000 Subject: [labnetwork] Sapphire substrates: precision scribe & break In-Reply-To: <34771ACF-F9AD-4E86-9C9F-5CEA898370AA@ntnu.no> References: , <34771ACF-F9AD-4E86-9C9F-5CEA898370AA@ntnu.no> Message-ID: Dear Vito, I wonder what you mean with precision cleaving. We use to cleave GaN/sapphire using a classic diamond scribing tool. We do full line scribe and pass the diamond tool several time on the sapphire side. Then we flip the wafer upside down on a rubber mat (mouse pad) and place a SS 2mm diameter rod and we push on both sides of the rod and generally increasing the pressure till it breaks. We were not interested in the shape of the cleave but and I don't believe you can get a vertical smooth wall as the cleavage is not relying on a cleavage plan (which is not straightforward with sapphire). For precision cleaving I know Loomis industry in California developed a scriber tool for sapphire based on full line scribe followed by a roller (like Espen described) to break the wafer. Hope this helps, Fouad Karouta ********************************* Manager ANFF ACT Node Australian National Fabrication Facility Research School of Physics and Engineering L. Huxley Building (#56), Mills Road, Room 4.02 Australian National University ACT 0200, Canberra, Australia Tel: + 61 2 6125 7174 Mob: + 61 451 046 412 Email: fouad.karouta at anu.edu.au http://anff-act.anu.edu.au/ From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Espen Rogstad Sent: Sunday, November 8, 2015 4:17 AM To: Vito Logiudice Cc: labnetwork at mtl.mit.edu Subject: Re: [labnetwork] Sapphire substrates: precision scribe & break Hi Vito, A couple of years ago we scribed and cleaved a few 2" sapphire wafers that were around 300um thick. This was done with a dynatex II scribe & break machine that I guess is around 15 years old. Had to use quite high scribing and breaking force (I can check numbers if interested) but it worked fine. The diamond scribe tool would probably not last very long but since we only scribed a few wafers we didn't have any issues with that. Also, never checked sidewalls so don't know if they were smooth or not... Hope this helps anyway! Regards, Espen Rogstad Senior Engineer NTNU NanoLab ------------------------- Sem S?lands vei 14, K1-113 NO-7491 Trondheim, Norway Tlf: +47 95285642 http://www.ntnu.no/nanolab Den 7. nov. 2015 kl. 15.17 skrev Christopher Raum >: Hi Vito, I've had success scribing across the length of the desired cleave location and then using the length of a hex key (1 to 2 mm) to provide a fulcrum under the scribe line. Then by placing finger tips on either side of the scribe (freshly trimmed fingernails help), push down evenly over the hex key edge. By placing a gentle but steadily increasing pressure I've been able to successfully cleave fused quartz wafers (100 to 500 um thick) this way. This technique is heavily operator dependent and not suitable for large volume, but if you just need some experimental samples prepared it's a useful technique. Good luck! -Chris -- Christopher Raum, PhD. R&D Engineer Experimental Cosmology Group Radio Astronomy Lab University of California, Berkeley 151 LeConte Hall Berkeley, CA, 94720 Work: (510) 642-7801 Cell: (949) 677-1905 Fax: (510) 643-5204 Email: craum at berkeley.edu Alt Email: crraum at gmail.com On Fri, Nov 6, 2015 at 10:42 AM, Vito Logiudice > wrote: Dear Colleagues, I would appreciate hearing from anyone whom might be able to share some insights on how to reliably scribe & break sapphire substrates. We're attempting to help out a couple of research groups here with such a requirement. We've had success with our water-cooled dicing saw but it appears this approach leads to unacceptable materials issues. We thus find ourselves having to resort to some sort of precision (& repeatable) scribe and break technique/setup which will result in consistently smooth sidewalls. Thank you for any insights on procedures you may be using or equipment vendors you have worked with whom might be able to help. Best regards, Vito -- Vito Logiudice P.Eng. Director of Operations, Quantum NanoFab University of Waterloo Lazaridis QNC 1207 200 University Avenue West Waterloo, ON Canada N2L 3G1 Tel.: (519) 888-4567 ext. 38703 Email: vito.logiudice at uwaterloo.ca Website: https://fab.qnc.uwaterloo.ca _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From efrat.moyal at latticegear.com Sun Nov 8 20:16:21 2015 From: efrat.moyal at latticegear.com (Efrat Moyal) Date: Mon, 9 Nov 2015 01:16:21 +0000 Subject: [labnetwork] Sapphire substrates: precision scribe & break In-Reply-To: References: Message-ID: Dear Chris, Id like to interest you with another, new cleaving option ? the FlipScribe - https://latticegear.com/flipscribe-100/ . I think it will be of an interest to you especial because of your last sentence: ?..This technique is heavily operator dependent and not suitable for large volume?? [cid:image004.png at 01D11A49.1E463F30] The FlipScribe allows one to view the target (under magnification even better), align the diamond tip to the target and scribe a fine, straight, very narrow line on the back of the sample. This way, the front is untouched while scribing and cleaving accurately. Cleaving is done over the same diamond pin on the surface of the FlipScribe, see the following short video clips: https://www.youtube.com/watch?v=zZ80NEpLVJc and https://www.youtube.com/watch?v=dQg5Yz9eBAE Best Regards, Efrat -------------------------------------------------------- Efrat R Moyal (Mrs.) DIRECT: 408.455.0475 Efrat.Moyal at LatticeGear.com [cid:image005.jpg at 01D11A49.1E463F30] Information contained in this electronic message is confidential. If you have received this communication in error, please notify LatticeGear LLC.info.latticegear.com immediately, and purge this message without copying or distributing. ************************************************** Begin forwarded message: From: Christopher Raum > Date: November 6, 2015 at 10:26:15 PM EST To: Vito Logiudice > Cc: "labnetwork at mtl.mit.edu" > Subject: Re: [labnetwork] Sapphire substrates: precision scribe & break Hi Vito, I've had success scribing across the length of the desired cleave location and then using the length of a hex key (1 to 2 mm) to provide a fulcrum under the scribe line. Then by placing finger tips on either side of the scribe (freshly trimmed fingernails help), push down evenly over the hex key edge. By placing a gentle but steadily increasing pressure I've been able to successfully cleave fused quartz wafers (100 to 500 um thick) this way. This technique is heavily operator dependent and not suitable for large volume, but if you just need some experimental samples prepared it's a useful technique. Good luck! -Chris -- Christopher Raum, PhD. R&D Engineer Experimental Cosmology Group Radio Astronomy Lab University of California, Berkeley 151 LeConte Hall Berkeley, CA, 94720 Work: (510) 642-7801 Cell: (949) 677-1905 Fax: (510) 643-5204 Email: craum at berkeley.edu Alt Email: crraum at gmail.com On Fri, Nov 6, 2015 at 10:42 AM, Vito Logiudice > wrote: Dear Colleagues, I would appreciate hearing from anyone whom might be able to share some insights on how to reliably scribe & break sapphire substrates. We?re attempting to help out a couple of research groups here with such a requirement. We?ve had success with our water-cooled dicing saw but it appears this approach leads to unacceptable materials issues. We thus find ourselves having to resort to some sort of precision (& repeatable) scribe and break technique/setup which will result in consistently smooth sidewalls. Thank you for any insights on procedures you may be using or equipment vendors you have worked with whom might be able to help. Best regards, Vito -- Vito Logiudice P.Eng. Director of Operations, Quantum NanoFab University of Waterloo Lazaridis QNC 1207 200 University Avenue West Waterloo, ON Canada N2L 3G1 Tel.: (519) 888-4567 ext. 38703 Email: vito.logiudice at uwaterloo.ca Website: https://fab.qnc.uwaterloo.ca _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image004.png Type: image/png Size: 272682 bytes Desc: image004.png URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image005.jpg Type: image/jpeg Size: 5818 bytes Desc: image005.jpg URL: From kevin.walsh at louisville.edu Tue Nov 10 19:06:50 2015 From: kevin.walsh at louisville.edu (kevin.walsh at louisville.edu) Date: Wed, 11 Nov 2015 00:06:50 +0000 Subject: [labnetwork] 2 open positions at UofL Message-ID: <0D1ABD6DF2541B42A05BD6E6D36954110141A790BC@exmbx18> I am pleased to announce 2 open faculty positions at the University of Louisville in the research thrust areas of Advanced Manufacturing and/or Sustainability. These are interdisciplinary research areas and the successful candidate will be comfortably placed in their most appropriate engineering academic department. The University of Louisville just became part of the NSF next generation NNIN, which is called the NNCI (National Nanotechnology Coordinated Infrastructure). Our site's theme is advanced multi-scale manufacturing, consistent with this search. I encourage candidates to consider this opportunity in the fine City of Louisville. Two Positions in Advanced Manufacturing and Sustainability at J.B. Speed School of Engineering, University of Louisville J.B. Speed School of Engineering invites applications from exceptional candidates with proven track record to strengthen the 21st century university research initiatives in advanced manufacturing and sustainability. The positions are expected at a rank of associate professor and will be housed in the appropriate discipline based on the candidate's educational qualifications and research interests. The following list of topics represent our preference but are not exclusive in nature. Advanced Manufacturing: Additive manufacturing and 3D printing; digital manufacturing and digital design; multi-scale manufacturing and integration; novel high throughput, low cost processes such as roll-to-roll, inkjet printing and micro-embossing, next generation micro and nano fabrication; smart materials for advanced manufacturing; bio-integrated and bio-compatible manufacturing. Sustainability: Renewable energy (solar, biomass, energy storage, advanced energy materials), energy efficiency (lighting and catalysis), nitrogen/phosphorous cycles, accelerated materials discovery, and advanced application and design. The chosen faculty candidates are expected to leverage resources and facilities available at our existing centers of excellence including Conn Center for Renewable Energy Research, and the Micro/NanoTechnology Center (www.louisville.edu/micronano), Additive Manufacturing Research Center. The candidates must have an earned Ph.D degree in an engineering discipline, and outstanding records of scientific research, doctoral student mentoring, and continuous research funding. The successful candidates will develop an imaginative research program that is both transformational and translational in nature and contribute to both undergraduate and graduate teaching. Applicants should apply online for Job ID 463 at (https://highereddecisions.com/uofl/current_vacancies.asp). The letter of application should indicate their qualifications, a current curriculum vitae, a short description of research and teaching plans along with a contact list of three or more references. Applications will be reviewed beginning December 1st, 2015 and applications will be received until the positions are filled. The expected start date is August 15, 2016. The University of Louisville is a state-supported metropolitan research university located in Kentucky's largest urban area. The J.B. Speed School of Engineering is located in the 177 acre Belknap campus. Louisville has world-class performing arts, great sports, a nationally acclaimed parks system and is home to the Kentucky Derby. It was named one of America's Breakout Cities for 2014 by CNN Money, the top travel destination for 2013 by Lonely Planet and the Most Livable City in America (large city category) in 2012 by the U.S. Conference of Mayors. The University of Louisville is an Affirmative Action, Equal Opportunity, Americans with Disabilities Employer, committed to diversity, and encourages applications from minorities and under-represented groups. Thanks, Kevin Walsh Dr. Kevin M. Walsh Ky nanoNET Director Samuel T. Fife Professor of Electrical and Computer Engineering Founding Director of the UofL Micro/Nanotechnology Center Fellow of the National Academy of Inventors 2210 South Brook St Shumaker Research Building, Room 234 Louisville, KY 40292 Office # (502) 852-0826 Fax # (502) 852-8128 http://kynanonet.org/ [Description: Capture for email signature] -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.jpg Type: image/jpeg Size: 14485 bytes Desc: image001.jpg URL: From lewin at illinois.edu Wed Nov 11 16:46:15 2015 From: lewin at illinois.edu (Reinhart, Leslie Lewin) Date: Wed, 11 Nov 2015 21:46:15 +0000 Subject: [labnetwork] University of Illinois - Managing Director - Micro and Nanotechnology Lab Message-ID: <0B48381248D4954CBEE4C4CC8FD100BD6E70442F@chimbx3.ad.uillinois.edu> The Micro and Nanotechnology Laboratory at the University of Illinois at Urbana-Champaign seeks applicants for a Managing Director to support the Director of the Micro and Nanotechnology Laboratory in an effort to assist with the day-to-day functioning of the Laboratory. For more information regarding this position, or to apply, please visit MNTL Managing Director. -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: University of Illinois - Managing Director - Micro and Nanotechnology Lab.pdf Type: application/pdf Size: 104092 bytes Desc: University of Illinois - Managing Director - Micro and Nanotechnology Lab.pdf URL: From christopher.joseph at kaust.edu.sa Thu Nov 12 02:55:27 2015 From: christopher.joseph at kaust.edu.sa (Christopher W. Joseph) Date: Thu, 12 Nov 2015 07:55:27 +0000 Subject: [labnetwork] The Advanced Nanofabrication and Thin Film Core Lab, Director Message-ID: <475838CEE978D34CA9A45E1B4C6E4F68AC602F@WTHEMXND05.KAUST.EDU.SA> Dear Colleagues, Just to introduce myself, I am a HR Consultant working at KAUST (King Abdullah University of Science and Technology). KAUST is an international graduate-level, merit-based research university dedicated to advancing science and technology through innovative and collaborative research and addressing challenges of regional and global significance. Based near Jeddah, Saudi Arabia, KAUST has attracted outstanding faculty and staff from all over the world, with strong representation from the USA, Germany, China, the UK, Australia, Japan, and Italy. This high diversity is also reflected by the student body, with more than 80 nations represented on campus. I am currently recruiting for a Nanofabrication's Director who will have responsibility for managing our Nanofab Clean room etc. The Nanofabrication and Thin Film Core Lab is positioned to facilitate and support KAUST research and education in the fields of microelectronics, electronic materials, MEMS, and biomedical and optical devices at micro and nano scales. The Core Lab's Nanofabrication facility provides a 2000 square meters of Class 100 and Class 1000 cleanroom environment for high yield device fabrication. It houses a wide spectrum of cleanroom processing equipment, covering lithography (stepper and ebeam writer), mask writing, dry and wet etch, thin film deposition, thermal processing, CMP, packaging and electrical characterization. The Thin Film Lab is a thin-film-growing facility for fundamental and application research in film deposition, thin film physical and chemical properties, and thin-film-related devices. It houses not only advanced thin film deposition capabilities, such as PLD, sputtering systems, atomic layer deposition, and electron beam deposition, but also advanced thin film physical and chemical property characterization instrumentation, such as physical property measurement system (PPMS), SQUID-VSM, RBS and atom probe. Major Responsibilities * Provide leadership and management to a team of scientists, engineers and technical staff at the Core Lab who provide research and education support and service to the research community at and beyond KAUST * Conduct strategic planning to ensure that the facility at the Core Lab is at cutting-edge and is able to meet the research and education needs at KAUST and contribute to high impact research at KAUST. * Ensure that equipment and facilities in the Lab are well maintained, available and operational as research tools to the highest degree possible * Ensure safe operation of all equipment at all times * Initiate and work with the Team Leads on the continuous improvement plan of the lab staff to ensure they are competent in their respective technical areas and are able to make value-added contribution to KAUST research and teaching. * Ensure the training plan meets the need of KAUST research and education. * Ensure the Core Lab is able to provide professional service to KAUST strategic partners and industrial collaborators. * Conduct effective performance management of research and technical staff, including objective setting and performance evaluation. * Work with User Committee to ensure effective communications between Core Lab staff and user community * Provide financial oversight in budget management, reviews, and reporting, and ensure the Lab is running based on the planned budget. * Develop policies and procedures specific to the Core Lab * Ensure compliance with applicable regulations and international best practices Competencies * Experience in leadership and management of a research team and administration of research facilities. * Excellent interpersonal skills and ability to build and motivate a team as well as communicate with upper management. * Good knowledge in overall cleanroom operation and running, preferably with strong process integration knowledge and in-depth knowledge of certain process modules. * Good knowledge in toxic gas management (TGM) system, laboratory control system (LCS) and clean room protocol execution. * Knowledge of the working principle of advanced characterization instruments such as physical properties measurement system (PPMS), magnetic properties measurement system (MPMS-SQUID), Rutherford backscattering spectrometry (RBS), magneto-optic Kerr effect (MOKE) etc. * Ability to catch up with the latest technical development in the area of nano-scale science and technology, advanced materials deposition techniques, advanced characterization instrumentation and techniques. Able to assess its relevance to KAUST research and make new instrumentation plan to facilitate KAUST research. * Ability to maintain and develop high-end facilities, and to sustain responsive services to the research community. * Ability to work with equipment vendors and build up win-win work relationship to ensure high equipment uptime. * Ability to initiate and develop collaborative projects with Lab users. Qualifications A PhD in science or engineering, at least 10 years of significant accomplishment in research or development, and extensive experience in leading a research team and managing research facilities. If this is of interest, or you may know someone who may be interested then please do get in touch. My email address is Christopher.joseph at kaust.edu.sa. Regards, Chris Christopher Joseph Senior Recruitment Specialist, Human Resources King Abdullah University of Science and Technology Administration Building 16 Level 2, Office 2516 Thuwal 23955-6900 Kingdom of Saudi Arabia Office: +966 12 808 3276 Email: christopher.joseph at kaust.edu.sa Website: www.kaust.edu.sa [Description: Description: Description: Description: Description: cid:image002.png at 01CB9559.17917DF0] The weekend in Saudi Arabia is Friday and Saturday ________________________________ This message and its contents including attachments are intended solely for the original recipient. If you are not the intended recipient or have received this message in error, please notify me immediately and delete this message from your computer system. Any unauthorized use or distribution is prohibited. Please consider the environment before printing this email. -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.png Type: image/png Size: 14148 bytes Desc: image001.png URL: From J.D.Watson at tudelft.nl Tue Nov 17 12:46:36 2015 From: J.D.Watson at tudelft.nl (John Watson - TNW) Date: Tue, 17 Nov 2015 17:46:36 +0000 Subject: [labnetwork] pmma cracking issue Message-ID: <5033ABE112FA6B49ABEC13F5C6FCB14CF9CB4C@SRV366.tudelft.net> Dear colleagues, Our group has been having a troublesome and seemingly random problem with pmma cracking during metalization steps, and I am hoping to get the community's ideas on what might be causing the problem. Our typical process (used to make ohmic contacts to III-V nanowire devices on Si/SiO2 substrates) is as follows: PMMA 950K A4 spun at 4000 RPM (~200nm thickness) Bake 175C 10 min Expose 1100-1300 uC/cm^2 at 100kV Develop 60s MIBK:IPA I:3, rinse in IPA 30s 60s O2 ashing (sample sits in Faraday cage, pmma etch rate ~1-3 nm/min) Ammonium polysulfide passivation of III-V surface (sample sits in heavily diluted, super-saturated polysulfide solution at 60C for 30 min) Quick load into evaporator followed by short in-situ He ion milling to remove residual sulfur layer Evaporation of 10/120nm Cr/Au at 0.5/1.5 A/s. Vacuum level typically high 10^-8 Torr throughout deposition Liftoff in acetone ~50C The problem that we see is illustrated in the attached SEM image - thin filaments of metal extend from the contacts (typically starting at sharp corners) and short out devices. The fact that the cracks originate at sharp corners suggests the issue is stress-related, but we have been unable to track down the cause of this excess stress. Many users (8-10) have seen this problem using different bottles of resist, different viscosities and molecular weights of pmma, different baking times and temperatures (as short/cold as 5 min/150C and as hot/long as 190C/30min), different hotplates, 3 different e-beam lithography systems, a number of substrates/gate dielectrics (SiO2, SiNx, BN, InSb, sapphire), different metalization systems (two different e-beam evaporators and one sputtering system - the helium etch is only done in one evaporator), different metalizations (Ti/Au, Cr/Au, NbTiN), and varying waiting times between spinning/exposure/developing/metalization (varying from 5 hours to 3 days for the whole process). The process I described above had been stable for over a year until about a month ago when the cracking problem came up. Since then it has been sporadic, ruining a few (out of many) processing runs per week, but it has not been repeatable enough to allow for really systematic testing. Does anyone have any insight into what could increase stress in the resist? For instance, is temperature/humidity during spinning and baking particularly critical? One theory we are currently testing is that a recently instituted rule of cleaning the spinners with a metal-ion-free photoresist developer following pmgi spinning could be causing the problem (e.g. this would help explain the random nature of the problem since it would depend on what the previous user did with the spinner). Thanks, John ----------------- John Watson Postdoctoral Fellow - Kavli Institute of Nanoscience Delft University of Technology Lorentzweg 1, 2628 CJ Delft The Netherlands -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: resist cracking.jpg Type: image/jpeg Size: 43169 bytes Desc: resist cracking.jpg URL: From price.798 at osu.edu Tue Nov 17 16:20:33 2015 From: price.798 at osu.edu (Price, Aimee) Date: Tue, 17 Nov 2015 21:20:33 +0000 Subject: [labnetwork] pmma cracking issue In-Reply-To: <5033ABE112FA6B49ABEC13F5C6FCB14CF9CB4C@SRV366.tudelft.net> References: <5033ABE112FA6B49ABEC13F5C6FCB14CF9CB4C@SRV366.tudelft.net> Message-ID: <83583687862B8444A85296A4944147DF8BF93AF1@CIO-TNC-D2MBX03.osuad.osu.edu> Hi John, We had a "cracking" issue with PMMA in two different time frames and labs here at Ohio State. Many years ago the first problem was also sporadic and we did a similar analysis to your analysis below. We even sent some samples (and a student) to another university for spinning and/or ebeam lithography. In the end, it was found that certain areas of our evaporator were hotter than others. That problem was a gross problem however and was visible immediately after removal from the evaporator. The metal was Cr/Au. Do you have any images of the metal before the liftoff? You are welcome to email me directly if you wish. Our most recent instance was also a heating issue in a completely different, and much newer evaporator, but with Ni. In both cases they were temperature related. We solved them by either slowing down the deposition rate, so using lower power in the electron beam evaporator, or changing the soak times. Just looking at your process, I would also take a look at the actual temperature of your hotplate(s). We have several of one type and one attached to a coater. The one type has the thermocouple under the stage and the actual temperature varies as much as 10deg Celsius from the setpoint. Some of them also vary across the stage itself. The actual temperature may be an issue, since you want the resist to actually see 175C not 160C etc. Also, I'd take a look at the resist under SEM after all of the steps post develop if you have time/enough samples. If you are concerned about the spinner verify the exhaust has not and is not changing. We've had issues in the past with the exhaust changing and causing trouble with other resist systems. Best of luck to you. Regards, Aimee From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of John Watson - TNW Sent: Tuesday, November 17, 2015 12:47 PM To: labnetwork at mtl.mit.edu Cc: Jakob Kammhuber - TNW Subject: [labnetwork] pmma cracking issue Dear colleagues, Our group has been having a troublesome and seemingly random problem with pmma cracking during metalization steps, and I am hoping to get the community's ideas on what might be causing the problem. Our typical process (used to make ohmic contacts to III-V nanowire devices on Si/SiO2 substrates) is as follows: PMMA 950K A4 spun at 4000 RPM (~200nm thickness) Bake 175C 10 min Expose 1100-1300 uC/cm^2 at 100kV Develop 60s MIBK:IPA I:3, rinse in IPA 30s 60s O2 ashing (sample sits in Faraday cage, pmma etch rate ~1-3 nm/min) Ammonium polysulfide passivation of III-V surface (sample sits in heavily diluted, super-saturated polysulfide solution at 60C for 30 min) Quick load into evaporator followed by short in-situ He ion milling to remove residual sulfur layer Evaporation of 10/120nm Cr/Au at 0.5/1.5 A/s. Vacuum level typically high 10^-8 Torr throughout deposition Liftoff in acetone ~50C The problem that we see is illustrated in the attached SEM image - thin filaments of metal extend from the contacts (typically starting at sharp corners) and short out devices. The fact that the cracks originate at sharp corners suggests the issue is stress-related, but we have been unable to track down the cause of this excess stress. Many users (8-10) have seen this problem using different bottles of resist, different viscosities and molecular weights of pmma, different baking times and temperatures (as short/cold as 5 min/150C and as hot/long as 190C/30min), different hotplates, 3 different e-beam lithography systems, a number of substrates/gate dielectrics (SiO2, SiNx, BN, InSb, sapphire), different metalization systems (two different e-beam evaporators and one sputtering system - the helium etch is only done in one evaporator), different metalizations (Ti/Au, Cr/Au, NbTiN), and varying waiting times between spinning/exposure/developing/metalization (varying from 5 hours to 3 days for the whole process). The process I described above had been stable for over a year until about a month ago when the cracking problem came up. Since then it has been sporadic, ruining a few (out of many) processing runs per week, but it has not been repeatable enough to allow for really systematic testing. Does anyone have any insight into what could increase stress in the resist? For instance, is temperature/humidity during spinning and baking particularly critical? One theory we are currently testing is that a recently instituted rule of cleaning the spinners with a metal-ion-free photoresist developer following pmgi spinning could be causing the problem (e.g. this would help explain the random nature of the problem since it would depend on what the previous user did with the spinner). Thanks, John ----------------- John Watson Postdoctoral Fellow - Kavli Institute of Nanoscience Delft University of Technology Lorentzweg 1, 2628 CJ Delft The Netherlands -------------- next part -------------- An HTML attachment was scrubbed... URL: From mondol at mit.edu Tue Nov 17 16:26:01 2015 From: mondol at mit.edu (Mark K Mondol) Date: Tue, 17 Nov 2015 16:26:01 -0500 Subject: [labnetwork] pmma cracking issue In-Reply-To: <5033ABE112FA6B49ABEC13F5C6FCB14CF9CB4C@SRV366.tudelft.net> References: <5033ABE112FA6B49ABEC13F5C6FCB14CF9CB4C@SRV366.tudelft.net> Message-ID: <564B9B69.6080808@mit.edu> John: Thanks for documenting the process so well. I am not sure that I would put this down to resist cracking, although it might be. My first thought was a metal evaporation issue, but you say it happens with different evaporators and sputtering systems (impressive to liftoff what look to be 100nm lines with a sputtering system putting down the metal). Stress in the metal seems more likely than stress in the resist. Almost any hotplate bake >160C should relieve stress in the PMMA. My second thought, uniformed by any real knowledge of chemistry, is that your Ammonium polysulfide is too base. In my experience base solutions attack PMMA and ruin it as a resist. The other, obvious, culprit is the He Ion Milling as it is common to all your failures; though I can't think of a particular mechanism that would create this fault. In many years of ebeam lithography I have never found PMMA resist to be the problem (i.e. it is extraordinarily stable) other than when it was inadvertently exposed to x-rays. So I would not be looking at the initial resist. Baking PMMA is also a very tolerant procedure. On the other hand your resist profiles must be suffering, to some extent, by the exposure to heat (plasma ash and possibly He ion milling and possibly by the metalization. The doses you mention and development times and developer all seem very reasonable. Have any users examined the exposed and developed PMMA prior to metalization? I think that would be my first step. Regards, Mark K Mondol -- Mark K Mondol Assistant Director NanoStructures Laboratory And Facility Manager Scanning Electron Beam Lithography Facility Bldg 38 Room 177 www.rle.mit.edu/sebl mondol at mit.edu office - 617-253-9617 cell - 617-224-8756 From michael.rooks at yale.edu Tue Nov 17 16:24:19 2015 From: michael.rooks at yale.edu (Michael Rooks) Date: Tue, 17 Nov 2015 16:24:19 -0500 Subject: [labnetwork] pmma cracking issue In-Reply-To: <5033ABE112FA6B49ABEC13F5C6FCB14CF9CB4C@SRV366.tudelft.net> References: <5033ABE112FA6B49ABEC13F5C6FCB14CF9CB4C@SRV366.tudelft.net> Message-ID: <564B9B03.1060001@yale.edu> I have seen PMMA form stress cracks like this, but not in 200nm thick films. It usually happens with > 1 um thick films developed in MIBK/IPA, since MIBK swells the resist film. A simple solution is to develop in IPA/water (3:1), preferably at a low temperature (we use 7C). You can find a paper about IPA/water development here. This is just a guess, but maybe the pmma is a lot thicker than you think. (Also, I suggest using hot NMP instead of hot acetone. It's a lot safer.) -------------------------------- Michael Rooks Yale Institute of Nanoscience and Quantum Engineering nano.yale.edu On 11/17/2015 12:46 PM, John Watson - TNW wrote: > > Dear colleagues, > > Our group has been having a troublesome and seemingly random problem > with pmma cracking during metalization steps, and I am hoping to get > the community?s ideas on what might be causing the problem. Our > typical process (used to make ohmic contacts to III-V nanowire devices > on Si/SiO2 substrates) is as follows: > > PMMA 950K A4 spun at 4000 RPM (~200nm thickness) > > Bake 175C 10 min > > Expose 1100-1300 uC/cm^2 at 100kV > > Develop 60s MIBK:IPA I:3, rinse in IPA 30s > > 60s O2 ashing (sample sits in Faraday cage, pmma etch rate ~1-3 nm/min) > > Ammonium polysulfide passivation of III-V surface (sample sits in > heavily diluted, super-saturated polysulfide solution at 60C for 30 min) > > Quick load into evaporator followed by short in-situ He ion milling to > remove residual sulfur layer > > Evaporation of 10/120nm Cr/Au at 0.5/1.5 A/s. Vacuum level typically > high 10^-8 Torr throughout deposition > > Liftoff in acetone ~50C > > The problem that we see is illustrated in the attached SEM image ? > thin filaments of metal extend from the contacts (typically starting > at sharp corners) and short out devices. The fact that the cracks > originate at sharp corners suggests the issue is stress-related, but > we have been unable to track down the cause of this excess stress. > Many users (8-10) have seen this problem using different bottles of > resist, different viscosities and molecular weights of pmma, different > baking times and temperatures (as short/cold as 5 min/150C and as > hot/long as 190C/30min), different hotplates, 3 different e-beam > lithography systems, a number of substrates/gate dielectrics (SiO2, > SiNx, BN, InSb, sapphire), different metalization systems (two > different e-beam evaporators and one sputtering system ? the helium > etch is only done in one evaporator), different metalizations (Ti/Au, > Cr/Au, NbTiN), and varying waiting times between > spinning/exposure/developing/metalization (varying from 5 hours to 3 > days for the whole process). The process I described above had been > stable for over a year until about a month ago when the cracking > problem came up. Since then it has been sporadic, ruining a few (out > of many) processing runs per week, but it has not been repeatable > enough to allow for really systematic testing. > > Does anyone have any insight into what could increase stress in the > resist? For instance, is temperature/humidity during spinning and > baking particularly critical? One theory we are currently testing is > that a recently instituted rule of cleaning the spinners with a > metal-ion-free photoresist developer following pmgi spinning could be > causing the problem (e.g. this would help explain the random nature of > the problem since it would depend on what the previous user did with > the spinner). Thanks, > > John > > ----------------- > John Watson > Postdoctoral Fellow - Kavli Institute of Nanoscience > Delft University of Technology > Lorentzweg 1, 2628 CJ Delft > The Netherlands > > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://urldefense.proofpoint.com/v2/url?u=https-3A__www-2Dmtl.mit.edu_mailman_listinfo.cgi_labnetwork&d=AwICAg&c=-dg2m7zWuuDZ0MUcV7Sdqw&r=apnDUg1OD9ejswcjrIvVgS28NpQ7-FGy7Sl7_YPlupc&m=k00J_xGJbn6kSnBRzd-5iCwCVl8AjkSQ0Xp0-3Nqud0&s=CSD8dbI60PxdOmtcMQVPTZIv38xyKb-TkNiqaGIRpYw&e= -------------- next part -------------- An HTML attachment was scrubbed... URL: From espen.rogstad at ntnu.no Tue Nov 17 16:50:21 2015 From: espen.rogstad at ntnu.no (Espen Rogstad) Date: Tue, 17 Nov 2015 21:50:21 +0000 Subject: [labnetwork] pmma cracking issue In-Reply-To: <5033ABE112FA6B49ABEC13F5C6FCB14CF9CB4C@SRV366.tudelft.net> References: <5033ABE112FA6B49ABEC13F5C6FCB14CF9CB4C@SRV366.tudelft.net> Message-ID: Hi John, We've also had issues with cracking and even bubbling of pmma during metallization. The problem was most severe for Pt deposition. We haven't gotten totally rid of the problem but the following helped in limiting it: - Increasing the deposition rate from 5?/s normally used to ~10?/s. - Increasing the source-sample distance. We have around 40cm distance in one of our e-beams and it mostly works fine. - Attaching samples to a 1cm thick aluminum disc (will act as a heat sink) using Mung II vacuum grease (we normally attach samples to a 4" Si wafer using kapton tape). - Putting the source material directly in the Cu pocket without using a crucible liner This does not explain why you suddenly see this problem though. Maybe your process cooling water pressure has changed? If you use a carbon liner for gold you normally get a crust of carbon on top which will deflect a lot of electrons which in turn will expose the pmma during metallization. We use tungsten liners (with a small tungsten disc under to minimize contact with Cu pocket) for gold and it works very well. Anyway, as I said we still see this problem occasionally and are very interested in what others have to say about this. Thanks for raising the question John! Regards, Espen Rogstad NTNU NanoLab ------------------------- Sem Saelands vei 14, K1-113 NO-7491 Trondheim, Norway Tlf: +47 95285642 http://www.ntnu.no/nanolab Den 17. nov. 2015 kl. 21.56 skrev John Watson - TNW >: Dear colleagues, Our group has been having a troublesome and seemingly random problem with pmma cracking during metalization steps, and I am hoping to get the community's ideas on what might be causing the problem. Our typical process (used to make ohmic contacts to III-V nanowire devices on Si/SiO2 substrates) is as follows: PMMA 950K A4 spun at 4000 RPM (~200nm thickness) Bake 175C 10 min Expose 1100-1300 uC/cm^2 at 100kV Develop 60s MIBK:IPA I:3, rinse in IPA 30s 60s O2 ashing (sample sits in Faraday cage, pmma etch rate ~1-3 nm/min) Ammonium polysulfide passivation of III-V surface (sample sits in heavily diluted, super-saturated polysulfide solution at 60C for 30 min) Quick load into evaporator followed by short in-situ He ion milling to remove residual sulfur layer Evaporation of 10/120nm Cr/Au at 0.5/1.5 A/s. Vacuum level typically high 10^-8 Torr throughout deposition Liftoff in acetone ~50C The problem that we see is illustrated in the attached SEM image - thin filaments of metal extend from the contacts (typically starting at sharp corners) and short out devices. The fact that the cracks originate at sharp corners suggests the issue is stress-related, but we have been unable to track down the cause of this excess stress. Many users (8-10) have seen this problem using different bottles of resist, different viscosities and molecular weights of pmma, different baking times and temperatures (as short/cold as 5 min/150C and as hot/long as 190C/30min), different hotplates, 3 different e-beam lithography systems, a number of substrates/gate dielectrics (SiO2, SiNx, BN, InSb, sapphire), different metalization systems (two different e-beam evaporators and one sputtering system - the helium etch is only done in one evaporator), different metalizations (Ti/Au, Cr/Au, NbTiN), and varying waiting times between spinning/exposure/developing/metalization (varying from 5 hours to 3 days for the whole process). The process I described above had been stable for over a year until about a month ago when the cracking problem came up. Since then it has been sporadic, ruining a few (out of many) processing runs per week, but it has not been repeatable enough to allow for really systematic testing. Does anyone have any insight into what could increase stress in the resist? For instance, is temperature/humidity during spinning and baking particularly critical? One theory we are currently testing is that a recently instituted rule of cleaning the spinners with a metal-ion-free photoresist developer following pmgi spinning could be causing the problem (e.g. this would help explain the random nature of the problem since it would depend on what the previous user did with the spinner). Thanks, John ----------------- John Watson Postdoctoral Fellow - Kavli Institute of Nanoscience Delft University of Technology Lorentzweg 1, 2628 CJ Delft The Netherlands _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From IRHarvey at eng.utah.edu Tue Nov 17 17:05:07 2015 From: IRHarvey at eng.utah.edu (Ian Harvey) Date: Tue, 17 Nov 2015 15:05:07 -0700 Subject: [labnetwork] UGIM '16 (Salt Lake City) First Call for Registration Message-ID: <4EB882A6-8CF4-4E00-9E8A-E36FB214F877@eng.utah.edu> Dear colleagues and prospective UGIM sponsors, UGIM '16 registration is now open. See attached announcement and also link to our website: http://ugim.nanofab.utah.edu/ The travel tab will convey the simplicity of getting in to SLC International Airport. Also easy door-to-door by light rail from the airport to our guest house and to our hosting facility, the Utah Nanofab. See you in June! ?Ian ******************************************** Ian R. Harvey, Ph.D. Associate Director Utah Nanofab Cleanroom Fabrication and Surface Analysis & nano-scale Imaging 801/585-6162 (voicemail) www.nanofab.utah.edu http://sal.nanofab.utah.edu Chair, UGIM '16 http://ugim.nanofab.utah.edu/ -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: PastedGraphic-2.pdf Type: application/pdf Size: 22517 bytes Desc: not available URL: -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: first call for registration_AV.compressed.pdf Type: application/pdf Size: 71945 bytes Desc: not available URL: -------------- next part -------------- An HTML attachment was scrubbed... URL: From roberto.panepucci at cti.gov.br Wed Nov 18 07:10:54 2015 From: roberto.panepucci at cti.gov.br (Roberto R. Panepucci) Date: Wed, 18 Nov 2015 10:10:54 -0200 (BRST) Subject: [labnetwork] pmma cracking issue In-Reply-To: <5033ABE112FA6B49ABEC13F5C6FCB14CF9CB4C@SRV366.tudelft.net> References: <5033ABE112FA6B49ABEC13F5C6FCB14CF9CB4C@SRV366.tudelft.net> Message-ID: <2029706422.1113271.1447848654199.JavaMail.zimbra@cti.gov.br> Dear John, In case you have discarded other options, have you considered if it is an issue in pattern generation? Layout conversion issue in boolean operation? If you are using a system with faulty or no blanking between patterns during exposure, unexpected beam traces could lead to this type of structure. What currents are you using? High beam currents would have to be used. Best regards, -- Roberto R. Panepucci, PhD Centro de Tecnologia da Informa??o Renato Archer - CTI Telefone: +55 19 3746-6072 ----- Em 17 de Nov de 2015, em 15:46, John Watson - TNW escreveu: Dear colleagues, Our group has been having a troublesome and seemingly random problem with pmma cracking during metalization steps, and I am hoping to get the community?s ideas on what might be causing the problem. Our typical process (used to make ohmic contacts to III-V nanowire devices on Si/SiO2 substrates) is as follows: PMMA 950K A4 spun at 4000 RPM (~200nm thickness) Bake 175C 10 min Expose 1100-1300 uC/cm^2 at 100kV Develop 60s MIBK:IPA I:3, rinse in IPA 30s 60s O2 ashing (sample sits in Faraday cage, pmma etch rate ~1-3 nm/min) Ammonium polysulfide passivation of III-V surface (sample sits in heavily diluted, super-saturated polysulfide solution at 60C for 30 min) Quick load into evaporator followed by short in-situ He ion milling to remove residual sulfur layer Evaporation of 10/120nm Cr/Au at 0.5/1.5 A/s. Vacuum level typically high 10^-8 Torr throughout deposition Liftoff in acetone ~50C The problem that we see is illustrated in the attached SEM image ? thin filaments of metal extend from the contacts (typically starting at sharp corners) and short out devices. The fact that the cracks originate at sharp corners suggests the issue is stress-related, but we have been unable to track down the cause of this excess stress. Many users (8-10) have seen this problem using different bottles of resist, different viscosities and molecular weights of pmma, different baking times and temperatures (as short/cold as 5 min/150C and as hot/long as 190C/30min), different hotplates, 3 different e-beam lithography systems, a number of substrates/gate dielectrics (SiO2, SiNx, BN, InSb, sapphire), different metalization systems (two different e-beam evaporators and one sputtering system ? the helium etch is only done in one evaporator), different metalizations (Ti/Au, Cr/Au, NbTiN), and varying waiting times between spinning/exposure/developing/metalization (varying from 5 hours to 3 days for the whole process). The process I described above had been stable for over a year until about a month ago when the cracking problem came up. Since then it has been sporadic, ruining a few (out of many) processing runs per week, but it has not been repeatable enough to allow for really systematic testing. Does anyone have any insight into what could increase stress in the resist? For instance, is temperature/humidity during spinning and baking particularly critical? One theory we are currently testing is that a recently instituted rule of cleaning the spinners with a metal-ion-free photoresist developer following pmgi spinning could be causing the problem (e.g. this would help explain the random nature of the problem since it would depend on what the previous user did with the spinner). Thanks, John ----------------- John Watson Postdoctoral Fellow - Kavli Institute of Nanoscience Delft University of Technology Lorentzweg 1, 2628 CJ Delft The Netherlands _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From J.D.Watson at tudelft.nl Wed Nov 18 07:38:00 2015 From: J.D.Watson at tudelft.nl (John Watson - TNW) Date: Wed, 18 Nov 2015 12:38:00 +0000 Subject: [labnetwork] pmma cracking issue In-Reply-To: <564B9B69.6080808@mit.edu> References: <5033ABE112FA6B49ABEC13F5C6FCB14CF9CB4C@SRV366.tudelft.net> <564B9B69.6080808@mit.edu> Message-ID: <5033ABE112FA6B49ABEC13F5C6FCB14CF9CD46@SRV366.tudelft.net> Hi all, Thank you all very much for all the responses; this gives us some good ideas of things to check into. In response to a few of the questions that were raised: 1) We have independently checked the hot plate temperatures, and they are a bit low (by ~15C), so we can try bumping the setpoints up a bit to compensate. 2) The polysulfide treatment is certainly the least standard part of our process, though it is very weak (diluted 200:1). We are planning on adding control samples without the polysulfide soak when we do our process runs to see how much difference this makes. 3) Heating during deposition/He etch. The samples are clipped to a 4" x 3/8" copper plate. After the deposition the copper is probably ~30-35C; I'm not sure if the resist surface could be hot enough to crack in this case, but we will start comparing the emission current from good and bad runs and check on the stability of the cooling water to the hearth. The gold crucible (graphite) glows bright orange during the deposition (so far I have not found any sweep parameters that can keep it cooler), so that probably doesn't help the situation. 4) State of resist at various stages of the process. We have inspected the resist after development and don't see any cracks. Most of the time we don't check the resist after the polysulfide since we want to avoid prolonged air exposure, but we will check more into this. Attached is an optical image of a bad chip before liftoff; given that the metal hasn't started to wrinkle I would guess the stress is not extremely high, but maybe it is high enough... 5) Stray exposure/faulty blanking. We have seen the cracks with devices patterned in three different e-beam systems (two Vistec, one Raith with the Raith using different file formats), so this along with the fact that we don't see the cracks after developing would seem to rule out extra exposure in the EBPG. Thank you all again, John -----Original Message----- From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Mark K Mondol Sent: Tuesday, November 17, 2015 10:26 PM To: labnetwork at mtl.mit.edu Subject: Re: [labnetwork] pmma cracking issue John: Thanks for documenting the process so well. I am not sure that I would put this down to resist cracking, although it might be. My first thought was a metal evaporation issue, but you say it happens with different evaporators and sputtering systems (impressive to liftoff what look to be 100nm lines with a sputtering system putting down the metal). Stress in the metal seems more likely than stress in the resist. Almost any hotplate bake >160C should relieve stress in the PMMA. My second thought, uniformed by any real knowledge of chemistry, is that your Ammonium polysulfide is too base. In my experience base solutions attack PMMA and ruin it as a resist. The other, obvious, culprit is the He Ion Milling as it is common to all your failures; though I can't think of a particular mechanism that would create this fault. In many years of ebeam lithography I have never found PMMA resist to be the problem (i.e. it is extraordinarily stable) other than when it was inadvertently exposed to x-rays. So I would not be looking at the initial resist. Baking PMMA is also a very tolerant procedure. On the other hand your resist profiles must be suffering, to some extent, by the exposure to heat (plasma ash and possibly He ion milling and possibly by the metalization. The doses you mention and development times and developer all seem very reasonable. Have any users examined the exposed and developed PMMA prior to metalization? I think that would be my first step. Regards, Mark K Mondol -- Mark K Mondol Assistant Director NanoStructures Laboratory And Facility Manager Scanning Electron Beam Lithography Facility Bldg 38 Room 177 www.rle.mit.edu/sebl mondol at mit.edu office - 617-253-9617 cell - 617-224-8756 _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- A non-text attachment was scrubbed... Name: before liftoff.jpg Type: image/jpeg Size: 157066 bytes Desc: before liftoff.jpg URL: From mondol at mit.edu Wed Nov 18 12:05:59 2015 From: mondol at mit.edu (Mark K Mondol) Date: Wed, 18 Nov 2015 12:05:59 -0500 Subject: [labnetwork] pmma cracking issue In-Reply-To: References: <5033ABE112FA6B49ABEC13F5C6FCB14CF9CB4C@SRV366.tudelft.net> Message-ID: <564CAFF7.7000002@mit.edu> I too wonder if heating during metallization is the issue. We normally do not "sweep" the beam during evaporation, we do this to reduce the spot size of the hot metal, which is important for small features. But I think this also means less total heat generation. I also evaporate metals at at least 1nm/sec. As the evaporation rate tends to be non-linear with power I think this decreases the heating of the substrate. An increased distance from source to substrate will also minimize heating of the substrate. Excess soak times may also generate excess heat at the substrate. The most important technique, which we use, to reduce heating is to have a "second" shutter very close to the substrate, this shields the substrate from heating during the ramp up and soak times. On the other hand I have no clue why this would suddenly become an issue for you. I suppose you could try a test of evaporating more Au, so heating the substrate more. Or evaporating Pt or W, which in my experience, requires much more heat. Or, conversely evaporating a thinner layer of Au to see if the cracking decreases. Regards, Mark K Mondol On 11/17/2015 4:50 PM, Espen Rogstad wrote: > Hi John, > We've also had issues with cracking and even bubbling of pmma during > metallization. The problem was most severe for Pt deposition. We > haven't gotten totally rid of the problem but the following helped in > limiting it: > - Increasing the deposition rate from 5?/s normally used to ~10?/s. > - Increasing the source-sample distance. We have around 40cm distance > in one of our e-beams and it mostly works fine. > - Attaching samples to a 1cm thick aluminum disc (will act as a heat > sink) using Mung II vacuum grease (we normally attach samples to a 4" > Si wafer using kapton tape). > - Putting the source material directly in the Cu pocket without using > a crucible liner -- Mark K Mondol Assistant Director NanoStructures Laboratory And Facility Manager Scanning Electron Beam Lithography Facility Bldg 38 Room 177 www.rle.mit.edu/sebl mondol at mit.edu office - 617-253-9617 cell - 617-224-8756 From lino.eugene at mcgill.ca Wed Nov 18 16:50:32 2015 From: lino.eugene at mcgill.ca (Lino Eugene, Dr) Date: Wed, 18 Nov 2015 21:50:32 +0000 Subject: [labnetwork] Thermocouple for JIPELEC JetFirst RTP system Message-ID: <7F3DC325FF6D6249B261422DED6D10514DD8AEAB@EXMBX2010-6.campus.MCGILL.CA> Dear colleagues, We have a JIPELEC JetFirst 200 rapid thermal processor. The spare thermocouples from the manufacturer are expensive and it seems that their lifetime is short. We are looking for a second source. We are thinking about replacing the damaged TC wire only. A bare wire TC can be purchased from Omega. Has anyone ever done that for their JetFirst system? Do you know thermocouple suppliers other than Omega? Thanks, _______________________________________________________________________________ Lino EUGENE, Ph.D., Jr. Eng. Research assistant McGill Nanotools - Microfab Mcgill University Rutherford Physics Building - Room 016 3600 University Street Montreal (Quebec) Canada H3A 2T8 Phone : 514 398 7329 Fax : 514 398 8434 E-mail : lino.eugene at mcgill.ca Website : www.mcgill.ca/microfab/ -------------- next part -------------- An HTML attachment was scrubbed... URL: From mwoonk at umich.edu Thu Nov 19 09:29:21 2015 From: mwoonk at umich.edu (Matthew Oonk) Date: Thu, 19 Nov 2015 09:29:21 -0500 Subject: [labnetwork] Thermocouple for JIPELEC JetFirst RTP system In-Reply-To: <7F3DC325FF6D6249B261422DED6D10514DD8AEAB@EXMBX2010-6.campus.MCGILL.CA> References: <7F3DC325FF6D6249B261422DED6D10514DD8AEAB@EXMBX2010-6.campus.MCGILL.CA> Message-ID: We had the same problem with out TCs on our Jetfirst 100 and 150. It's mainly due to the fact that we have users who run high temperature recipes using the TC (our users don't use the pyrometer due to different substrate coatings causing it to vary.) The problem with Omega is that the TC is a strange length and it's hard to have confidence in the calibration adjustments in the software. The Jupilec TCs are a somehow callibrated by the vendors - I think that is half the expense. The only hack I can suggest is from Axic - if you have a glass blower on campus and the break is at the tip of the TC (usually where it is since it fuses with the Si and snaps,) you can have them re-bonded in a hot torch. -Matt Matthew Oonk Research Engineer Lurie Nanofabrication Facility University of Michigan 734-646-1275 mwoonk at umich.edu On Wed, Nov 18, 2015 at 4:50 PM, Lino Eugene, Dr wrote: > Dear colleagues, > > > > We have a JIPELEC JetFirst 200 rapid thermal processor. > > > > The spare thermocouples from the manufacturer are expensive and it seems > that their lifetime is short. We are looking for a second source. We are > thinking about replacing the damaged TC wire only. A bare wire TC can be > purchased from Omega. > > > > Has anyone ever done that for their JetFirst system? Do you know > thermocouple suppliers other than Omega? > > > > Thanks, > > > *_______________________________________________________________________________* > > *Lino EUGENE, Ph.D., Jr. Eng.* > > Research assistant > > McGill Nanotools - Microfab > > > > Mcgill University > > Rutherford Physics Building - Room 016 > > 3600 University Street > > Montreal (Quebec) Canada > > H3A 2T8 > > > > Phone : 514 398 7329 > > Fax : 514 398 8434 > > E-mail : lino.eugene at mcgill.ca > > Website : www.mcgill.ca/microfab/ > > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From bcord at umn.edu Thu Nov 19 10:31:17 2015 From: bcord at umn.edu (bryan cord) Date: Thu, 19 Nov 2015 09:31:17 -0600 Subject: [labnetwork] pmma cracking issue In-Reply-To: <564CAFF7.7000002@mit.edu> References: <5033ABE112FA6B49ABEC13F5C6FCB14CF9CB4C@SRV366.tudelft.net> <564CAFF7.7000002@mit.edu> Message-ID: <564DEB45.4010802@umn.edu> Seconding Mark here. Cracking of PMMA during evaporation of high melting point metals (like Ta or W) has been a major issue for us, with final results that look similar to your "before liftoff" image. I actually had it randomly happen with gold once too, as metal had worked its way out of the crucible during previous runs and gotten between the crucible and the block, which increased thermal conductivity to the cooling block enough that it took a lot longer to heat the gold to melting point. In that case it was very obvious that something was wrong (the crucible didn't glow nearly as brightly as it would during a "good" run and the deposition rate vs. power was way off), but maybe something similar but less severe is happening? Comparing beam currents and total run times between the good and bad runs might be able to tell you if something similar is up. -bryan On 11/18/2015 11:05 AM, Mark K Mondol wrote: > I too wonder if heating during metallization is the issue. > > We normally do not "sweep" the beam during evaporation, we do this to > reduce the spot size of the hot metal, which is important for small > features. But I think this also means less total heat generation. I > also evaporate metals at at least 1nm/sec. As the evaporation rate > tends to be non-linear with power I think this decreases the heating > of the substrate. An increased distance from source to substrate will > also minimize heating of the substrate. Excess soak times may also > generate excess heat at the substrate. The most important technique, > which we use, to reduce heating is to have a "second" shutter very > close to the substrate, this shields the substrate from heating during > the ramp up and soak times. On the other hand I have no clue why this > would suddenly become an issue for you. > > I suppose you could try a test of evaporating more Au, so heating the > substrate more. Or evaporating Pt or W, which in my experience, > requires much more heat. Or, conversely evaporating a thinner layer of > Au to see if the cracking decreases. > > Regards, > > Mark K Mondol > > On 11/17/2015 4:50 PM, Espen Rogstad wrote: >> Hi John, >> We've also had issues with cracking and even bubbling of pmma during >> metallization. The problem was most severe for Pt deposition. We >> haven't gotten totally rid of the problem but the following helped in >> limiting it: >> - Increasing the deposition rate from 5?/s normally used to ~10?/s. >> - Increasing the source-sample distance. We have around 40cm distance >> in one of our e-beams and it mostly works fine. >> - Attaching samples to a 1cm thick aluminum disc (will act as a heat >> sink) using Mung II vacuum grease (we normally attach samples to a 4" >> Si wafer using kapton tape). >> - Putting the source material directly in the Cu pocket without using >> a crucible liner > -- Bryan Cord Minnesota Nano Center (MNC) University of Minnesota 115 Union St SE, Rm 153 Minneapolis, MN 55455 612.626.3287 (work) 857.891.6820 (cell) bcord at umn.edu http://wiki.umn.edu/EBPG From spaolini at cns.fas.harvard.edu Thu Nov 19 10:50:24 2015 From: spaolini at cns.fas.harvard.edu (Paolini, Steven) Date: Thu, 19 Nov 2015 15:50:24 +0000 Subject: [labnetwork] Thermocouple for JIPELEC JetFirst RTP system In-Reply-To: <7F3DC325FF6D6249B261422DED6D10514DD8AEAB@EXMBX2010-6.campus.MCGILL.CA> References: <7F3DC325FF6D6249B261422DED6D10514DD8AEAB@EXMBX2010-6.campus.MCGILL.CA> Message-ID: Lino, I have the same RTP and I have searched extensively for a second source of TC's for this system without any reasonable results. You cannot simply replace the junction wire within the sheath since it is potted inside to provide a vacuum seal. With the list of T/C manufacturers I have compiled over the years, it has been found that the cost of a Jipelec factory T/C is about what you would pay anyone else to fabricate one. What makes it unique is the fact that the sheath diameter is non standard for a T/C. What's worse is that it is either a "J" or "K" type (I forgot) which is rated for the temperature range of the RTP but Ideally only with momentary exposure to temperatures >900 Deg. C. This is why they open up and fail frequently. Ideally, the T/C would be of the type "R" or "S" which would last very long while sustaining very high temperatures. Unfortunately, these T/C's are made of platinum and rhodium wire and would end up costing about ten times the cost of a standard replacement. My advice would be to bite the bullet and order them 6 at a time. Hope this helps, Steve Paolini Equipment Dood Harvard University Center for Nanoscale Systems. From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Lino Eugene, Dr Sent: Wednesday, November 18, 2015 4:51 PM To: labnetwork at mtl.mit.edu Subject: [labnetwork] Thermocouple for JIPELEC JetFirst RTP system Dear colleagues, We have a JIPELEC JetFirst 200 rapid thermal processor. The spare thermocouples from the manufacturer are expensive and it seems that their lifetime is short. We are looking for a second source. We are thinking about replacing the damaged TC wire only. A bare wire TC can be purchased from Omega. Has anyone ever done that for their JetFirst system? Do you know thermocouple suppliers other than Omega? Thanks, _______________________________________________________________________________ Lino EUGENE, Ph.D., Jr. Eng. Research assistant McGill Nanotools - Microfab Mcgill University Rutherford Physics Building - Room 016 3600 University Street Montreal (Quebec) Canada H3A 2T8 Phone : 514 398 7329 Fax : 514 398 8434 E-mail : lino.eugene at mcgill.ca Website : www.mcgill.ca/microfab/ -------------- next part -------------- An HTML attachment was scrubbed... URL: From yglian at illinois.edu Thu Nov 19 12:40:42 2015 From: yglian at illinois.edu (Lian, Yaguang) Date: Thu, 19 Nov 2015 17:40:42 +0000 Subject: [labnetwork] Thermocouple for JIPELEC JetFirst RTP system In-Reply-To: References: <7F3DC325FF6D6249B261422DED6D10514DD8AEAB@EXMBX2010-6.campus.MCGILL.CA> Message-ID: <851B39526FEED74691E4131301DE17E51821C4FC@CITESMBX1.ad.uillinois.edu> Lino, I have the same RTP in the clean room, the model is JetFirst 100. I know the whole TC set is very expensive, because the chamber needs to keep vacuum. So I make the thermocouples myself by using Torr Seal. Maybe you can try. Good luck, Yaguang Lian Research Engineer 2306 Micro and Nanotechnology Laboratory University of Illinois at Urbana-Champaign 208 N. Wright St. Urbana, IL 61801 Phone: 217-333-8051 Email: yglian at illinois.edu From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Paolini, Steven Sent: 2015?11?19? 9:50 To: Lino Eugene, Dr ; labnetwork at mtl.mit.edu Subject: Re: [labnetwork] Thermocouple for JIPELEC JetFirst RTP system Lino, I have the same RTP and I have searched extensively for a second source of TC?s for this system without any reasonable results. You cannot simply replace the junction wire within the sheath since it is potted inside to provide a vacuum seal. With the list of T/C manufacturers I have compiled over the years, it has been found that the cost of a Jipelec factory T/C is about what you would pay anyone else to fabricate one. What makes it unique is the fact that the sheath diameter is non standard for a T/C. What?s worse is that it is either a ?J? or ?K? type (I forgot) which is rated for the temperature range of the RTP but Ideally only with momentary exposure to temperatures >900 Deg. C. This is why they open up and fail frequently. Ideally, the T/C would be of the type ?R? or ?S? which would last very long while sustaining very high temperatures. Unfortunately, these T/C?s are made of platinum and rhodium wire and would end up costing about ten times the cost of a standard replacement. My advice would be to bite the bullet and order them 6 at a time. Hope this helps, Steve Paolini Equipment Dood Harvard University Center for Nanoscale Systems. From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Lino Eugene, Dr Sent: Wednesday, November 18, 2015 4:51 PM To: labnetwork at mtl.mit.edu Subject: [labnetwork] Thermocouple for JIPELEC JetFirst RTP system Dear colleagues, We have a JIPELEC JetFirst 200 rapid thermal processor. The spare thermocouples from the manufacturer are expensive and it seems that their lifetime is short. We are looking for a second source. We are thinking about replacing the damaged TC wire only. A bare wire TC can be purchased from Omega. Has anyone ever done that for their JetFirst system? Do you know thermocouple suppliers other than Omega? Thanks, _______________________________________________________________________________ Lino EUGENE, Ph.D., Jr. Eng. Research assistant McGill Nanotools - Microfab Mcgill University Rutherford Physics Building - Room 016 3600 University Street Montreal (Quebec) Canada H3A 2T8 Phone : 514 398 7329 Fax : 514 398 8434 E-mail : lino.eugene at mcgill.ca Website : The MTL Mail Server has detected a possible fraud attempt from "urldefense.proofpoint.com" claiming to be www.mcgill.ca/microfab/ -------------- next part -------------- An HTML attachment was scrubbed... URL: From derose at caltech.edu Thu Nov 19 13:30:37 2015 From: derose at caltech.edu (DeRose, Guy A.) Date: Thu, 19 Nov 2015 18:30:37 +0000 Subject: [labnetwork] Thermocouple for JIPELEC JetFirst RTP system In-Reply-To: References: <7F3DC325FF6D6249B261422DED6D10514DD8AEAB@EXMBX2010-6.campus.MCGILL.CA> Message-ID: This is pretty good advice. Our Jetfirst 150 goes through the TC?s as well, but at least my users are using the pyrometer for the high temp processes. We need to replace our TC?s now in order to recalibrate the pyrometer that has been removed for maintenance, so I?m stuck with the vendor on those. I suspect the larger portion of the cost is for the calibration. Guy Guy DeRose, PhD, Member of the Professional Staff Associate Director, Kavli Nanoscience Institute California Institute of Technology, Pasadena, CA USA (O) 1-626-395-3423 (M) 1-626-676-8529 http://kni.caltech.edu Skype: guy_derose From: > on behalf of Matthew Oonk > Date: Thursday, November 19, 2015 at 6:29 AM To: "Lino Eugene, Dr" > Cc: "labnetwork at mtl.mit.edu" > Subject: Re: [labnetwork] Thermocouple for JIPELEC JetFirst RTP system We had the same problem with out TCs on our Jetfirst 100 and 150. It's mainly due to the fact that we have users who run high temperature recipes using the TC (our users don't use the pyrometer due to different substrate coatings causing it to vary.) The problem with Omega is that the TC is a strange length and it's hard to have confidence in the calibration adjustments in the software. The Jupilec TCs are a somehow callibrated by the vendors - I think that is half the expense. The only hack I can suggest is from Axic - if you have a glass blower on campus and the break is at the tip of the TC (usually where it is since it fuses with the Si and snaps,) you can have them re-bonded in a hot torch. -Matt Matthew Oonk Research Engineer Lurie Nanofabrication Facility University of Michigan 734-646-1275 mwoonk at umich.edu On Wed, Nov 18, 2015 at 4:50 PM, Lino Eugene, Dr > wrote: Dear colleagues, We have a JIPELEC JetFirst 200 rapid thermal processor. The spare thermocouples from the manufacturer are expensive and it seems that their lifetime is short. We are looking for a second source. We are thinking about replacing the damaged TC wire only. A bare wire TC can be purchased from Omega. Has anyone ever done that for their JetFirst system? Do you know thermocouple suppliers other than Omega? Thanks, _______________________________________________________________________________ Lino EUGENE, Ph.D., Jr. Eng. Research assistant McGill Nanotools - Microfab Mcgill University Rutherford Physics Building - Room 016 3600 University Street Montreal (Quebec) Canada H3A 2T8 Phone : 514 398 7329 Fax : 514 398 8434 E-mail : lino.eugene at mcgill.ca Website : www.mcgill.ca/microfab/ _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From lino.eugene at mcgill.ca Thu Nov 19 14:00:44 2015 From: lino.eugene at mcgill.ca (Lino Eugene, Dr) Date: Thu, 19 Nov 2015 19:00:44 +0000 Subject: [labnetwork] Thermocouple for JIPELEC JetFirst RTP system In-Reply-To: References: <7F3DC325FF6D6249B261422DED6D10514DD8AEAB@EXMBX2010-6.campus.MCGILL.CA> Message-ID: <7F3DC325FF6D6249B261422DED6D10514DD8B099@EXMBX2010-6.campus.MCGILL.CA> Thanks for your answers. I found some manuals for the JetFirst in Google and noticed that old versions of the software give access to the thermocouple calibration table. There is no way to access to the thermocouple calibration table in the software provided with our system. I guess that now the company doesn't want the customers to use other TCs than its. Lino _______________________________________________________________________________ Lino EUGENE, Ph.D., Jr. Eng. Research assistant McGill Nanotools - Microfab Mcgill University Rutherford Physics Building - Room 016 3600 University Street Montreal (Quebec) Canada H3A 2T8 Phone : 514 398 7329 Fax : 514 398 8434 E-mail : lino.eugene at mcgill.ca Website : www.mcgill.ca/microfab/ From: DeRose, Guy A. [mailto:derose at caltech.edu] Sent: Thursday, November 19, 2015 13:31 To: Matthew Oonk; Lino Eugene, Dr Cc: labnetwork at mtl.mit.edu Subject: Re: [labnetwork] Thermocouple for JIPELEC JetFirst RTP system This is pretty good advice. Our Jetfirst 150 goes through the TC's as well, but at least my users are using the pyrometer for the high temp processes. We need to replace our TC's now in order to recalibrate the pyrometer that has been removed for maintenance, so I'm stuck with the vendor on those. I suspect the larger portion of the cost is for the calibration. Guy Guy DeRose, PhD, Member of the Professional Staff Associate Director, Kavli Nanoscience Institute California Institute of Technology, Pasadena, CA USA (O) 1-626-395-3423 (M) 1-626-676-8529 http://kni.caltech.edu Skype: guy_derose From: > on behalf of Matthew Oonk > Date: Thursday, November 19, 2015 at 6:29 AM To: "Lino Eugene, Dr" > Cc: "labnetwork at mtl.mit.edu" > Subject: Re: [labnetwork] Thermocouple for JIPELEC JetFirst RTP system We had the same problem with out TCs on our Jetfirst 100 and 150. It's mainly due to the fact that we have users who run high temperature recipes using the TC (our users don't use the pyrometer due to different substrate coatings causing it to vary.) The problem with Omega is that the TC is a strange length and it's hard to have confidence in the calibration adjustments in the software. The Jupilec TCs are a somehow callibrated by the vendors - I think that is half the expense. The only hack I can suggest is from Axic - if you have a glass blower on campus and the break is at the tip of the TC (usually where it is since it fuses with the Si and snaps,) you can have them re-bonded in a hot torch. -Matt Matthew Oonk Research Engineer Lurie Nanofabrication Facility University of Michigan 734-646-1275 mwoonk at umich.edu On Wed, Nov 18, 2015 at 4:50 PM, Lino Eugene, Dr > wrote: Dear colleagues, We have a JIPELEC JetFirst 200 rapid thermal processor. The spare thermocouples from the manufacturer are expensive and it seems that their lifetime is short. We are looking for a second source. We are thinking about replacing the damaged TC wire only. A bare wire TC can be purchased from Omega. Has anyone ever done that for their JetFirst system? Do you know thermocouple suppliers other than Omega? Thanks, _______________________________________________________________________________ Lino EUGENE, Ph.D., Jr. Eng. Research assistant McGill Nanotools - Microfab Mcgill University Rutherford Physics Building - Room 016 3600 University Street Montreal (Quebec) Canada H3A 2T8 Phone : 514 398 7329 Fax : 514 398 8434 E-mail : lino.eugene at mcgill.ca Website : www.mcgill.ca/microfab/ _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From Thomas_Ferraguto at uml.edu Fri Nov 20 14:38:03 2015 From: Thomas_Ferraguto at uml.edu (Ferraguto, Thomas) Date: Fri, 20 Nov 2015 19:38:03 +0000 Subject: [labnetwork] Boron Powder for E-Beam Evaporation Message-ID: Colleagues, I have an industrial user that would like to use our (only) E-Beam Evaporator to deposit "Boron 10 metal Powder". My first response is "NO" because it's dopant. Has anyone done this and feels comfortable or has advice as to hour to abate the issues that my occur? Please advise. Thanks... Tom Thomas S. Ferraguto Saab ETIC Nanofabrication Laboratory Director University of Massachusetts Lowell 1 University Avenue Lowell MA 01854-5120 978-934-1809 land 617-755-0910 mobile 978-934-1014 fax [cid:image001.png at 01D123A1.0FE94E30] -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.png Type: image/png Size: 57996 bytes Desc: image001.png URL: From mmoneck at andrew.cmu.edu Mon Nov 23 23:28:47 2015 From: mmoneck at andrew.cmu.edu (Matt Moneck) Date: Mon, 23 Nov 2015 23:28:47 -0500 Subject: [labnetwork] Sputtering of AlScN Message-ID: <039401d12670$9cdb37a0$d691a6e0$@andrew.cmu.edu> Hi All, We have recently had a request in our facility to reactively sputter AlScN, either from an AlSc target or from co-sputtering of Al and Sc in an Ar/N2 environment. However, scandium is not a material that we have previously dealt with. The various MSDS I've read suggest there is little concern over toxicity, but I am also concerned about chamber contamination and incompatibility with other materials. Has anyone had experience with this material in their vacuum systems? Best Regards, Matt -- Matthew T. Moneck, Ph.D. Executive Manager, Carnegie Mellon Nanofabrication Facility Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.5430 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From lej at danchip.dtu.dk Wed Nov 25 03:58:25 2015 From: lej at danchip.dtu.dk (Leif Johansen) Date: Wed, 25 Nov 2015 08:58:25 +0000 Subject: [labnetwork] How do you handle PDMS in a cleanroom environment? Message-ID: <879AEF5002D70747B136D02BC86A9C985A1795@ait-pex02mbx05.win.dtu.dk> Dear Lab Network, I have a dilemma. Polydimethylsiloxane (PDMS) is a promising material for soft lithography, and a lot of our users have a strong wish to process this material in our lab - especially for making nanoimprint stamps . However, before being cured, PDMS is basically a silicone oil, and all our front end engineers (plasma chambers, lithography etc. ) are really scared about this substance ending up in their equipment. Our back end engineers (especially the wire bonding engineer) is also strongly opposed to the introduction of PDMS into the back end lab. Are there any experience out there in the community on how to handle PDMS in a cleanroom environment? Best regards, Leif Leif S. Johansen Head of Operations DTU Danchip Technical University of Denmark [http://www.dtu.dk/images/DTU_email_logo_01.gif] Danchip ?rsteds Plads, Byg. 347 2800 Lyngby Direct +45 45255713 Mobile +45 25348992 lesjo at danchip.dtu.dk www.danchip.dtu.dk/ -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.gif Type: image/gif Size: 1055 bytes Desc: image001.gif URL: From mark.chiappa at ntnu.no Wed Nov 25 09:51:13 2015 From: mark.chiappa at ntnu.no (Mark Giulio Chiappa) Date: Wed, 25 Nov 2015 14:51:13 +0000 Subject: [labnetwork] How do you handle PDMS in a cleanroom environment? In-Reply-To: <879AEF5002D70747B136D02BC86A9C985A1795@ait-pex02mbx05.win.dtu.dk> References: <879AEF5002D70747B136D02BC86A9C985A1795@ait-pex02mbx05.win.dtu.dk> Message-ID: Hi Leif, We have PDMS in the ISO 7 area of our cleanroom. Obviously we have a strict regime for this. All work is carried out in a designated fume hood. Uncured PDMS is only permitted in that fume hood. Users must wear an extra pair of gloves and often sleeve protectors when working with PDMS and remove them immediately after PDMS work. All PDMS equipment is clearly marked and all users, even the untrained PDMS users are made aware of the dangers PDMS represents and are told not to touch anything from the PDMS area. The responsible engineer is Mathilde you could contact her directly if you would like to have more information on the routines in the area. mathilde.i.barriet at ntnu.no . Kind regards Mark Mark Chiappa NTNU NanoLab Sem S?landsvei 14 7491 Trondheim Mob: +47 918 97 617 From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Leif Johansen Sent: 25. november 2015 09:58 To: labnetwork at mtl.mit.edu Subject: [labnetwork] How do you handle PDMS in a cleanroom environment? Dear Lab Network, I have a dilemma. Polydimethylsiloxane (PDMS) is a promising material for soft lithography, and a lot of our users have a strong wish to process this material in our lab - especially for making nanoimprint stamps . However, before being cured, PDMS is basically a silicone oil, and all our front end engineers (plasma chambers, lithography etc. ) are really scared about this substance ending up in their equipment. Our back end engineers (especially the wire bonding engineer) is also strongly opposed to the introduction of PDMS into the back end lab. Are there any experience out there in the community on how to handle PDMS in a cleanroom environment? Best regards, Leif Leif S. Johansen Head of Operations DTU Danchip Technical University of Denmark [http://www.dtu.dk/images/DTU_email_logo_01.gif] Danchip ?rsteds Plads, Byg. 347 2800 Lyngby Direct +45 45255713 Mobile +45 25348992 lesjo at danchip.dtu.dk www.danchip.dtu.dk/ -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.gif Type: image/gif Size: 1055 bytes Desc: image001.gif URL: From price.798 at osu.edu Wed Nov 25 10:33:29 2015 From: price.798 at osu.edu (Price, Aimee) Date: Wed, 25 Nov 2015 15:33:29 +0000 Subject: [labnetwork] How do you handle PDMS in a cleanroom environment? In-Reply-To: <879AEF5002D70747B136D02BC86A9C985A1795@ait-pex02mbx05.win.dtu.dk> References: <879AEF5002D70747B136D02BC86A9C985A1795@ait-pex02mbx05.win.dtu.dk> Message-ID: <83583687862B8444A85296A4944147DF8BF9BCBF@CIO-KRC-D2MBX09.osuad.osu.edu> Hi Leif, We actually have a lot of users who use PDMS for various uses here at Ohio State, including soft lithography. We allow it in most of our tools, including our plasma tools and metal deposition chambers that are reserved for high quality contacts with the requirement that the PDMS must be fully cured. We do allow some users to cure the PDMS on benchtops or hotplates in the cleanroom itself as well. We have not seen any problems with it, but we are not processing CMOS type structures. Mainly we deal with compounds III-V, III-N, ceramics, etc. I think it depends on what kind of user base you have, but in our case it would have excluded a lot of users to disallow it. However, we would have forbidden it if we felt that it would contaminate or found any contamination issues. I've copied our lab manager Paul in case he may have more to add on the subject. Best of luck, Aimee From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Leif Johansen Sent: Wednesday, November 25, 2015 3:58 AM To: labnetwork at mtl.mit.edu Subject: [labnetwork] How do you handle PDMS in a cleanroom environment? Dear Lab Network, I have a dilemma. Polydimethylsiloxane (PDMS) is a promising material for soft lithography, and a lot of our users have a strong wish to process this material in our lab - especially for making nanoimprint stamps . However, before being cured, PDMS is basically a silicone oil, and all our front end engineers (plasma chambers, lithography etc. ) are really scared about this substance ending up in their equipment. Our back end engineers (especially the wire bonding engineer) is also strongly opposed to the introduction of PDMS into the back end lab. Are there any experience out there in the community on how to handle PDMS in a cleanroom environment? Best regards, Leif Leif S. Johansen Head of Operations DTU Danchip Technical University of Denmark [http://www.dtu.dk/images/DTU_email_logo_01.gif] Danchip ?rsteds Plads, Byg. 347 2800 Lyngby Direct +45 45255713 Mobile +45 25348992 lesjo at danchip.dtu.dk www.danchip.dtu.dk/ -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.gif Type: image/gif Size: 1055 bytes Desc: image001.gif URL: From vito.logiudice at uwaterloo.ca Wed Nov 25 11:31:40 2015 From: vito.logiudice at uwaterloo.ca (Vito Logiudice) Date: Wed, 25 Nov 2015 16:31:40 +0000 Subject: [labnetwork] How do you handle PDMS in a cleanroom environment? Message-ID: <952ACE98-CBEB-491F-9095-0E5D9788376F@connect.uwaterloo.ca> Hi Leif, Based on some past experience with PDMS I agree with the concerns expressed by your engineers. If PDMS is handled carefully and conscientiously by your end users then possible damage can be contained or at least limited should it come into contact with any of your equipment. The problem many of us face in an academic setting however is the vast diversity of people whom use our facilities. A minority of these individuals tend to be inexperienced/disorganized/messy/self-absorbed and it is these people whom will possibly wreak havoc should you allow them to work with PDMS in your cleanroom. I recall slipping on a large glob of uncured PDMS that had been dropped on the floor of the cleanroom by one of these ?challenging users" at another site. Another concern may be the outgassing of silicone over time and its possible effects on other people?s work. I?m not an expert in this particular field but for instance, the use of silicone caulking was strictly forbidden during the construction of our cleanroom here. Hopefully Jack Paul of HDR Architecture will be able to share some insights in this regard (HDR designed our facility). For what it?s worth we do not currently allow PDMS in the cleanroom at all. Should a well-justified argument for introducing it be made in the future, I would likely insist on only allowing cured PDMS in the cleanroom and only in well-defined, possibly isolated, areas. Uncured work would only be permitted in a satellite (non-cleanroom) lab. Best regards, Vito -- Vito Logiudice P.Eng. Director of Operations, Quantum NanoFab University of Waterloo Lazaridis QNC 1207 200 University Avenue West Waterloo, ON Canada N2L 3G1 Tel.: (519) 888-4567 ext. 38703 Email: vito.logiudice at uwaterloo.ca Website: https://fab.qnc.uwaterloo.ca From: > on behalf of Leif Johansen > Date: Wednesday, November 25, 2015 at 3:58 AM To: "labnetwork at mtl.mit.edu" > Subject: [labnetwork] How do you handle PDMS in a cleanroom environment? Dear Lab Network, I have a dilemma. Polydimethylsiloxane (PDMS) is a promising material for soft lithography, and a lot of our users have a strong wish to process this material in our lab ? especially for making nanoimprint stamps . However, before being cured, PDMS is basically a silicone oil, and all our front end engineers (plasma chambers, lithography etc. ) are really scared about this substance ending up in their equipment. Our back end engineers (especially the wire bonding engineer) is also strongly opposed to the introduction of PDMS into the back end lab. Are there any experience out there in the community on how to handle PDMS in a cleanroom environment? Best regards, Leif Leif S. Johansen Head of Operations DTU Danchip Technical University of Denmark [http://www.dtu.dk/images/DTU_email_logo_01.gif] Danchip ?rsteds Plads, Byg. 347 2800 Lyngby Direct +45 45255713 Mobile +45 25348992 lesjo at danchip.dtu.dk www.danchip.dtu.dk/ -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.gif Type: image/gif Size: 1055 bytes Desc: image001.gif URL: From mmoneck at andrew.cmu.edu Wed Nov 25 11:50:41 2015 From: mmoneck at andrew.cmu.edu (Matt Moneck) Date: Wed, 25 Nov 2015 11:50:41 -0500 Subject: [labnetwork] How do you handle PDMS in a cleanroom environment? In-Reply-To: <879AEF5002D70747B136D02BC86A9C985A1795@ait-pex02mbx05.win.dtu.dk> References: <879AEF5002D70747B136D02BC86A9C985A1795@ait-pex02mbx05.win.dtu.dk> Message-ID: <020701d127a1$6c2113a0$44633ae0$@andrew.cmu.edu> Hi Leif, We get a lot of requests for PDMS in our lab, and we do allow users to process PDMS coated wafers/chips as well as cured PDMS molds. However, we have a lot of restrictions in place in order to mitigate the same concerns that you highlighted in your post. Our PDMS users are basically classified into two categories: thin-film and thick-film. The thin-film users are generally working with PDMS in the range of several microns or less. We allow spin-coating of these films in the cleanroom, but the users are restricted to a specific spinner and a specific hot plate. The thick-film users are working with hundreds of microns or even millimeters of PDMS. At the moment, we do not allow coating of such thick films in the cleanroom, as we found that it was simply too messy. They must coat and cure their samples outside the cleanroom. Fully cured PDMS samples are allowed in certain process equipment, but again, we had to restrict users to a specific subset of tools, as we have seen and are continually concerned about contamination. These films do outgas, so users are restricted to one of two sputtering systems for deposition. Samples are typically placed on carrier wafers to avoid contact with the substrate table. In addition, we limit the range of sputtering powers that users can run in an attempt to mitigate heat at the sample. So far, we have not had any vacuum issues or problems with other standard films in these tools. We also have an RIE dedicated to ?dirty? processes. Users are allowed to etch PDMS in this tool, but it does leave residue in the chamber that must be cleaned from time to time. In addition, users are restricted to a specific profilometer, as we found that even fully cured PDMS was contaminating the stylus in our other systems. Uncured PDMS is not allowed in any of our tools, and heating of PDMS in any vacuum system is not allowed. Hope this helps. Best Regards, Matt -- Matthew T. Moneck, Ph.D. Executive Manager, Carnegie Mellon Nanofabrication Facility Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.5430 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Leif Johansen Sent: Wednesday, November 25, 2015 3:58 AM To: labnetwork at mtl.mit.edu Subject: [labnetwork] How do you handle PDMS in a cleanroom environment? Dear Lab Network, I have a dilemma. Polydimethylsiloxane (PDMS) is a promising material for soft lithography, and a lot of our users have a strong wish to process this material in our lab ? especially for making nanoimprint stamps . However, before being cured, PDMS is basically a silicone oil, and all our front end engineers (plasma chambers, lithography etc. ) are really scared about this substance ending up in their equipment. Our back end engineers (especially the wire bonding engineer) is also strongly opposed to the introduction of PDMS into the back end lab. Are there any experience out there in the community on how to handle PDMS in a cleanroom environment? Best regards, Leif Leif S. Johansen Head of Operations DTU Danchip Technical University of Denmark Danchip ?rsteds Plads, Byg. 347 2800 Lyngby Direct +45 45255713 Mobile +45 25348992 lesjo at danchip.dtu.dk www.danchip.dtu.dk/ -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.gif Type: image/gif Size: 1055 bytes Desc: not available URL: From sbhas at uchicago.edu Wed Nov 25 12:11:25 2015 From: sbhas at uchicago.edu (Shivakumar Bhaskaran) Date: Wed, 25 Nov 2015 17:11:25 +0000 Subject: [labnetwork] How do you handle PDMS in a cleanroom environment? In-Reply-To: <879AEF5002D70747B136D02BC86A9C985A1795@ait-pex02mbx05.win.dtu.dk> References: <879AEF5002D70747B136D02BC86A9C985A1795@ait-pex02mbx05.win.dtu.dk> Message-ID: We have the soft litho lab outside the cleanroom. These device fabrication can be done outside the cleanroom. Yes these materials outgas if you are using it in RIE, evaporation chambers. Its better to have dedicated system for softlitho. There are small desktop plasma chambers available. -Shiva Shivakumar Bhaskaran, Ph.D. Searle CleanRoom Manager The University of Chicago 5735 S.Ellis, Room 032 Chicago-60637 Ph:773-795-2297 https://searle-cleanroom.uchicago.edu/ From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Leif Johansen Sent: Wednesday, November 25, 2015 2:58 AM To: labnetwork at mtl.mit.edu Subject: [labnetwork] How do you handle PDMS in a cleanroom environment? Dear Lab Network, I have a dilemma. Polydimethylsiloxane (PDMS) is a promising material for soft lithography, and a lot of our users have a strong wish to process this material in our lab - especially for making nanoimprint stamps . However, before being cured, PDMS is basically a silicone oil, and all our front end engineers (plasma chambers, lithography etc. ) are really scared about this substance ending up in their equipment. Our back end engineers (especially the wire bonding engineer) is also strongly opposed to the introduction of PDMS into the back end lab. Are there any experience out there in the community on how to handle PDMS in a cleanroom environment? Best regards, Leif Leif S. Johansen Head of Operations DTU Danchip Technical University of Denmark [http://www.dtu.dk/images/DTU_email_logo_01.gif] Danchip ?rsteds Plads, Byg. 347 2800 Lyngby Direct +45 45255713 Mobile +45 25348992 lesjo at danchip.dtu.dk www.danchip.dtu.dk/ -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.gif Type: image/gif Size: 1055 bytes Desc: image001.gif URL: From mtang at stanford.edu Thu Nov 26 11:03:54 2015 From: mtang at stanford.edu (Mary Tang) Date: Thu, 26 Nov 2015 08:03:54 -0800 Subject: [labnetwork] How do you handle PDMS in a cleanroom environment? In-Reply-To: <952ACE98-CBEB-491F-9095-0E5D9788376F@connect.uwaterloo.ca> References: <952ACE98-CBEB-491F-9095-0E5D9788376F@connect.uwaterloo.ca> Message-ID: <56572D6A.9070800@stanford.edu> Hi Leif -- At SNF, we do allow PDMS in the cleanroom, with certain restrictions. 1. It must be of the Sylgard 182 or 184 or similar variety, where there no volatile organics (i.e., no RTV's.) 2. Mixing and degassing are done outside of the cleanroom (we have a Thinky mixer in a prep area outside the cleanroom). This is to prevent uncured silicone oils from migrating everywhere -- as others have noted, extremely careful handling is required, but not a skill most of our students have acquired. If they spill the mixed PDMS, it will self-cure within a day. 3. Uncured PDMS is allowed only in the manual spin coat station (the one that can be lined with foil, for quick cleanup) and on the adjacent hot plates, when covered with foil. 4. Cured PDMS is allowed only in certain tools -- generally, those that run at low temperatures and are not used for front-end device processing. We've been able to control it, for the most part, because up to now, it's been a small population of researchers using this. But because of increased interest, we are trying to create establish more processes and create more work spaces outside the cleanroom, where students can spin coat, UV or plasma treat, bond, etc. Mary __ Mary X. Tang, Ph.D. Lab Manager Stanford Nanofabrication Facility Paul G. Allen Building Stanford, CA. 94305 mtang at stanford.edu (650)723-9980 http://snf.stanford.edu On 11/25/2015 8:31 AM, Vito Logiudice wrote: > Hi Leif, > > Based on some past experience with PDMS I agree with the concerns > expressed by your engineers. If PDMS is handled carefully and > conscientiously by your end users then possible damage can be > contained or at least limited should it come into contact with any of > your equipment. The problem many of us face in an academic setting > however is the vast diversity of people whom use our facilities. A > minority of these individuals tend to be > inexperienced/disorganized/messy/self-absorbed and it is these people > whom will possibly wreak havoc should you allow them to work with PDMS > in your cleanroom. I recall slipping on a large glob of uncured PDMS > that had been dropped on the floor of the cleanroom by one of these > ?challenging users" at another site. > > Another concern may be the outgassing of silicone over time and its > possible effects on other people?s work. I?m not an expert in this > particular field but for instance, the use of silicone caulking was > strictly forbidden during the construction of our cleanroom here. > Hopefully Jack Paul of HDR Architecture will be able to share some > insights in this regard (HDR designed our facility). > > For what it?s worth we do not currently allow PDMS in the cleanroom at > all. Should a well-justified argument for introducing it be made in > the future, I would likely insist on only allowing cured PDMS in the > cleanroom and only in well-defined, possibly isolated, areas. Uncured > work would only be permitted in a satellite (non-cleanroom) lab. > > Best regards, > Vito > -- > Vito Logiudice P.Eng. > Director of Operations, Quantum NanoFab > University of Waterloo > Lazaridis QNC 1207 > 200 University Avenue West > Waterloo, ON Canada N2L 3G1 > Tel.: (519) 888-4567 ext. 38703 > Email: vito.logiudice at uwaterloo.ca > Website: https://fab.qnc.uwaterloo.ca > > > From: > on behalf of Leif Johansen > > > Date: Wednesday, November 25, 2015 at 3:58 AM > To: "labnetwork at mtl.mit.edu " > > > Subject: [labnetwork] How do you handle PDMS in a cleanroom environment? > > Dear Lab Network, > > I have a dilemma. Polydimethylsiloxane (PDMS) is a promising material > for soft lithography, and a lot of our users have a strong wish to > process this material in our lab ? especially for making nanoimprint > stamps . However, before being cured, PDMS is basically a silicone > oil, and all our front end engineers (plasma chambers, lithography > etc. ) are really scared about this substance ending up in their > equipment. Our back end engineers (especially the wire bonding > engineer) is also strongly opposed to the introduction of PDMS into > the back end lab. > > Are there any experience out there in the community on how to handle > PDMS in a cleanroom environment? > > Best regards, > > Leif > > *Leif S. Johansen *** > > Head of Operations > > DTU Danchip > > *Technical University of Denmark*** > > > > http://www.dtu.dk/images/DTU_email_logo_01.gif > > Danchip > > ?rsteds Plads, Byg. 347 > > 2800 Lyngby > > Direct +45 45255713 > > Mobile +45 25348992 > > lesjo at danchip.dtu.dk > > www.danchip.dtu.dk/ > > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: