From sbhas at uchicago.edu Fri Feb 5 14:54:35 2016 From: sbhas at uchicago.edu (Shivakumar Bhaskaran) Date: Fri, 5 Feb 2016 19:54:35 +0000 Subject: [labnetwork] LiCoO2/Li3PO4 sputtering Message-ID: One of our user wants to sputter LiCoO2 and Li3PO4 for fabricating the battery device. Have anyone used this materials in your sputtering system. Will this material have contamination issue with other processes (mostly metals). Do I need to follow any safety procedures before/after sputtering. Thanks -Shiva Shivakumar Bhaskaran, Ph.D. Searle CleanRoom Manager The University of Chicago 5735 S.Ellis, Room 032 Chicago-60637 Ph:773-795-2297 https://searle-cleanroom.uchicago.edu/ -------------- next part -------------- An HTML attachment was scrubbed... URL: From vito.logiudice at uwaterloo.ca Mon Feb 8 16:53:39 2016 From: vito.logiudice at uwaterloo.ca (Vito Logiudice) Date: Mon, 8 Feb 2016 21:53:39 +0000 Subject: [labnetwork] Suggestions for interlocking O2 plasma & HMDS systems Message-ID: <09B153BB-7E27-410D-A495-C45AE23F634D@connect.uwaterloo.ca> Dear Colleagues, I?d greatly appreciate hearing from those of you whom have devised ways of safely interlocking a couple of systems we?re currently working on. These include the following: Oxygen plasma strip system: http://www.yieldengineering.com/Portals/0/YES-CV200RFS_specs.pdf HMDS prime oven: http://www.yieldengineering.com/Portals/0/YES-310TA_specs.pdf Thank you very much for any insights. Best regards, Vito -- Vito Logiudice P.Eng. Director of Operations, Quantum NanoFab University of Waterloo Lazaridis QNC 1207 200 University Avenue West Waterloo, ON Canada N2L 3G1 Tel.: (519) 888-4567 ext. 38703 Email: vito.logiudice at uwaterloo.ca Website: https://fab.qnc.uwaterloo.ca -------------- next part -------------- An HTML attachment was scrubbed... URL: From nclay at upenn.edu Mon Feb 8 20:04:10 2016 From: nclay at upenn.edu (Noah Clay) Date: Mon, 8 Feb 2016 20:04:10 -0500 Subject: [labnetwork] Suggestions for interlocking O2 plasma & HMDS systems In-Reply-To: <09B153BB-7E27-410D-A495-C45AE23F634D@connect.uwaterloo.ca> References: <09B153BB-7E27-410D-A495-C45AE23F634D@connect.uwaterloo.ca> Message-ID: <75901241-BC30-4F64-A3A2-243C414048F6@upenn.edu> Hey Vito, We interlock the pneumatics on our YES oven and barrel ashers with a simple 24V valve from McMaster-Carr; the valve cost is about $30. Best, Noah Sent from my iPhone > On Feb 8, 2016, at 16:53, Vito Logiudice wrote: > > Dear Colleagues, > > I?d greatly appreciate hearing from those of you whom have devised ways of safely interlocking a couple of systems we?re currently working on. These include the following: > > Oxygen plasma strip system: http://www.yieldengineering.com/Portals/0/YES-CV200RFS_specs.pdf > HMDS prime oven: http://www.yieldengineering.com/Portals/0/YES-310TA_specs.pdf > > Thank you very much for any insights. > > Best regards, > Vito > -- > Vito Logiudice P.Eng. > Director of Operations, Quantum NanoFab > University of Waterloo > Lazaridis QNC 1207 > 200 University Avenue West > Waterloo, ON Canada N2L 3G1 > Tel.: (519) 888-4567 ext. 38703 > Email: vito.logiudice at uwaterloo.ca > Website: https://fab.qnc.uwaterloo.ca > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From kjvowen at lnf.umich.edu Tue Feb 9 14:55:48 2016 From: kjvowen at lnf.umich.edu (Kevin Owen) Date: Tue, 9 Feb 2016 14:55:48 -0500 Subject: [labnetwork] Suggestions for interlocking O2 plasma & HMDS systems In-Reply-To: <09B153BB-7E27-410D-A495-C45AE23F634D@connect.uwaterloo.ca> References: <09B153BB-7E27-410D-A495-C45AE23F634D@connect.uwaterloo.ca> Message-ID: Vito, We have both of those tools and on both we interlocked the power to the touch screen. On our CV200RFS, we put TB10 pin 1 on a relay connected to our interlocking system. I did not open up the 310TA, but it's the same idea. -Kevin On Mon, Feb 8, 2016 at 4:53 PM, Vito Logiudice wrote: > Dear Colleagues, > > I?d greatly appreciate hearing from those of you whom have devised ways of > safely interlocking a couple of systems we?re currently working on. These > include the following: > > Oxygen plasma strip system: > http://www.yieldengineering.com/Portals/0/YES-CV200RFS_specs.pdf > HMDS prime oven: > http://www.yieldengineering.com/Portals/0/YES-310TA_specs.pdf > > Thank you very much for any insights. > > Best regards, > Vito > -- > Vito Logiudice P.Eng. > Director of Operations, Quantum NanoFab > University of Waterloo > Lazaridis QNC 1207 > 200 University Avenue West > Waterloo, ON Canada N2L 3G1 > Tel.: (519) 888-4567 ext. 38703 > Email: vito.logiudice at uwaterloo.ca > Website: https://fab.qnc.uwaterloo.ca > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork > > -- Kevin Owen Senior Engineer in Research Operations Group, Lurie Nanofabrication Facility University of Michigan (734) 545-4014 -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: 2016-02-09 14.43.56.jpg Type: image/jpeg Size: 863912 bytes Desc: not available URL: From julia.aebersold at louisville.edu Tue Feb 9 17:43:37 2016 From: julia.aebersold at louisville.edu (julia.aebersold at louisville.edu) Date: Tue, 9 Feb 2016 22:43:37 +0000 Subject: [labnetwork] Suggestions for interlocking O2 plasma & HMDS systems In-Reply-To: References: <09B153BB-7E27-410D-A495-C45AE23F634D@connect.uwaterloo.ca> Message-ID: We interlock the 110V pump on our YES HMDS Prime/Image Reversal systems. Cheers! Julia Aebersold, Ph.D. Cleanroom Manager Micro/Nano Technology Center University of Louisville Shumaker Research Building, Room 233 2210 South Brook Street Louisville, KY 40292 502-852-1572 http://louisville.edu/micronano/ From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Kevin Owen Sent: Tuesday, February 9, 2016 2:56 PM To: Vito Logiudice Cc: labnetwork at mtl.mit.edu Subject: Re: [labnetwork] Suggestions for interlocking O2 plasma & HMDS systems Vito, We have both of those tools and on both we interlocked the power to the touch screen. On our CV200RFS, we put TB10 pin 1 on a relay connected to our interlocking system. I did not open up the 310TA, but it's the same idea. -Kevin On Mon, Feb 8, 2016 at 4:53 PM, Vito Logiudice > wrote: Dear Colleagues, I?d greatly appreciate hearing from those of you whom have devised ways of safely interlocking a couple of systems we?re currently working on. These include the following: Oxygen plasma strip system: http://www.yieldengineering.com/Portals/0/YES-CV200RFS_specs.pdf HMDS prime oven: http://www.yieldengineering.com/Portals/0/YES-310TA_specs.pdf Thank you very much for any insights. Best regards, Vito -- Vito Logiudice P.Eng. Director of Operations, Quantum NanoFab University of Waterloo Lazaridis QNC 1207 200 University Avenue West Waterloo, ON Canada N2L 3G1 Tel.: (519) 888-4567 ext. 38703 Email: vito.logiudice at uwaterloo.ca Website: https://fab.qnc.uwaterloo.ca _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork -- Kevin Owen Senior Engineer in Research Operations Group, Lurie Nanofabrication Facility University of Michigan (734) 545-4014 -------------- next part -------------- An HTML attachment was scrubbed... URL: From lej at danchip.dtu.dk Wed Feb 10 06:07:56 2016 From: lej at danchip.dtu.dk (Leif Johansen) Date: Wed, 10 Feb 2016 11:07:56 +0000 Subject: [labnetwork] Suggestions for interlocking O2 plasma & HMDS systems In-Reply-To: <09B153BB-7E27-410D-A495-C45AE23F634D@connect.uwaterloo.ca> References: <09B153BB-7E27-410D-A495-C45AE23F634D@connect.uwaterloo.ca> Message-ID: <879AEF5002D70747B136D02BC86A9C985FD1BD@ait-pex02mbx05.win.dtu.dk> Hello Vito, We have plasma ashers from TePla. We have interlocked the ?Enter? and ?Run? buttons. We have a YES-310TA identical to yours. We have interlocked the valve on the HMDS line. If you are interested, we can send a sketch of the solution. A few people have forgotten to log in and only discovered their mistake when their patterns fell off the wafer during development. A bit unfortunate, but a good way to teach people that they should log on to equipment. Best regards, Leif Leif S. Johansen Head of Operations DTU Danchip Technical University of Denmark [http://www.dtu.dk/images/DTU_email_logo_01.gif] Danchip ?rsteds Plads, Byg. 347 2800 Lyngby Direct +45 45255713 Mobile +45 25348992 lesjo at danchip.dtu.dk www.danchip.dtu.dk/ From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Vito Logiudice Sent: 8. februar 2016 22:54 To: labnetwork at mtl.mit.edu Subject: [labnetwork] Suggestions for interlocking O2 plasma & HMDS systems Dear Colleagues, I?d greatly appreciate hearing from those of you whom have devised ways of safely interlocking a couple of systems we?re currently working on. These include the following: Oxygen plasma strip system: http://www.yieldengineering.com/Portals/0/YES-CV200RFS_specs.pdf HMDS prime oven: http://www.yieldengineering.com/Portals/0/YES-310TA_specs.pdf Thank you very much for any insights. Best regards, Vito -- Vito Logiudice P.Eng. Director of Operations, Quantum NanoFab University of Waterloo Lazaridis QNC 1207 200 University Avenue West Waterloo, ON Canada N2L 3G1 Tel.: (519) 888-4567 ext. 38703 Email: vito.logiudice at uwaterloo.ca Website: https://fab.qnc.uwaterloo.ca -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.gif Type: image/gif Size: 1055 bytes Desc: image001.gif URL: From vito.logiudice at uwaterloo.ca Thu Feb 11 09:18:49 2016 From: vito.logiudice at uwaterloo.ca (Vito Logiudice) Date: Thu, 11 Feb 2016 14:18:49 +0000 Subject: [labnetwork] Suggestions for interlocking O2 plasma & HMDS systems In-Reply-To: <879AEF5002D70747B136D02BC86A9C985FD1BD@ait-pex02mbx05.win.dtu.dk> References: <09B153BB-7E27-410D-A495-C45AE23F634D@connect.uwaterloo.ca> <879AEF5002D70747B136D02BC86A9C985FD1BD@ait-pex02mbx05.win.dtu.dk> Message-ID: <361B11A9-9D5C-445D-BC00-D46E34443238@connect.uwaterloo.ca> Hi Leif (and others), Thank you and everyone else for taking the time to share your very varied and helpful suggestions. It?s greatly appreciated. Best regards, Vito From: Leif Johansen > Date: Wednesday, February 10, 2016 at 6:07 AM To: Vito Logiudice >, "labnetwork at mtl.mit.edu" > Subject: RE: Suggestions for interlocking O2 plasma & HMDS systems Hello Vito, We have plasma ashers from TePla. We have interlocked the ?Enter? and ?Run? buttons. We have a YES-310TA identical to yours. We have interlocked the valve on the HMDS line. If you are interested, we can send a sketch of the solution. A few people have forgotten to log in and only discovered their mistake when their patterns fell off the wafer during development. A bit unfortunate, but a good way to teach people that they should log on to equipment. Best regards, Leif Leif S. Johansen Head of Operations DTU Danchip Technical University of Denmark [http://www.dtu.dk/images/DTU_email_logo_01.gif] Danchip ?rsteds Plads, Byg. 347 2800 Lyngby Direct +45 45255713 Mobile +45 25348992 lesjo at danchip.dtu.dk www.danchip.dtu.dk/ From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Vito Logiudice Sent: 8. februar 2016 22:54 To: labnetwork at mtl.mit.edu Subject: [labnetwork] Suggestions for interlocking O2 plasma & HMDS systems Dear Colleagues, I?d greatly appreciate hearing from those of you whom have devised ways of safely interlocking a couple of systems we?re currently working on. These include the following: Oxygen plasma strip system: http://www.yieldengineering.com/Portals/0/YES-CV200RFS_specs.pdf HMDS prime oven: http://www.yieldengineering.com/Portals/0/YES-310TA_specs.pdf Thank you very much for any insights. Best regards, Vito -- Vito Logiudice P.Eng. Director of Operations, Quantum NanoFab University of Waterloo Lazaridis QNC 1207 200 University Avenue West Waterloo, ON Canada N2L 3G1 Tel.: (519) 888-4567 ext. 38703 Email: vito.logiudice at uwaterloo.ca Website: https://fab.qnc.uwaterloo.ca -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.gif Type: image/gif Size: 1055 bytes Desc: image001.gif URL: From sbhas at uchicago.edu Mon Feb 15 10:50:04 2016 From: sbhas at uchicago.edu (Shivakumar Bhaskaran) Date: Mon, 15 Feb 2016 15:50:04 +0000 Subject: [labnetwork] Lithium Compound target in the Sputtering Message-ID: Due to interest of fabricating battery device, we have users requesting for sputtering LiCoO2 and Li3PO4. Have anyone used this materials in your sputtering system. Will this material have contamination issue with other processes (mostly metals). Do I need to follow any safety procedures before/after sputtering. Thanks -Shiva Shivakumar Bhaskaran, Ph.D. Searle CleanRoom Manager The University of Chicago 5735 S.Ellis, Room 032 Chicago-60637 Ph:773-795-2297 https://searle-cleanroom.uchicago.edu/ -------------- next part -------------- An HTML attachment was scrubbed... URL: From jrg at lesker.com Mon Feb 15 16:00:06 2016 From: jrg at lesker.com (JR Gaines) Date: Mon, 15 Feb 2016 21:00:06 +0000 Subject: [labnetwork] Lithium Compound target in the Sputtering In-Reply-To: References: Message-ID: Hello Shiva, The materials you mention are the principle layers of an all solid-state lithium ion battery. LiCoO2 is the cathode of the battery, and is electrically conductive so that it can be sputtered DC or RF. The Li3PO4 is an electrical insulator but ionic conductor so it must be sputtered by RF. Typically, the user wants to form a nitrogen-doped version of Li3PO4 which is similar to Li3PO(4-x)N(x) where x is about 0.3 ? so that the Li3PO4 needs to be sputtered in a background of N2. Some people use pure N2 as the working gas in the chamber Vs a mix of Ar/N2. A cartoon of the battery stack, as developed by Dr. John Bates et al .. at the Oak Ridge National Lab, is attached. You must avoid cross contamination between the LiCoO2 and Li3PO4 for obvious reasons. The LiCoO2 layer is typically grown on top of a high temperature electrode, like gold or tantalum, because the as-deposited film will likely be amorphous and require and ex-situ anneal in air to become crystalline. I am not aware of any safety issues as there is typically no free lithium that evolves during sputtering of these materials. I do suggest that you try and shield your chamber walls and other things in your chamber to facilitate clean up. If you want some papers on the sputter if the materials and thin film batteries in general let me know. J.R. From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Shivakumar Bhaskaran Sent: Monday, February 15, 2016 10:50 AM To: labnetwork at mtl.mit.edu Subject: [labnetwork] Lithium Compound target in the Sputtering Due to interest of fabricating battery device, we have users requesting for sputtering LiCoO2 and Li3PO4. Have anyone used this materials in your sputtering system. Will this material have contamination issue with other processes (mostly metals). Do I need to follow any safety procedures before/after sputtering. Thanks -Shiva Shivakumar Bhaskaran, Ph.D. Searle CleanRoom Manager The University of Chicago 5735 S.Ellis, Room 032 Chicago-60637 Ph:773-795-2297 https://searle-cleanroom.uchicago.edu/ JR Gaines | Technical Director of Education | Tel: +1 (412) 896-8402 | Cell: +1 (614) 446-2202 | Fax: +1 (412) 872-5046 | Email: jrg at lesker.com | Skype ID: kjlc.jrg | [http://www.lesker.com/newweb/emailsignature/EmailSignature_KJLCLogoMission.png] [http://www.lesker.com/newweb/emailsignature/EmailSignature_Twitter.png] [http://www.lesker.com/newweb/emailsignature/EmailSignature_LinkedIn.png] If this email is transmitted to you in error, please notify me, and then delete this email and all copies. If this email is sent for legal or business purposes, (a) this email and its content or attachments may include confidential and/or proprietary information of Kurt J. Lesker Company, in which case all rights to that information are reserved by the Company, and (b) your right and authorization to retain, and use, this information is limited to the purpose(s) expressly stated in, or reasonably implied by, this email. Any questions should be directed to me. Thank you. -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: Thin Film Battery cartoon from ORNL.png Type: image/png Size: 36100 bytes Desc: Thin Film Battery cartoon from ORNL.png URL: From Jacob.Trevino at asrc.cuny.edu Tue Feb 16 09:05:43 2016 From: Jacob.Trevino at asrc.cuny.edu (Jacob Trevino) Date: Tue, 16 Feb 2016 14:05:43 +0000 Subject: [labnetwork] Chips on a EVG 620 Message-ID: <72BD7637-B8C2-42C2-8398-AA7CAFF146B8@asrc.cuny.edu> Hello All, At the CUNY ASRC NanoFab, we have a EVG 620 mask aligner with 6? and 4? wafer tooling. We have a number of users who need to process chips of varying sizes. In some cases, users need the flexibility to move the chip across the mask. As I am sure you are familiar, many researchers have several chip layers across one photomask. It seems as though EVG?s tooling options for chips are fairly limited with less flexibility than I have seen with SUSS chucks in the past. I am curious what other EVG mask aligner owners do to accommodate users who need to perform lithography on chips. Have you made your own custom tooling? Any thoughts would be greatly appreciated. Best regards, Jacob -------------------------------- Jacob Trevino, PhD NanoFabrication Facility Director The City University of New York (CUNY) Advanced Science Research Center (ASRC) Tel. (212) 413-3310 Cel. (646) 629-1179 Email: Jacob.Trevino at asrc.cuny.edu Web: http://asrc.cuny.edu/ -------------- next part -------------- An HTML attachment was scrubbed... URL: From fouad.karouta at anu.edu.au Tue Feb 16 17:25:01 2016 From: fouad.karouta at anu.edu.au (Fouad Karouta) Date: Tue, 16 Feb 2016 22:25:01 +0000 Subject: [labnetwork] Chips on a EVG 620 In-Reply-To: <72BD7637-B8C2-42C2-8398-AA7CAFF146B8@asrc.cuny.edu> References: <72BD7637-B8C2-42C2-8398-AA7CAFF146B8@asrc.cuny.edu> Message-ID: Hi Jacob, Indeed the EVG 620 is not as flexible as the Suss MA6 for instance. We do have an EVG620 and similarly to your case we have people working with small samples and therefore we purchased a mask chuck with a 55mm dia opening allowing user to position the mask to the desired pattern. You need the chuck and the corresponding loading frame. In parallel you also need to have a sample chuck holder for small pieces. We do have one for 2? (EVG said it works for small pieces) but due to the vacuum grooves working with 10x10 mm2 sample will not give you the best resolution as sample cannot be clamped with vacuum. Maybe EVG offers now more suitable chuck for small pieces. Along all these hardware tools you also need a software upgrade (service visit) to include these parts in the software. A rather expensive upgrade. Let me know if you need more details on this that we do it outside the labnetowrk. Kind regards, Fouad Karouta ANFF ACT Node Manager From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Jacob Trevino Sent: Wednesday, 17 February 2016 1:06 AM To: labnetwork at mtl.mit.edu Subject: [labnetwork] Chips on a EVG 620 Hello All, At the CUNY ASRC NanoFab, we have a EVG 620 mask aligner with 6? and 4? wafer tooling. We have a number of users who need to process chips of varying sizes. In some cases, users need the flexibility to move the chip across the mask. As I am sure you are familiar, many researchers have several chip layers across one photomask. It seems as though EVG?s tooling options for chips are fairly limited with less flexibility than I have seen with SUSS chucks in the past. I am curious what other EVG mask aligner owners do to accommodate users who need to perform lithography on chips. Have you made your own custom tooling? Any thoughts would be greatly appreciated. Best regards, Jacob -------------------------------- Jacob Trevino, PhD NanoFabrication Facility Director The City University of New York (CUNY) Advanced Science Research Center (ASRC) Tel. (212) 413-3310 Cel. (646) 629-1179 Email: Jacob.Trevino at asrc.cuny.edu Web: http://asrc.cuny.edu/ -------------- next part -------------- An HTML attachment was scrubbed... URL: From nclay at seas.upenn.edu Tue Feb 16 11:45:51 2016 From: nclay at seas.upenn.edu (Noah Clay) Date: Tue, 16 Feb 2016 11:45:51 -0500 Subject: [labnetwork] Chips on a EVG 620 In-Reply-To: <72BD7637-B8C2-42C2-8398-AA7CAFF146B8@asrc.cuny.edu> References: <72BD7637-B8C2-42C2-8398-AA7CAFF146B8@asrc.cuny.edu> Message-ID: Hi Jacob, Check out Class One for this: http://parts.classoneequipment.com/all_parts/EVG/EVG-_56.html Best regards, Noah > On Feb 16, 2016, at 9:05 AM, Jacob Trevino wrote: > > Hello All, > > At the CUNY ASRC NanoFab, we have a EVG 620 mask aligner with 6? and 4? wafer tooling. We have a number of users who need to process chips of varying sizes. In some cases, users need the flexibility to move the chip across the mask. As I am sure you are familiar, many researchers have several chip layers across one photomask. > > It seems as though EVG?s tooling options for chips are fairly limited with less flexibility than I have seen with SUSS chucks in the past. I am curious what other EVG mask aligner owners do to accommodate users who need to perform lithography on chips. Have you made your own custom tooling? Any thoughts would be greatly appreciated. > > Best regards, > Jacob > > > -------------------------------- > Jacob Trevino, PhD > NanoFabrication Facility Director > The City University of New York (CUNY) > Advanced Science Research Center (ASRC) > Tel. (212) 413-3310 > Cel. (646) 629-1179 > Email: Jacob.Trevino at asrc.cuny.edu > Web: http://asrc.cuny.edu/ > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From Vincent.Luciani at nist.gov Wed Feb 17 09:12:54 2016 From: Vincent.Luciani at nist.gov (Luciani, Vincent) Date: Wed, 17 Feb 2016 14:12:54 +0000 Subject: [labnetwork] Lithium Compound target in the Sputtering In-Reply-To: References: Message-ID: Hello Shiva, We successfully sputter deposit these materials. Dr. Gerard Henein (copied) is the scientist responsible for our sputter tools and processes and is a wealth of information. I would suggest giving him a call if you want some first-hand experience and expertise. Gerard's number is 301-975-5645. Best Regards, Vince Vincent K. Luciani NanoFab Manager Center for Nanoscale Science and Technology National Institute of Standards and Technology 100 Bureau Drive, MS 6201 Gaithersburg, MD 20899-6200 USA +1-301-975-2886 From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Shivakumar Bhaskaran Sent: Monday, February 15, 2016 10:50 AM To: labnetwork at mtl.mit.edu Subject: [labnetwork] Lithium Compound target in the Sputtering Due to interest of fabricating battery device, we have users requesting for sputtering LiCoO2 and Li3PO4. Have anyone used this materials in your sputtering system. Will this material have contamination issue with other processes (mostly metals). Do I need to follow any safety procedures before/after sputtering. Thanks -Shiva Shivakumar Bhaskaran, Ph.D. Searle CleanRoom Manager The University of Chicago 5735 S.Ellis, Room 032 Chicago-60637 Ph:773-795-2297 https://searle-cleanroom.uchicago.edu/ -------------- next part -------------- An HTML attachment was scrubbed... URL: From hollingshead.19 at osu.edu Wed Feb 17 10:08:41 2016 From: hollingshead.19 at osu.edu (Hollingshead, David) Date: Wed, 17 Feb 2016 15:08:41 +0000 Subject: [labnetwork] Chips on a EVG 620 In-Reply-To: References: <72BD7637-B8C2-42C2-8398-AA7CAFF146B8@asrc.cuny.edu> Message-ID: <14E984EF1C44A342BE084EC29BE52DAF13A1D7F8@CIO-TNC-D2MBX04.osuad.osu.edu> Hi Jacob, Like you we have quite a few users who work with small pieces and also use EVG620 aligners. I would guess we see more chip lithography than full wafer lithography. Over the years there have been a couple of techniques developed to deal with this. 1) The first involves using wide cleanroom tape to cover a 4? (or 2?) vacuum chuck. Small holes are then poked in the vacuum grooves near where the sample needs to be placed. This was the technique of choice for quite some time. Often the vacuum hold is not very good however and overlaps in the tape can cause many issues. 2) Recently a group of users came up with another option that I personally think works quite well. This involves using a 4? Si wafer as a carrier. Personally I have had success using the unpolished backside of the wafer. A small amount of water is placed on the surface (we use a pipette) to create a very thin film. The sample is then placed on the carrier and the water film adheres the sample to the carrier, keeping it in place during alignment and exposure. It is the same idea as sticking two glass slides together with a drop of water. The key is to limit the amount of water, too much and the sample will simply slide around. The beauty of this technique is that the sample can be placed anywhere on the carrier. Additionally, the carrier can be marked or scribed to denote the position where the samples need to go for each mask level. The next time the user needs to run the mask they can easily locate where the sample should go. You could go even further and mask and coat a carrier wafer with a grid or location reference for a more exact ?fixture?. With either of the above options the user must still be careful to roughly align the sample on the carrier to ensure that there is enough travel in the stage to do alignment. Dealing with small pieces is never going to be as easy as full wafers but we?ve found that the techniques above do take quite a bit of the pain out of the ordeal. If you are doing many samples (ie. small production quantities) actual tooling would probably be a better option. For the small, occasional runs that many researchers and students are doing those these are a very low cost and simple way to get reasonable results using small pieces. If you need any more details please let me know. Thanks, -Dave Dave Hollingshead Research Engineer The Ohio State University Ohio Sensor and Semiconductor Innovation Platform Nanotech West Lab Suite 100, 1381 Kinnear Road, Columbus, OH 43212 614.292.1355 Office hollingshead.19 at osu.edu osu.edu From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Fouad Karouta Sent: Tuesday, February 16, 2016 5:25 PM To: Jacob Trevino; labnetwork at mtl.mit.edu Subject: Re: [labnetwork] Chips on a EVG 620 Hi Jacob, Indeed the EVG 620 is not as flexible as the Suss MA6 for instance. We do have an EVG620 and similarly to your case we have people working with small samples and therefore we purchased a mask chuck with a 55mm dia opening allowing user to position the mask to the desired pattern. You need the chuck and the corresponding loading frame. In parallel you also need to have a sample chuck holder for small pieces. We do have one for 2? (EVG said it works for small pieces) but due to the vacuum grooves working with 10x10 mm2 sample will not give you the best resolution as sample cannot be clamped with vacuum. Maybe EVG offers now more suitable chuck for small pieces. Along all these hardware tools you also need a software upgrade (service visit) to include these parts in the software. A rather expensive upgrade. Let me know if you need more details on this that we do it outside the labnetowrk. Kind regards, Fouad Karouta ANFF ACT Node Manager From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Jacob Trevino Sent: Wednesday, 17 February 2016 1:06 AM To: labnetwork at mtl.mit.edu Subject: [labnetwork] Chips on a EVG 620 Hello All, At the CUNY ASRC NanoFab, we have a EVG 620 mask aligner with 6? and 4? wafer tooling. We have a number of users who need to process chips of varying sizes. In some cases, users need the flexibility to move the chip across the mask. As I am sure you are familiar, many researchers have several chip layers across one photomask. It seems as though EVG?s tooling options for chips are fairly limited with less flexibility than I have seen with SUSS chucks in the past. I am curious what other EVG mask aligner owners do to accommodate users who need to perform lithography on chips. Have you made your own custom tooling? Any thoughts would be greatly appreciated. Best regards, Jacob -------------------------------- Jacob Trevino, PhD NanoFabrication Facility Director The City University of New York (CUNY) Advanced Science Research Center (ASRC) Tel. (212) 413-3310 Cel. (646) 629-1179 Email: Jacob.Trevino at asrc.cuny.edu Web: http://asrc.cuny.edu/ -------------- next part -------------- An HTML attachment was scrubbed... URL: From mark.chiappa at ntnu.no Wed Feb 17 12:42:12 2016 From: mark.chiappa at ntnu.no (Mark Giulio Chiappa) Date: Wed, 17 Feb 2016 17:42:12 +0000 Subject: [labnetwork] Chips on a EVG 620 In-Reply-To: <72BD7637-B8C2-42C2-8398-AA7CAFF146B8@asrc.cuny.edu> References: <72BD7637-B8C2-42C2-8398-AA7CAFF146B8@asrc.cuny.edu> Message-ID: Hi Jacob, Here at NTNU NanoLab we have a solution. It's not very elegant but it is cheap, flexible and does work. We use low tac tape (I forget the brand but I can let you know if you want it) to cover the entire area of the vacuum chuck with a hole in it for where the user wants to place their chip. That way the sample is held by system vacuum. The WEC works fine and we've had no complaints about the results. If your users are really pushing it and have their chip very close to the perimeter of the chuck it may be smart to place a dummy chip or even two to avoid a bad WEC. We use the same trick with our MA6. Kind regards Mark Sent from my iPhone On 16 Feb 2016, at 17:41, Jacob Trevino > wrote: Hello All, At the CUNY ASRC NanoFab, we have a EVG 620 mask aligner with 6" and 4" wafer tooling. We have a number of users who need to process chips of varying sizes. In some cases, users need the flexibility to move the chip across the mask. As I am sure you are familiar, many researchers have several chip layers across one photomask. It seems as though EVG's tooling options for chips are fairly limited with less flexibility than I have seen with SUSS chucks in the past. I am curious what other EVG mask aligner owners do to accommodate users who need to perform lithography on chips. Have you made your own custom tooling? Any thoughts would be greatly appreciated. Best regards, Jacob -------------------------------- Jacob Trevino, PhD NanoFabrication Facility Director The City University of New York (CUNY) Advanced Science Research Center (ASRC) Tel. (212) 413-3310 Cel. (646) 629-1179 Email: Jacob.Trevino at asrc.cuny.edu Web: http://asrc.cuny.edu/ _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From na2661 at columbia.edu Thu Feb 18 08:04:12 2016 From: na2661 at columbia.edu (Nava Ariel Sternberg) Date: Thu, 18 Feb 2016 08:04:12 -0500 Subject: [labnetwork] Lithium Compound target in the Sputtering In-Reply-To: References: Message-ID: Dear Shiva, I sputtered both materials in grad school. but I wasn't using a clean sputtering system. There are no special safety considerations (the lithium in these compounds is stable and is not reactive with N2 or moisture as elemental lithium) but the contamination of other metals deposited in the same system is a valid concern. I would use a less clean system for that if you have one. Hope this helps, Nava Nava Ariel-Sternberg, Ph.D. Director of CNI Facilities Columbia University 530 W120th Street, NY 10027 Room 1020/MC 8903 Office: 212-854-9927 Cell: 201-562-7600 On Mon, Feb 15, 2016 at 10:50 AM, Shivakumar Bhaskaran wrote: > > > Due to interest of fabricating battery device, we have users requesting > for sputtering LiCoO2 and Li3PO4. > > > > Have anyone used this materials in your sputtering system. Will this > material have contamination issue with other processes (mostly metals). Do > I need to follow any safety procedures before/after sputtering. > > > > Thanks > > -Shiva > > > > > > Shivakumar Bhaskaran, Ph.D. > > Searle CleanRoom Manager > > The University of Chicago > > 5735 S.Ellis, Room 032 > > Chicago-60637 > > Ph:773-795-2297 > > https://searle-cleanroom.uchicago.edu/ > > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From kjvowen at lnf.umich.edu Thu Feb 18 10:43:33 2016 From: kjvowen at lnf.umich.edu (Kevin Owen) Date: Thu, 18 Feb 2016 10:43:33 -0500 Subject: [labnetwork] Chips on a EVG 620 In-Reply-To: References: <72BD7637-B8C2-42C2-8398-AA7CAFF146B8@asrc.cuny.edu> Message-ID: We have a 620 but only use it for bond alignment. We do occasionally run into this on the our MA-6, our best recommendation is to put the process chip in the right spot on the chuck for the mask level they want to use and then put several other pieces of equal thickness around the chuck to even it out. -Kevin On Wed, Feb 17, 2016 at 12:42 PM, Mark Giulio Chiappa wrote: > Hi Jacob, > > Here at NTNU NanoLab we have a solution. It's not very elegant but it is > cheap, flexible and does work. We use low tac tape (I forget the brand but > I can let you know if you want it) to cover the entire area of the vacuum > chuck with a hole in it for where the user wants to place their chip. That > way the sample is held by system vacuum. The WEC works fine and we've had > no complaints about the results. If your users are really pushing it and > have their chip very close to the perimeter of the chuck it may be smart to > place a dummy chip or even two to avoid a bad WEC. > > We use the same trick with our MA6. > > Kind regards > Mark > > Sent from my iPhone > > On 16 Feb 2016, at 17:41, Jacob Trevino > wrote: > > Hello All, > > At the CUNY ASRC NanoFab, we have a EVG 620 mask aligner with 6? and 4? > wafer tooling. We have a number of users who need to process chips of > varying sizes. In some cases, users need the flexibility to move the chip > across the mask. As I am sure you are familiar, many researchers have > several chip layers across one photomask. > > It seems as though EVG?s tooling options for chips are fairly limited with > less flexibility than I have seen with SUSS chucks in the past. I am > curious what other EVG mask aligner owners do to accommodate users who need > to perform lithography on chips. Have you made your own custom tooling? Any > thoughts would be greatly appreciated. > > Best regards, > Jacob > > > -------------------------------- > > *Jacob Trevino, PhD* > NanoFabrication Facility Director > The City University of New York (CUNY) > Advanced Science Research Center (ASRC) > Tel. (212) 413-3310 > > Cel. (646) 629-1179 > > Email: Jacob.Trevino at asrc.cuny.edu > > Web: http://asrc.cuny.edu/ > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork > > -- Kevin Owen Senior Engineer in Research Operations Group, Lurie Nanofabrication Facility University of Michigan (734) 545-4014 -------------- next part -------------- An HTML attachment was scrubbed... URL: From nannini.matthieu at gmail.com Fri Feb 19 00:04:20 2016 From: nannini.matthieu at gmail.com (Matthieu Nannini) Date: Fri, 19 Feb 2016 00:04:20 -0500 Subject: [labnetwork] Ammonium Sulfide Message-ID: Dear labNetwork, Did any of you have the privilege of working with Ammonium Sulfide. I kind of need this chemical for a cleaning of GaN surface. Oh yeah ... also I would like to boil it. Any experience is welcomed ! Matthieu -------------- next part -------------- An HTML attachment was scrubbed... URL: From pilarhf at umich.edu Fri Feb 19 14:25:25 2016 From: pilarhf at umich.edu (Pilar Herrera-Fierro) Date: Fri, 19 Feb 2016 14:25:25 -0500 Subject: [labnetwork] Ammonium Sulfide In-Reply-To: References: Message-ID: Here at LNF our II-V users do it often. Yes it is heated NH4S. We do it in the base bench. Fortunately, they always have small pieces. We use small beakers on the hotplate, under the hood, collect the waste. Never had an issue (fingers crossed in the back) Pilar On Fri, Feb 19, 2016 at 12:04 AM, Matthieu Nannini < nannini.matthieu at gmail.com> wrote: > Dear labNetwork, > > Did any of you have the privilege of working with Ammonium Sulfide. I kind > of need this chemical for a cleaning of GaN surface. Oh yeah ... also I > would like to boil it. > > Any experience is welcomed ! > > Matthieu > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork > > -- Pilar Herrera-Fierro, Ph.D. LNF User Services Director Lurie Nanofabrication Facility University of Michigan RM 1239 EECS Building 1301 Beal Ave. Ann Arbor, MI 48109-2122 Cell 734 646 1399 (734) 646 1399 www.lnf.umich.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From cibuzar at umn.edu Fri Feb 19 15:50:08 2016 From: cibuzar at umn.edu (Gregory Cibuzar) Date: Fri, 19 Feb 2016 14:50:08 -0600 Subject: [labnetwork] Open Position: Ebeam Litho Research Scientist Message-ID: The Minnesota Nano Center at the University of Minnesota has an opening for a staff member to manage our nanoscale lithography processes. The major responsibility is to support the researchers who use our Vistec EBPG5000+ electron beam lithography tool. For more information or to apply, see the link below. Please feel free to contact me directly with any questions. https://www.myu.umn.edu/psp/psprd/EMPLOYEE/HRMS/c/HRS_HRAM.HRS_APP_SCHJOB.GBL?Page=HRS_APP_JBPST&Action=U&FOCUS=Applicant&SiteId=1&JobOpeningId=307751&PostingSeq=1 Regards, Greg Greg Cibuzar Manager, Minnesota Nano Center www.mnc.umn.edu University of Minnesota 612-625-8079 -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtiner at masdar.ac.ae Mon Feb 22 07:11:45 2016 From: mtiner at masdar.ac.ae (Mike Tiner) Date: Mon, 22 Feb 2016 12:11:45 +0000 Subject: [labnetwork] RTA bulb lifetime Message-ID: <89e6c91491c0499ab3011f062f39fae4@MI-MBX-PROD2.minet.ae> Dear Colleagues, One of our users is interested in using our RTA system as an anneal oven with recipe of ~1 hour at ~400C-500C. We would be interested to hear if anyone has experience with "long" hold times like this and we would also appreciate if there is readily available data on lamp lifetime vs. temperature. My initial feeling is that the setpoint temperature should not affect the lamp lifetime too much as it is my understanding that thermal shock is a main source of failure for the bulbs. It would also be helpful for us to know what is a reasonable expectation for bulb lifetime in this system (operating hours). We are running an accutherm AW 610. Any feedback is helpful, even if it is that we are being too cautious. Thanks in advance, mike Mike Tiner Director, Research Laboratories PO Box 54224, Khalifa City Abu Dhabi, United Arab Emirates Office +971 2 810 8122 Direct +971 2 810 9053 Fax +971 2 810 8121 Mobile +971 56 733 9604 Email mtiner at masdar.ac.ae http://www.masdar.ac.ae P Please consider the environment before printing this email This transmission is confidential and intended solely for the person or organization to whom it is addressed. It may contain privileged and confidential information. If you are not the intended recipient, you should not copy, distribute or take any action in reliance on it. If you have received this transmission in error, please notify us immediately by e-mail at info at masdar.ac.ae -------------- next part -------------- An HTML attachment was scrubbed... URL: From Thomas_Ferraguto at uml.edu Mon Feb 22 13:30:38 2016 From: Thomas_Ferraguto at uml.edu (Ferraguto, Thomas) Date: Mon, 22 Feb 2016 18:30:38 +0000 Subject: [labnetwork] FREE short course at UML in Partnership with Kurt J. Lesker Message-ID: Colleagues, We're hosting a free short course in vacuum with a hands on leak detection portion (at the end of the day in the clean room) March 16th , 2016. The main course is free , the break out session in the cleanroom requires you to become a registered user and pay for entry . (Industry rate is $32 day) The day includes lunch and refreshments. If you'd like to participate let me know. See the attached cut sheet from our friends at Kurt J. Lesker. Thomas S. Ferraguto Saab ETIC Nanofabrication Laboratory Director University of Massachusetts Lowell 1 University Avenue Lowell MA 01854-5120 978-934-1809 land 617-755-0910 mobile 978-934-1014 fax [cid:image003.png at 01D16D75.37436560] -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image003.png Type: image/png Size: 57996 bytes Desc: image003.png URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: UML- KJLC-ShortCourseDatasheet- for 16 March 2016.pdf Type: application/pdf Size: 537179 bytes Desc: UML- KJLC-ShortCourseDatasheet- for 16 March 2016.pdf URL: From IRHarvey at eng.utah.edu Mon Feb 22 17:51:07 2016 From: IRHarvey at eng.utah.edu (Ian Harvey) Date: Mon, 22 Feb 2016 15:51:07 -0700 Subject: [labnetwork] UGIM 2016 Abstract deadline Feb 29; Gold, Platinum sponsors full... References: <76B65CBD-2835-45F4-AB4D-5374F16EABED@eng.utah.edu> Message-ID: <6D6217EA-2B21-4565-98A5-620CB4C5FF92@eng.utah.edu> Dear Colleagues, ? Vendors & Exhibitors: Gold and platinum sponsorships are sold out. We still have some slots for workshop sponsorships which have platinum benefits. Contact Ian Harvey with any questions, by reply to this email http://ugim.nanofab.utah.edu/survey/ ? Lab Operations Staff: One more week to abstract submission Deadline: Leap Day! Feb 29, 2016 (see attached Call) Upload Abstracts here (including proposals for vendor workshops): http://ugim.nanofab.utah.edu/call-for-participation/ ? Registration information at: http://ugim.nanofab.utah.edu/registration/ In order to access the reserved block of rooms at the recommended University Guest House, please CALL them and refer to Nanofab/UGIM (the reserved rooms are not accessible through the University Guest House web portal?? it will just show "sold out"): University Guest House, 1-888-416-4075 Reference Nanofab / UGIM Short (~12 minutes) presentations including but not limited to the following topics: Equipment advances and tool selection (Looking for best practices here from facilities managers, not for a commercial solution from vendors) Acquiring and managing mission-critical tools How to fill the gap: nanolith technologies between EBL and UV contact litho How to bring in tools when they are not sexy anymore, but badly needed for capacity Case studies in evaluating and acquiring tools How to extend the life of aging tools and operating systems How to handle tools with a small user base (one PI for example) Tools with small user base but very expensive infrastructure (WF6 CVD for example): acquire/install or give PI money to have the work somewhere else? Renting space inside the cleanroom to individual groups? How do you collect rent and who maintains the tools? Some call it marketing, we call it Outreach, education and shared training media session How to use lab facilities to support educational programs? Student MEMS design competitions Teaching scaling engineering Filling the experiential gaps left by formal coursework Teaching DOE/SPC Media: marketing and outreach materials available for others to use ??? Media: safety training materials available for others to use Managing exotic materials: safely enabling new devices beyond simple scaling and design tricks Handling PDMS for microfluidics without contaminating the fab with oils Managing VO2, PZT and other materials whose properties of interest also raise risk for cross-contamination or toxic exposure Full-flow management schemes for segregating difficult materials and mitigating cost Fab efficiency and continuous improvement Communication: pass downs, staff meetings: how often, how to track projects and firefighting, best practices for interacting with faculty and researchers Telepresence robotics for 24/7 operations: non-hazardous safety buddy roles and facilitating remote communication between staff and researchers Navigating the transition to paperless billing: best practices Managing 24/7 operations Managing integrated cleanroom + analytical microscopy facilities Management peculiarities associated with international and remote facilities Managing multiple processes on a couple of etch tools: user responsibility for monitoring and conditioning or scheduled, staff-driven configuration changes? http://ugim.nanofab.utah.edu John Shott, Program Chair: jdshott at earthlink.net Amy VanRoosendaal: amy.van at utah.edu or 801-587-0676 -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: ugim-banner.png Type: image/png Size: 109631 bytes Desc: not available URL: From Jean.Lapointe at nrc-cnrc.gc.ca Tue Feb 23 12:46:55 2016 From: Jean.Lapointe at nrc-cnrc.gc.ca (Lapointe, Jean) Date: Tue, 23 Feb 2016 12:46:55 -0500 Subject: [labnetwork] Spinner problems with a Suss Labspin 8 Message-ID: Hello, Our Suss Microtech Labspin 8 spinner is giving problems as we observe the formation of 'cotton candy' - a hairy mess - in the bowl area when spin coating PMGI (SF15). This cotton candy can deposit itself on part of the wafers when the cycle is complete. We added a Venturi-type pump to increase the exhaust flow and measured 59 l/min near the bowl exhaust port using an anemometer. We're only measuring part of the exhaust flow and the total exhaust should be well above the 50 l/min recommended by Suss. We could use a mechanical pump to improve further increase the exhaust but a dry pump designed to handle solvent fumes may be needed. Has anyone else had this kind of problem and was a solution found? Thanks, Jean Dr Jean Lapointe ICT portfolio, Fab2 National Research Council, Canada -------------- next part -------------- An HTML attachment was scrubbed... URL: From kurt.kupcho at wisc.edu Tue Feb 23 17:17:40 2016 From: kurt.kupcho at wisc.edu (Kurt Kupcho) Date: Tue, 23 Feb 2016 22:17:40 +0000 Subject: [labnetwork] Ge in a deep Si RIE/ICP Message-ID: Hi All Here at UW we have a deep silicon etcher like most academic cleanrooms. We pretty much restrict the materials allowed in it to Si, SiO2, SiN, and photoresist. We do not allow any metals in the system. This is because of worries about mobile conductive ions and micro-masking problems that can occur from using metals in the system. Recently, we had a student request using Ge in the system. I know other academic cleanrooms have rather restrictive materials and rules for their Si DRIE systems as well and wanted to get your opinions on allowing Ge in such a system. Do you? Is there any problems with contamination or micro-masking? Any other additional thoughts beyond those two questions are much appreciated as well. Thanks! Kurt --------------------------------------------------- Kurt Kupcho Process Engineer WCAM 1550 Engineering Drive ECB Room 3110 Madison, WI 53706 E: kurt.kupcho at wisc.edu T: 608-262-2982 [http://wcam.engr.wisc.edu/logos/pics/wcam420x80.png] -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image003.png Type: image/png Size: 23961 bytes Desc: image003.png URL: From kjvowen at lnf.umich.edu Thu Feb 25 12:10:58 2016 From: kjvowen at lnf.umich.edu (Kevin Owen) Date: Thu, 25 Feb 2016 12:10:58 -0500 Subject: [labnetwork] Ge in a deep Si RIE/ICP In-Reply-To: References: Message-ID: While I don't think it has come up recently, we do allow Ge in our deep silicon etcher. It is a "semi-clean" tool (select "non-contaminating" metals and other materials are allowed). Generally speaking, though, Ge will etch in fluorine chemistries just as readily as Si, so we don't believe it will spread any contamination or change the chamber conditioning significantly. Also I suspect micro-masking would not be a problem, since it will etch in the same chemistry as the Si, anyway. -Kevin On Tue, Feb 23, 2016 at 5:17 PM, Kurt Kupcho wrote: > Hi All > > > > Here at UW we have a deep silicon etcher like most academic cleanrooms. > We pretty much restrict the materials allowed in it to Si, SiO2, SiN, and > photoresist. We do not allow any metals in the system. This is because of > worries about mobile conductive ions and micro-masking problems that can > occur from using metals in the system. Recently, we had a student request > using Ge in the system. I know other academic cleanrooms have rather > restrictive materials and rules for their Si DRIE systems as well and > wanted to get your opinions on allowing Ge in such a system. Do you? Is > there any problems with contamination or micro-masking? Any other > additional thoughts beyond those two questions are much appreciated as well. > > > > Thanks! > > > > Kurt > > > > > > --------------------------------------------------- > > Kurt Kupcho > > Process Engineer > > > > WCAM > > 1550 Engineering Drive > > ECB Room 3110 > > Madison, WI 53706 > > > > E: kurt.kupcho at wisc.edu > > T: 608-262-2982 > > > > [image: http://wcam.engr.wisc.edu/logos/pics/wcam420x80.png] > > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork > > -- Kevin Owen Senior Engineer in Research Operations Group, Lurie Nanofabrication Facility University of Michigan (734) 545-4014 -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image003.png Type: image/png Size: 23961 bytes Desc: not available URL: From nannini.matthieu at gmail.com Thu Feb 25 13:06:42 2016 From: nannini.matthieu at gmail.com (Matthieu Nannini) Date: Thu, 25 Feb 2016 13:06:42 -0500 Subject: [labnetwork] integrity of multiuser evaporator Message-ID: Dear all, Beside using a dedicated evaporator and/or using dedicated crucibles, how would you prepare this kind of tool for a sensitive process (Ni/Au 8/8nm) where cross-contamination could be an issue ? Thanks Matthieu -------------- next part -------------- An HTML attachment was scrubbed... URL: From yglian at illinois.edu Thu Feb 25 17:25:17 2016 From: yglian at illinois.edu (Lian, Yaguang) Date: Thu, 25 Feb 2016 22:25:17 +0000 Subject: [labnetwork] Ge in a deep Si RIE/ICP In-Reply-To: References: Message-ID: <851B39526FEED74691E4131301DE17E518282D35@CITESMBX1.ad.uillinois.edu> Kurt, The MNTL at the University of Illinois has a DRIE (STS ICP). I am the super user of the tool. I don?t have Ge issue right now because no users request using Ge in the system. But if the students want to use it, I will allow Ge into the system. Ge cannot give contamination to the chamber. After chemical reaction between Ge and F, the reactant GeF4 is volatile because the boiling point of GeF4 is -36.5C. After chemical reaction between Si and F, the boiling point of SiF4 is -86C. The fluorine based chemicals can be used to etch Si, and Ge as well, because of the volatile reactants. Some metals are not allowed to the fluorine system, such DRIE, because of non-volatile reactants. Aluminum, for example, the melting point of AlF3 is 1291C. If Al goes to the chamber with fluoride based chemicals, the tiny particles of AlF3 will deposit on the surface of wafer, causing micro-masking problem. Best regards, Yaguang Lian Research Engineer 2306 Micro and Nanotechnology Laboratory University of Illinois at Urbana-Champaign 208 N. Wright St. Urbana, IL 61801 Phone: 217-333-8051 Email: yglian at illinois.edu From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Kurt Kupcho Sent: 2016?2?23? 16:18 To: labnetwork at mtl.mit.edu Subject: [labnetwork] Ge in a deep Si RIE/ICP Hi All Here at UW we have a deep silicon etcher like most academic cleanrooms. We pretty much restrict the materials allowed in it to Si, SiO2, SiN, and photoresist. We do not allow any metals in the system. This is because of worries about mobile conductive ions and micro-masking problems that can occur from using metals in the system. Recently, we had a student request using Ge in the system. I know other academic cleanrooms have rather restrictive materials and rules for their Si DRIE systems as well and wanted to get your opinions on allowing Ge in such a system. Do you? Is there any problems with contamination or micro-masking? Any other additional thoughts beyond those two questions are much appreciated as well. Thanks! Kurt --------------------------------------------------- Kurt Kupcho Process Engineer WCAM 1550 Engineering Drive ECB Room 3110 Madison, WI 53706 E: kurt.kupcho at wisc.edu T: 608-262-2982 [http://wcam.engr.wisc.edu/logos/pics/wcam420x80.png] -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.png Type: image/png Size: 23961 bytes Desc: image001.png URL: From mmorgan3 at uw.edu Thu Feb 25 19:03:40 2016 From: mmorgan3 at uw.edu (Mark Morgan) Date: Thu, 25 Feb 2016 16:03:40 -0800 Subject: [labnetwork] Etching NbSe2 Message-ID: Greetings Friends and Neighbors, i have a user here at the Washington Nanofabrication Facility desirous of etching NbSe2 in our Flourine ICP system. I am seeking info/experience/suggestions regarding this activity and Selenium with respect to hazards and equipment contamination concerns. There is some info in the literature about RIE of this material via CF4 but i?m not seeing anything regarding hazards to equipment (especially equipment geared to many different users and projects?) and personnel. Probable etch products are SeF6 and NbF5(?)- The SeF6 appears to be a nasty actor but perhaps proper post-process pumping and purging (mmmm? alliteration!) would take care of that?. Thank you so much for the help and guidance. Best Regards Mark Mark D. Morgan Research Engineer, Washington Nanofabrication Facility (WNF) National Nanotechnology Coordinated Infrastructure (NNCI) University of Washington Fluke Hall 132, Box 352143 (206) 221-6349 mmorgan3 at uw.edu http://www.wnf.washington.edu/ -------------- next part -------------- An HTML attachment was scrubbed... URL: From nclay at upenn.edu Thu Feb 25 21:21:57 2016 From: nclay at upenn.edu (Noah Clay) Date: Thu, 25 Feb 2016 21:21:57 -0500 Subject: [labnetwork] Ge in a deep Si RIE/ICP In-Reply-To: <851B39526FEED74691E4131301DE17E518282D35@CITESMBX1.ad.uillinois.edu> References: <851B39526FEED74691E4131301DE17E518282D35@CITESMBX1.ad.uillinois.edu> Message-ID: Kurt, We have a request for deep etching Ge x-ray optics with our SPTS Rapier. As Yaguang pointed out, we don't have much concern about volatility of the byproducts. However, we use optical endpoint for chamber cleaning, which is tuned to SiF4 emission; we are not sure of the emission intensity of GeF4 (~400nm) and are therefore not quite certain of how this bodes for chamber cleaning (the endpoint detector gain settings are optimized for SiF4, etc.). Somewhat fortunate for us: we have data for etching similar x-ray structures in silicon and will likely write an over etch recipe for Ge that mirrors Si. Best, Noah Sent from my iPhone > On Feb 25, 2016, at 17:25, Lian, Yaguang wrote: > > Kurt, > > The MNTL at the University of Illinois has a DRIE (STS ICP). I am the super user of the tool. I don?t have Ge issue right now because no users request using Ge in the system. But if the students want to use it, I will allow Ge into the system. Ge cannot give contamination to the chamber. After chemical reaction between Ge and F, the reactant GeF4 is volatile because the boiling point of GeF4 is -36.5C. After chemical reaction between Si and F, the boiling point of SiF4 is -86C. The fluorine based chemicals can be used to etch Si, and Ge as well, because of the volatile reactants. Some metals are not allowed to the fluorine system, such DRIE, because of non-volatile reactants. Aluminum, for example, the melting point of AlF3 is 1291C. If Al goes to the chamber with fluoride based chemicals, the tiny particles of AlF3 will deposit on the surface of wafer, causing micro-masking problem. > > Best regards, > > Yaguang Lian > Research Engineer > 2306 Micro and Nanotechnology Laboratory > University of Illinois at Urbana-Champaign > 208 N. Wright St. > Urbana, IL 61801 > Phone: 217-333-8051 > Email: yglian at illinois.edu > > > > From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Kurt Kupcho > Sent: 2016?2?23? 16:18 > To: labnetwork at mtl.mit.edu > Subject: [labnetwork] Ge in a deep Si RIE/ICP > > Hi All > > Here at UW we have a deep silicon etcher like most academic cleanrooms. We pretty much restrict the materials allowed in it to Si, SiO2, SiN, and photoresist. We do not allow any metals in the system. This is because of worries about mobile conductive ions and micro-masking problems that can occur from using metals in the system. Recently, we had a student request using Ge in the system. I know other academic cleanrooms have rather restrictive materials and rules for their Si DRIE systems as well and wanted to get your opinions on allowing Ge in such a system. Do you? Is there any problems with contamination or micro-masking? Any other additional thoughts beyond those two questions are much appreciated as well. > > Thanks! > > Kurt > > > --------------------------------------------------- > Kurt Kupcho > Process Engineer > > WCAM > 1550 Engineering Drive > ECB Room 3110 > Madison, WI 53706 > > E: kurt.kupcho at wisc.edu > T: 608-262-2982 > > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://www-mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From yglian at illinois.edu Fri Feb 26 12:00:20 2016 From: yglian at illinois.edu (Lian, Yaguang) Date: Fri, 26 Feb 2016 17:00:20 +0000 Subject: [labnetwork] Etching NbSe2 In-Reply-To: References: Message-ID: <851B39526FEED74691E4131301DE17E518283436@CITESMBX1.ad.uillinois.edu> Mark, If the fluorine ICP system is used to etch silicon, I don?t think the NbSe2 can give you a big problem. Because after chemical reaction of NbSe2 with fluorine, all the byproducts are volatility. The Boiling point of NbF5 is 236C, SeF6 is -46.6C, and SeF4 is 101C. These numbers are all in the pressure of atmosphere. They will be much lower in the pressure of dry etching. If the pumping system uses turbo and dry pump, it cannot hurt the pump very much. If the ICP is used to etch SiO2 or Si3N4 films on the top of photoelectric or optical devices (III-V materials), I am afraid the residues of NbF5 can give some side-effects for the devices (dark current?). To avoid the contamination, a clean recipe can be run after NbSe2 dry etching. The recipe should use O2+CF4 as clean gases. Regards, Yaguang Lian Research Engineer 2306 Micro and Nanotechnology Laboratory University of Illinois at Urbana-Champaign 208 N. Wright St. Urbana, IL 61801 Phone: 217-333-8051 Email: yglian at illinois.edu From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Mark Morgan Sent: 2016?2?25? 18:04 To: labnetwork at mtl.mit.edu Subject: [labnetwork] Etching NbSe2 Greetings Friends and Neighbors, i have a user here at the Washington Nanofabrication Facility desirous of etching NbSe2 in our Flourine ICP system. I am seeking info/experience/suggestions regarding this activity and Selenium with respect to hazards and equipment contamination concerns. There is some info in the literature about RIE of this material via CF4 but i?m not seeing anything regarding hazards to equipment (especially equipment geared to many different users and projects?) and personnel. Probable etch products are SeF6 and NbF5(?)- The SeF6 appears to be a nasty actor but perhaps proper post-process pumping and purging (mmmm? alliteration!) would take care of that?. Thank you so much for the help and guidance. Best Regards Mark Mark D. Morgan Research Engineer, Washington Nanofabrication Facility (WNF) National Nanotechnology Coordinated Infrastructure (NNCI) University of Washington Fluke Hall 132, Box 352143 (206) 221-6349 mmorgan3 at uw.edu http://www.wnf.washington.edu/ -------------- next part -------------- An HTML attachment was scrubbed... URL: From Jacob.Trevino at asrc.cuny.edu Fri Feb 26 13:28:01 2016 From: Jacob.Trevino at asrc.cuny.edu (Jacob Trevino) Date: Fri, 26 Feb 2016 18:28:01 +0000 Subject: [labnetwork] Clean Room & Facilities Manager Position @ NYU Message-ID: <813AE23C-75E3-4601-AA45-316AECC00580@asrc.cuny.edu> Hello All, Our colleagues at NYU Tandon School of Engineering are hiring a Clean Room & Facilities Manager. They are finishing construction of a new facility and will be fitting it out over the coming years. Come join the growing nanofabrication community in NYC! https://www.nyucareers.com/applicants/jsp/shared/position/JobDetails_css.jsp?postingId=235806 Best regards, Jacob -------------------------------- Jacob Trevino, PhD NanoFabrication Facility Director The City University of New York (CUNY) Advanced Science Research Center (ASRC) Tel. (212) 413-3310 Cel. (646) 629-1179 Email: Jacob.Trevino at asrc.cuny.edu ASRC Web: http://asrc.cuny.edu/ NanoFab Web: http://nanofab.asrc.cuny.edu/ -------------- next part -------------- An HTML attachment was scrubbed... URL: From lrehn at tamu.edu Fri Feb 26 17:04:36 2016 From: lrehn at tamu.edu (Rehn, Larry A) Date: Fri, 26 Feb 2016 22:04:36 +0000 Subject: [labnetwork] Filaments for Wide Range Vacuum Gauge Message-ID: All, We have had filaments burn out several times in a Granville-Phillips Micro-Ion ATM, wide range vacuum gauge. Has anyone had success with changing out filaments in these types of gauges, instead of sending them back for service at the factory? Best regards, Larry A Rehn Technical Lab Manager AggieFab Nanofabrication Facility Texas A&M University 979 845-3199 lrehn at tamu.edu [cid:image001.jpg at 01CEC37D.FAF8C9E0] -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... 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