[labnetwork] Oxford ICP helium backside cooling performance

[Fouad Karouta]

Hi all,
Adding to what others mentioned I lie to add:
We use dedicated 4” Si wafers as carrier trays when etching small piers that are fixed with Dow Corning 340 heat sink paste, we ask the users to limit the paste to sample area iso it is not exposed directly to the plasma.
About the He leak it was less than 2 sccm.
If wafer tray or quartz clamp has a chip the He flow may increase so wafer trays should be exempt of chipping. If quartz clamp is damaged it needs replacement.
Note the wafer tray should be a good thermal conductor otherwise sample temperature may go much higher than electrode temperature especially with high ICP / RF powers.
Regards
Fouad Karouta
ANFF ACT Node, Canberra, Australia

Sent from my iPhone

On 20 Feb 2018, at 3:43 am, Aebersold,Julia W. <julia.aebersold at louisville.edu<mailto:julia.aebersold at louisville.edu>> wrote:

We emphasize a very clean backside before processing is performed.  Also, if processing has been performed prior to etching on the wafer then it can incur deformational stress that just makes it hard to sit on the chuck without an elevated leak up rate.

We also change the chuck o-rings when the rate starts to climb and perform O2 chamber cleans on a regular basis.

Cheers!

Julia Aebersold
Manager, Micro/Nano Technology Center
University of Louisville
Shumaker Research Building, Room 233
2210 South Brook Street
Louisville, KY  40292
(502) 852-1572

http://louisville.edu/micronano/

From: labnetwork-bounces at mtl.mit.edu<mailto:labnetwork-bounces at mtl.mit.edu> [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Luciani, Vincent (Fed)
Sent: Friday, February 16, 2018 3:49 PM
To: labnetwork at mtl.mit.edu<mailto:labnetwork at mtl.mit.edu>
Subject: [labnetwork] Oxford ICP helium backside cooling performance

Hello All,

We have 2 Oxford Plasmalab 100 ICP etch tools that are heavily used.  100 mm wafers are the most popular.  I am sure I discussed with many of you the trials and tribulations about these tools.  My question is about a yur experiences and lessons learned with regard to keeping the helium leak rate from underneath the wafer under control.  I am trying to get a general idea of what is typical and how we are doing compared to that.  We have several users that utilize the cryonic etching capability of our tools so the helium cooling is very important.  For those using the tool at -100 C, we find that 8 sccm is too high and users request repair.  We generally try to keep the leak rate < 5 sccm at all time but find this difficult to do with the variety of substrates and etch recipes.  We made some progress by ordering  specially made quartz discs with a cutout for the wafer flat for better wafer positioning.  I am happy to share the dwg if anyone would like it.

What is your experience?  What leak rate do you find tolerable and at what leak rate do you shut the tool down.  Any tricks you can share?


Thanks,
Vince


Vincent K. Luciani
NanoFab Manager
Center for Nanoscale Science and Technology<https://urldefense.proofpoint.com/v2/url?u=http-3A__www.cnst.nist.gov_&d=DwMFAg&c=OAG1LQNACBDguGvBeNj18Swhr9TMTjS-x4O_KuapPgY&r=l9C3cuOkWyGd6C0ye_FDTBHMFl4lPXPJztVHQPL_Bao&m=mdoZzuh-iVfW2dkEtxoD3tB5i278Se94ZmSWmOELTeI&s=EaRs0ZZXBmYM6V4o-hRirTnx1nBy5yHN8foZcdY62h4&e=>
National Institute of Standards and Technology
100 Bureau Drive, MS 6201
Gaithersburg, MD 20899-6200 USA
+1-301-975-2886





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