From mrisley at andrew.cmu.edu Mon Apr 1 10:08:55 2019 From: mrisley at andrew.cmu.edu (Mason Risley) Date: Mon, 1 Apr 2019 14:08:55 +0000 Subject: [labnetwork] Has anyone using thicker than 200nm HSQ for EBL patterning? In-Reply-To: <1DE742C03F382B44848ED7C52E4C3E41C13F3170@OC11EXPO30.exchange.mit.edu> References: , <4270623f-ea5c-a49f-e737-543acb5e07c3@yale.edu> <1DE742C03F382B44848ED7C52E4C3E41C13F3170@OC11EXPO30.exchange.mit.edu> Message-ID: Hi Mark, Thanks for mentioning about the dry HSQ, I didn't realize that was available. Do you know if dry HSQ has a better shelf life than the standard XR1541 in MIBK? That's a challenge my lab is always fighting that our HSQ ends up gelling or solidifying before we use the entire bottled, I'm wondering if by prepping smaller quantities from dry HSQ as needed would be a better way to manage shelf life. Mason Risley Process Development Engineer Clair and John Bertucci Nanotechnology Laboratory 5000 Forbes Street, Pittsburgh PA 15213 nanofab-staff at lists.andrew.cmu.edu | http://www.nanofab.ece.cmu.edu/ ph: 412.268.5419 | cell : 505.795.4805 From: labnetwork-bounces at mtl.mit.edu On Behalf Of Mark K Mondol Sent: Saturday, March 9, 2019 5:06 PM To: Michael Rooks ; labnetwork at mtl.mit.edu Subject: Re: [labnetwork] Has anyone using thicker than 200nm HSQ for EBL patterning? As usual I agree with Mike, but have to chime in anyway. Applied Quantum Materials in Canada offers dry HSQ, which you mix with MIBK to make a solution. I just got some and haven't used it yet, but others have. As it is dry you can make whatever dilution you want to achieve thicker films. ________________________________ From: labnetwork-bounces at mtl.mit.edu [labnetwork-bounces at mtl.mit.edu] on behalf of Michael Rooks [michael.rooks at yale.edu] Sent: Saturday, March 09, 2019 8:50 AM To: labnetwork at mtl.mit.edu Subject: Re: [labnetwork] Has anyone using thicker than 200nm HSQ for EBL patterning? Multiple-spins seldom produce good results. It's easier to use a thicker solution of HSQ. Of course you can buy thicker HSQ, such as Fox-16, but if you are in a hurry you can thicken the 6% HSQ (well, any resist really) by bubbling nitrogen through it. Just put a tube in the bottle and blow in some dry nitrogen. The solvent will evaporate, and the bubbles will keep the solution agitated, so a skin does not form on the surface. No need to be precise about the solution. Just keep bubbling until you get the thickness you want. ------------------------------------ Michael Rooks Yale Institute for Nanoscience and Quantum Engineering nano.yale.edu On 3/8/2019 10:02 PM, Zhao, Mengdi wrote: Hello everyone, I am trying to spin 350nm HSQ by double coating XR1541 6% at 2000rpm and bake at 80C between coating. However, HSQ thickness measured by reflectance spectrum actually get thinner after the second spin and bake. I wonder if the HSQ still get dissolved again during the 2nd dispense even with 80C bake for 4min after the first coating. Any suggestion on getting over 200nm HSQ spin coated on Si? Best regards, Mengdi _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From michael.rooks at yale.edu Mon Apr 1 10:15:35 2019 From: michael.rooks at yale.edu (Michael Rooks) Date: Mon, 01 Apr 2019 10:15:35 -0400 Subject: [labnetwork] Has anyone using thicker than 200nm HSQ for EBL patterning? In-Reply-To: References: , <4270623f-ea5c-a49f-e737-543acb5e07c3@yale.edu> <1DE742C03F382B44848ED7C52E4C3E41C13F3170@OC11EXPO30.exchange.mit.edu> Message-ID: <5CA21D07.9020107@yale.edu> You should be storing HSQ in liquid nitrogen. Check out the presentation https://nano.yale.edu/sites/default/files/files/hsq_frozen(1).pdf We have been doing this for five years, and it works great. Five year old HSQ is just as good as fresh HSQ. Getting reliable deliveries from Dow-Corning is an issue, but at least we don't have to worry about shelf life anymore. -------------------------------- Michael Rooks Yale Institute of Nanoscience and Quantum Engineering nano.yale.edu On 04/01/2019 10:08 AM, Mason Risley wrote: > > Hi Mark, > > Thanks for mentioning about the dry HSQ, I didn?t realize that was > available. Do you know if dry HSQ has a better shelf life than the > standard XR1541 in MIBK? That?s a challenge my lab is always fighting > that our HSQ ends up gelling or solidifying before we use the entire > bottled, I?m wondering if by prepping smaller quantities from dry HSQ > as needed would be a better way to manage shelf life. > > *Mason Risley* > > /Process Development Engineer/ > > /Clair and John Bertucci Nanotechnology Laboratory / > > 5000 Forbes Street, Pittsburgh PA 15213 > > nanofab-staff at lists.andrew.cmu.edu > | > http://www.nanofab.ece.cmu.edu/ > > ph: 412.268.5419 | cell : 505.795.4805 > > *From:*labnetwork-bounces at mtl.mit.edu > *On Behalf Of *Mark K Mondol > *Sent:* Saturday, March 9, 2019 5:06 PM > *To:* Michael Rooks ; labnetwork at mtl.mit.edu > *Subject:* Re: [labnetwork] Has anyone using thicker than 200nm HSQ > for EBL patterning? > > As usual I agree with Mike, but have to chime in anyway. Applied > Quantum Materials in Canada offers dry HSQ, which you mix with MIBK to > make a solution. I just got some and haven't used it yet, but others > have. As it is dry you can make whatever dilution you want to achieve > thicker films. > > ------------------------------------------------------------------------ > > *From:*labnetwork-bounces at mtl.mit.edu > > [labnetwork-bounces at mtl.mit.edu] on behalf of Michael Rooks > [michael.rooks at yale.edu] > *Sent:* Saturday, March 09, 2019 8:50 AM > *To:* labnetwork at mtl.mit.edu > *Subject:* Re: [labnetwork] Has anyone using thicker than 200nm HSQ > for EBL patterning? > > Multiple-spins seldom produce good results. It's easier to use a > thicker solution of HSQ. Of course you can buy thicker HSQ, such as > Fox-16, but if you are in a hurry you can thicken the 6% HSQ (well, > any resist really) by bubbling nitrogen through it. Just put a tube in > the bottle and blow in some dry nitrogen. The solvent will evaporate, > and the bubbles will keep the solution agitated, so a skin does not > form on the surface. No need to be precise about the solution. Just > keep bubbling until you get the thickness you want. > > ------------------------------------ > Michael Rooks > Yale Institute for Nanoscience and Quantum Engineering > nano.yale.edu > > On 3/8/2019 10:02 PM, Zhao, Mengdi wrote: > > Hello everyone, > > I am trying to spin 350nm HSQ by double coating XR1541 6% at > 2000rpm and bake at 80C between coating. However, HSQ thickness > measured by reflectance spectrum actually get thinner after the > second spin and bake. I wonder if the HSQ still get dissolved > again during the 2nd dispense even with 80C bake for 4min after > the first coating. Any suggestion on getting over 200nm HSQ spin > coated on Si? > > Best regards, > > Mengdi > > > > _______________________________________________ > > labnetwork mailing list > > labnetwork at mtl.mit.edu > > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > -------------- next part -------------- An HTML attachment was scrubbed... URL: From mrisley at andrew.cmu.edu Mon Apr 1 10:23:09 2019 From: mrisley at andrew.cmu.edu (Mason Risley) Date: Mon, 1 Apr 2019 14:23:09 +0000 Subject: [labnetwork] Has anyone using thicker than 200nm HSQ for EBL patterning? In-Reply-To: <5CA21D07.9020107@yale.edu> References: , <4270623f-ea5c-a49f-e737-543acb5e07c3@yale.edu> <1DE742C03F382B44848ED7C52E4C3E41C13F3170@OC11EXPO30.exchange.mit.edu> <5CA21D07.9020107@yale.edu> Message-ID: Thanks Michael, that is good information. I had it in mind to switch to cold storage and those HC LN2 refrigerators seem like a great way to go. I've also heard it helps to dispense the HSQ into the 4mL vials while in a nitrogen glove box to prevent exposing the stock solution to oxygen or humidity, do you guys do the same or do you just transfer from the stock bottle under ambient conditions in the clean room before freezing? From: Michael Rooks Sent: Monday, April 1, 2019 10:16 AM To: Mason Risley ; Mark K Mondol ; labnetwork at mtl.mit.edu Subject: Re: [labnetwork] Has anyone using thicker than 200nm HSQ for EBL patterning? You should be storing HSQ in liquid nitrogen. Check out the presentation https://nano.yale.edu/sites/default/files/files/hsq_frozen(1).pdf We have been doing this for five years, and it works great. Five year old HSQ is just as good as fresh HSQ. Getting reliable deliveries from Dow-Corning is an issue, but at least we don't have to worry about shelf life anymore. -------------------------------- Michael Rooks Yale Institute of Nanoscience and Quantum Engineering nano.yale.edu On 04/01/2019 10:08 AM, Mason Risley wrote: Hi Mark, Thanks for mentioning about the dry HSQ, I didn't realize that was available. Do you know if dry HSQ has a better shelf life than the standard XR1541 in MIBK? That's a challenge my lab is always fighting that our HSQ ends up gelling or solidifying before we use the entire bottled, I'm wondering if by prepping smaller quantities from dry HSQ as needed would be a better way to manage shelf life. Mason Risley Process Development Engineer Clair and John Bertucci Nanotechnology Laboratory 5000 Forbes Street, Pittsburgh PA 15213 nanofab-staff at lists.andrew.cmu.edu | http://www.nanofab.ece.cmu.edu/ ph: 412.268.5419 | cell : 505.795.4805 From: labnetwork-bounces at mtl.mit.edu On Behalf Of Mark K Mondol Sent: Saturday, March 9, 2019 5:06 PM To: Michael Rooks ; labnetwork at mtl.mit.edu Subject: Re: [labnetwork] Has anyone using thicker than 200nm HSQ for EBL patterning? As usual I agree with Mike, but have to chime in anyway. Applied Quantum Materials in Canada offers dry HSQ, which you mix with MIBK to make a solution. I just got some and haven't used it yet, but others have. As it is dry you can make whatever dilution you want to achieve thicker films. ________________________________ From: labnetwork-bounces at mtl.mit.edu [labnetwork-bounces at mtl.mit.edu] on behalf of Michael Rooks [michael.rooks at yale.edu] Sent: Saturday, March 09, 2019 8:50 AM To: labnetwork at mtl.mit.edu Subject: Re: [labnetwork] Has anyone using thicker than 200nm HSQ for EBL patterning? Multiple-spins seldom produce good results. It's easier to use a thicker solution of HSQ. Of course you can buy thicker HSQ, such as Fox-16, but if you are in a hurry you can thicken the 6% HSQ (well, any resist really) by bubbling nitrogen through it. Just put a tube in the bottle and blow in some dry nitrogen. The solvent will evaporate, and the bubbles will keep the solution agitated, so a skin does not form on the surface. No need to be precise about the solution. Just keep bubbling until you get the thickness you want. ------------------------------------ Michael Rooks Yale Institute for Nanoscience and Quantum Engineering nano.yale.edu On 3/8/2019 10:02 PM, Zhao, Mengdi wrote: Hello everyone, I am trying to spin 350nm HSQ by double coating XR1541 6% at 2000rpm and bake at 80C between coating. However, HSQ thickness measured by reflectance spectrum actually get thinner after the second spin and bake. I wonder if the HSQ still get dissolved again during the 2nd dispense even with 80C bake for 4min after the first coating. Any suggestion on getting over 200nm HSQ spin coated on Si? Best regards, Mengdi _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From mondol at mit.edu Mon Apr 1 10:48:04 2019 From: mondol at mit.edu (Mark K Mondol) Date: Mon, 1 Apr 2019 14:48:04 +0000 Subject: [labnetwork] Has anyone using thicker than 200nm HSQ for EBL patterning? In-Reply-To: References: , <4270623f-ea5c-a49f-e737-543acb5e07c3@yale.edu> <1DE742C03F382B44848ED7C52E4C3E41C13F3170@OC11EXPO30.exchange.mit.edu> <5CA21D07.9020107@yale.edu>, Message-ID: <1DE742C03F382B44848ED7C52E4C3E41C1409898@OC11EXPO30.exchange.mit.edu> Mason: I started storing HSQ in liquid N2 (make sure you crack open the lid when you take it out, some N2 will get into your bottle) and it works great. I started doing this at Mike's suggestion and completely agree with him. We had been decanting from the Dow, 100ml, containers to 1.5 mL cryo tubes in a glove box before we started with the liquid N2. This worked well for us so we continued doing it, though the glove box may not be necessary (segregating the HSQ from solvents, especially NMP is the goal). We then store the cryo tubes in a -60C fridge in the lab for convenience (little room for a dewar in the lab). The dry HSQ is advertised to have a very long shelf life if stored in a dry environment. I have not tried to use it yet, but have some on hand. HSQ delivery times, from Dow, are variable. Last time I ordered 6% in November, it arrived mid-March. Regards, Mark K Mondol ________________________________ From: Mason Risley [mrisley at andrew.cmu.edu] Sent: Monday, April 01, 2019 10:23 AM To: Michael Rooks; Mark K Mondol; labnetwork at mtl.mit.edu Subject: RE: [labnetwork] Has anyone using thicker than 200nm HSQ for EBL patterning? Thanks Michael, that is good information. I had it in mind to switch to cold storage and those HC LN2 refrigerators seem like a great way to go. I?ve also heard it helps to dispense the HSQ into the 4mL vials while in a nitrogen glove box to prevent exposing the stock solution to oxygen or humidity, do you guys do the same or do you just transfer from the stock bottle under ambient conditions in the clean room before freezing? From: Michael Rooks Sent: Monday, April 1, 2019 10:16 AM To: Mason Risley ; Mark K Mondol ; labnetwork at mtl.mit.edu Subject: Re: [labnetwork] Has anyone using thicker than 200nm HSQ for EBL patterning? You should be storing HSQ in liquid nitrogen. Check out the presentation https://nano.yale.edu/sites/default/files/files/hsq_frozen(1).pdf We have been doing this for five years, and it works great. Five year old HSQ is just as good as fresh HSQ. Getting reliable deliveries from Dow-Corning is an issue, but at least we don't have to worry about shelf life anymore. -------------------------------- Michael Rooks Yale Institute of Nanoscience and Quantum Engineering nano.yale.edu On 04/01/2019 10:08 AM, Mason Risley wrote: Hi Mark, Thanks for mentioning about the dry HSQ, I didn?t realize that was available. Do you know if dry HSQ has a better shelf life than the standard XR1541 in MIBK? That?s a challenge my lab is always fighting that our HSQ ends up gelling or solidifying before we use the entire bottled, I?m wondering if by prepping smaller quantities from dry HSQ as needed would be a better way to manage shelf life. Mason Risley Process Development Engineer Clair and John Bertucci Nanotechnology Laboratory 5000 Forbes Street, Pittsburgh PA 15213 nanofab-staff at lists.andrew.cmu.edu | http://www.nanofab.ece.cmu.edu/ ph: 412.268.5419 | cell : 505.795.4805 From: labnetwork-bounces at mtl.mit.edu On Behalf Of Mark K Mondol Sent: Saturday, March 9, 2019 5:06 PM To: Michael Rooks ; labnetwork at mtl.mit.edu Subject: Re: [labnetwork] Has anyone using thicker than 200nm HSQ for EBL patterning? As usual I agree with Mike, but have to chime in anyway. Applied Quantum Materials in Canada offers dry HSQ, which you mix with MIBK to make a solution. I just got some and haven't used it yet, but others have. As it is dry you can make whatever dilution you want to achieve thicker films. ________________________________ From: labnetwork-bounces at mtl.mit.edu [labnetwork-bounces at mtl.mit.edu] on behalf of Michael Rooks [michael.rooks at yale.edu] Sent: Saturday, March 09, 2019 8:50 AM To: labnetwork at mtl.mit.edu Subject: Re: [labnetwork] Has anyone using thicker than 200nm HSQ for EBL patterning? Multiple-spins seldom produce good results. It's easier to use a thicker solution of HSQ. Of course you can buy thicker HSQ, such as Fox-16, but if you are in a hurry you can thicken the 6% HSQ (well, any resist really) by bubbling nitrogen through it. Just put a tube in the bottle and blow in some dry nitrogen. The solvent will evaporate, and the bubbles will keep the solution agitated, so a skin does not form on the surface. No need to be precise about the solution. Just keep bubbling until you get the thickness you want. ------------------------------------ Michael Rooks Yale Institute for Nanoscience and Quantum Engineering nano.yale.edu On 3/8/2019 10:02 PM, Zhao, Mengdi wrote: Hello everyone, I am trying to spin 350nm HSQ by double coating XR1541 6% at 2000rpm and bake at 80C between coating. However, HSQ thickness measured by reflectance spectrum actually get thinner after the second spin and bake. I wonder if the HSQ still get dissolved again during the 2nd dispense even with 80C bake for 4min after the first coating. Any suggestion on getting over 200nm HSQ spin coated on Si? Best regards, Mengdi _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From escarra at tulane.edu Mon Apr 1 14:37:12 2019 From: escarra at tulane.edu (Escarra, Matthew D) Date: Mon, 1 Apr 2019 18:37:12 +0000 Subject: [labnetwork] Commercial power interlocks compatible with NEMO In-Reply-To: References: <5C9D2D81.1020203@cns.fas.harvard.edu> Message-ID: <0E4DCABE-5107-4D06-A75C-A31EAA95B9D6@tulane.edu> Hi Shane, We recently learned about a company called Safety Spot that has an off-the-shelf equipment energizer with associated software for lab management. I?m attaching a manual for their energizer with pictures and contact info at the end. Best, Matt ? Matthew Escarra Assistant Professor Department of Physics and Engineering Physics Tulane University 6400 Freret Street 2001 Percival Stern Hall New Orleans, LA 70118 (504) 862-8673 From: on behalf of Shimon Eliav Date: Friday, March 29, 2019 at 6:50 AM To: "labnetwork at mtl.mit.edu" Subject: Re: [labnetwork] Commercial power interlocks compatible with NEMO Hi Shane, Here at Hebrew University we use a 8 channels Digital I/O box from National Instruments (NI-9472): http://www.ni.com/en-il/shop/select/c-series-digital-module?modelId=122223 Simple to use, not expensive and very robust: in use for more than 10 years. Regards, Shimon From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Hathaway, Malcolm R Sent: Thursday, 28 March 2019 22:24 To: labnetwork at mtl.mit.edu Subject: Re: [labnetwork] Commercial power interlocks compatible with NEMO Hi Shane, I don't know if the ones we use are NEMO-compatible right out of the box, but the CLEAN system at Harvard CNS uses ADAM-6060 6-channel relays from Advantech. They are the only such ones I've run across, so perhaps everybody uses them, if they don't make their own. Just needs a static IP address, and compatible control software (which I suspect is quite generic)... Only drawback is they only have 6 channels, so you need many of them scattered around the labs to serve everything that is interlocked. We have them in these little boxes, which can serve up 6 sets of "dry contacts" (to work in series with tool internal interlock circuits), or 12V outputs, which we use to trigger power relays for equipment control PC monitors. Mac Mac Hathaway Senior Process and Systems Engineer Harvard Center for Nanoscale Systems 11 Oxford St. Cambridge, MA 02138 617-495-9012 On 3/28/2019 11:56 AM, Kevin M McPeak wrote: Dear Shane, Here at the LSU cleanroom we use NEMO and implemented an IP interlock system with a Raspberry PI an Arduino UNO and a 24V relay driver shield plus some Python code written by a CS student. We are happy with the results. If you are interested in learning more I am happy to discuss. Regards, Kevin On Wed, Mar 27, 2019 at 11:09 AM Xin (Shane) Guo wrote: Hi Colleagues, I saw that NEMO had been discussed here before. We are interested in NEMO as well. What's challenging for us to figure out is identifying IP-based power interlocks. I think that a lot of you bought FPGA boards and progammed them yourselves. Are there any commercial products compatible with NEMO and are ready to use with no or minimum customisation. Cheers Shane _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://nam04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fmtl.mit.edu%2Fmailman%2Flistinfo.cgi%2Flabnetwork&data=02%7C01%7Ckmcpeak%40lsu.edu%7Ce812531673624639c57b08d6b2ce921b%7C2d4dad3f50ae47d983a09ae2b1f466f8%7C0%7C0%7C636892997616270407&sdata=K8xOHFgu6JqQ4V8P9LBrjb67GqCCmCMvAxgNqu8Uul0%3D&reserved=0 -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: Safetyspot Equipment Energizer Instruction Manual 20190322 Generation 6_ (jh)(bji)(bji)[3].pdf Type: application/pdf Size: 703977 bytes Desc: Safetyspot Equipment Energizer Instruction Manual 20190322 Generation 6_ (jh)(bji)(bji)[3].pdf URL: From wjkiethe at ncsu.edu Mon Apr 1 15:13:06 2019 From: wjkiethe at ncsu.edu (Bill Kiether) Date: Mon, 1 Apr 2019 15:13:06 -0400 Subject: [labnetwork] SiC Fabrication Postdoctoral Researcher Position Opening - North Carolina State University Message-ID: The NCSU Nanofabrication Facility (NNF) seeks a talented and industrious experimentalist to join our team for a one-year term as a SiC Fabrication Postdoctoral Researcher. We have recently been awarded a grant from PowerAmerica that funds the development of a number of SiC power device process blocks, including implant mask fabrication, gate oxide formation, interlayer dielectric growth, and ohmic contact metallization. Interested individuals can apply at the following link: https://jobs.ncsu.edu/postings/115209 Please direct any questions to NNF Director of Operations, Dr. Phil Barletta: pbarlet at ncsu.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtkhbeis at gmail.com Tue Apr 2 11:08:18 2019 From: mtkhbeis at gmail.com (mtkhbeis at gmail.com) Date: Tue, 2 Apr 2019 08:08:18 -0700 Subject: [labnetwork] General maintenance engineer training Message-ID: <834EE297-075E-44C4-87A8-0BCAF9CF142D@gmail.com> Dear Colleagues and Friends, A friend of mine is establishing a field service engineering group and wants to know if anyone offers a semiconductor equipment short course on the safety/hazards aspects and best practices of working on (machine agnostic) equipment that processes hazardous and spec gasses, high voltage/power sources, etc. If anyone can recommend a program, please advise. Gratefully, Dr. Michael Khbeis (C) 443.254.5192 -------------- next part -------------- An HTML attachment was scrubbed... URL: From john_sweeney at harvard.edu Tue Apr 2 13:56:37 2019 From: john_sweeney at harvard.edu (Sweeney, John) Date: Tue, 2 Apr 2019 17:56:37 +0000 Subject: [labnetwork] General maintenance engineer training In-Reply-To: <834EE297-075E-44C4-87A8-0BCAF9CF142D@gmail.com> References: <834EE297-075E-44C4-87A8-0BCAF9CF142D@gmail.com> Message-ID: A good place to start is the training courses that SESHA offers http://seshaonline.org/training/ There online training is excellent and is pertinent to your needs. From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of mtkhbeis at gmail.com Sent: Tuesday, April 02, 2019 11:08 AM To: labnetwork at mtl.mit.edu Subject: [labnetwork] General maintenance engineer training Dear Colleagues and Friends, A friend of mine is establishing a field service engineering group and wants to know if anyone offers a semiconductor equipment short course on the safety/hazards aspects and best practices of working on (machine agnostic) equipment that processes hazardous and spec gasses, high voltage/power sources, etc. If anyone can recommend a program, please advise. Gratefully, Dr. Michael Khbeis (C) 443.254.5192 -------------- next part -------------- An HTML attachment was scrubbed... URL: From michael.martin at louisville.edu Wed Apr 3 10:51:13 2019 From: michael.martin at louisville.edu (Martin,Michael David) Date: Wed, 3 Apr 2019 14:51:13 +0000 Subject: [labnetwork] CMOS Clean in a MEMS Fab Facility In-Reply-To: <5fa3958d-d2db-8974-9078-8b0134784ee9@stanford.edu> References: <98970e3513f04e51806c9b4028476c83@tamu.edu>, <5fa3958d-d2db-8974-9078-8b0134784ee9@stanford.edu> Message-ID: Thank you everyone for taking the time to respond! I thought I would summarize the key take-aways on trying to move aspects of our MEMS fab to CMOS. First, though Mary to your point: we are actually trying to do some Ge on Silicon devices and this is what is driving the changes. Larry, we are using metal gates (Al-Si). You mentioned ?other tricks? for this case? Can you elaborate? Changes I'd like to implement: 1. RCA Cleans before any ?high? temperature process steps where ?high? temperatures might be locally induced by aggressive plasma based processes. Fortunately, we have a dedicated RCA bench. 2. Dedicated quartz or Teflon containers for lithography, Piranha cleans, and aluminum etch. Separate containers for aluminum lithography vs. completely metal free wafers? 3. We have had a dedicated furnace tube for some time but it was made ?compatible? after years of general oxidation use by an aggressive HF etch. I don?t think this is sufficient and will buy a new tube, rod, boat, etc? 4. We will begin monitoring contamination by regular CV tests 5. We will continue to use disposable polypropylene droppers for resist dispensing and amber bottles for CMOS resists 6. I will ask the management to set aside a spinner for CMOS compatible resists only with a particular emphasis on potential contamination from AZ 400k resists. We will stick to the Shipley S series. 7. Dedicated CMOS container for either NMP, piranha or other resist removal solvents. Thank you again! Regards, Michael ________________________________ From: Mary Tang Sent: Wednesday, March 20, 2019 5:17 PM To: Rehn, Larry A; Matthew Moneck; Martin,Michael David; labnetwork at mtl.mit.edu Subject: Re: [labnetwork] CMOS Clean in a MEMS Fab Facility Hi Michael, et al ? Good points, all. For the last few years, we have been asking ourselves the same questions, as we evolve from being predominately a CMOS-compatible lab to one where most of our labmembers don?t require this level of contamination control. It?s been a slower transition than we?d like, because the process requires unraveling the why?s of 60 years of best-known-practices, so we can figure out which rules we can break with minimal risk. The main question is what level of technology needs to be protected and to what degree. Our most demanding customers are the detector researchers. The next most demanding are the Ge/SiGe device researchers. So, we try to make sure to work with them to safeguard the high-risk process steps. The next step is to identify the process steps where there is possible transfer of contaminants. Basically, RCA cleans done before any high temperature step can rectify all sorts of assaults to the system. So at SNF, we don?t dedicate litho equipment for reasons of contamination and pretend that a CMOS substrate remains as CMOS clean when it leaves litho. There is basis for this pretense - resist developers in the 80?s were NaOH-based, but the post-etch resist cleans and pre-furnace RCA cleans were sufficient for that generation of technology. However, it?s also important to remember that temperatures don?t need to be very high for mobile ions to start migrating ? a high density plasma asher can get hot enough, so it?s advisable to carefully review the process runsheet. Depending on the stringency of your device requirements, it?s possible to share CMOS and non-CMOS processes on a single tool. You might be able to do a chamber clean or have dedicated cassettes, handlers, of inserts. You might be able to lay down a barrier or getter layer in a deposition system. You might be able to run a Cl-based clean cycle in an oxidation furnace. Lastly, every time a device run fails, the very first suspect is contamination. More often, it?s not, but rather because researchers often unknowingly violate 60 years of process integration best-practices with seemingly innocuous process changes (evaporating vs sputtering metal, damaging gates; changing barrier metal, resulting in spiking) or misprocessing (wrong implant dose). This is where careful review of the process runsheet with an experienced integration person can really save a lot of time and frustration. If you are building a process from scratch, it's best to build up from modules. I am far from expert, but will gladly share our experiences - and can refer you to the real experts. Best, Mary -- Mary X. Tang, Ph.D. Managing Director Stanford Nanofabrication Facility Paul G. Allen Building, Rm 141 420 Via Palou Mall Stanford, CA 94305 (650)723-9980 mtang at stanford.edu https://snf.stanford.edu On 3/20/2019 7:09 AM, Rehn, Larry A wrote: Hello Michael, I general, I would say that you need to be most careful to control any processes the involve elevated temperature, or cleanups that occur before steps with high temperature. I would suggest dedicated quartz containers for piranha cleans. Besides suggestions from Matt below, I would concentrate first on your oxidation and furnace operations. It is best to have dedicated oxidation tubes that never see any other materials except silicon and oxides, particularly metal for annealing , sintering etc. In fact most would have a dedicated field ox tube and a separate tube just for the gate oxidation step, which is the most critical. If you only have one furnace, then you will need to change out quartz tubes (and push rods, wafer boats, profile thermocouples, etc) for each operation. When you fabricate the CMOS device it is also important to control any other sources for Na+ contamination. Will you be using polysilicon gates, or metal? If metal, than there are other process tricks to make sure the gate integrity is preserved. There are also some ongoing things that are done to maintain cleanliness of the system. Cleaning of tubes with dilute HF, monitoring the gate/oxide device performance with CV tests will ensure that you do not have too much mobile ion concentration to affect the device. Good luck! Larry A Rehn Technical Lab Manager AggieFab Nanofabrication Facility Texas A&M University 979 845-3199 lrehn at tamu.edu [cid:image001.jpg at 01CEC37D.FAF8C9E0] From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Matthew Moneck Sent: Tuesday, March 19, 2019 11:59 AM To: Martin,Michael David ; labnetwork at mtl.mit.edu Subject: Re: [labnetwork] CMOS Clean in a MEMS Fab Facility Hi Michael, Our fab does not do a lot of traditional CMOS work, so I am by no means an expert in this area. A lot of our work is concentrated in MEMS (including back-end processing on CMOS tapeout chips), magnetics, spintronics, photonics, 2D materials, functional oxides, bio interfaces, other emerging technologies. However, I can hopefully offer a few comments from lessons learned or experiences we?ve had in the past, especially when working on devices where trapped charge or ion contamination were an issue. Referencing your original question numbers: 1. We typically use PTFE petri dishes for this application. We routinely process 100mm wafers in low profile evaporating dishes. While not cheap, a couple dishes won?t typically set you back too much. 2. We separate glassware for metal ion free (MIF) and metal ion containing (MIC) containers (I?m assuming you are using MIF developers for CMOS). Beakers are labeled MIF or MIC by etching the letters into the glass exterior of the beaker. If I recall correctly most of the beakers are Type 1, Class A, 33 expansion Borosilicate glass (note that I?m not endorsing this one way or the other for CMOS). 2A. We do not have a dedicated spinner for CMOS, but we do limit which resists can go in which spinners (in the case where non-standard resists are used). 2B. I would verify the type of glass used in the amber bottles. Also, we buy droppers in clean, sterile packaging, as we have seen that droppers packaged and stored incorrectly can introduce contaminates. In extreme cases, we have had some users request and move to glass pipettes. 2C. The shared bath of NMP would be one of my biggest concerns in this whole process. Manufacturers will list that NMP is safe on a lot of metals, including copper. However, there is a caveat. If the NMP bath collects or becomes contaminated with moisture, it makes the bath corrosive. I have seen first-hand how NMP can corrode, or even etch through metals, such as copper. If people are using the bath with such materials, it could have trace metals and other contaminants. We do not do a lot in the way of furnace work, so I will default to others in the network that are much more of an expert in this area than me, but for what it?s worth, the latter questions on quartz tube contaminants would be a concern in my opinion. Even in simple annealing furnaces and our RTA, we keep ?clean? and ?dirty? tubes/chambers that we exchange depending on the materials being used. In regards to potential vendors, we have purchased quartz products from Technical Glass Products in the past (https://technicalglass.com/), although, again, others who do a lot more work with furnaces will likely have more input than me. Hope this helps in some capacity. Best Regards, Matt -- Matthew T. Moneck, Ph.D. Executive Manager, Claire & John Bertucci Nanotechnology Laboratory Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.5430 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Martin,Michael David Sent: Monday, March 18, 2019 2:07 PM To: labnetwork at mtl.mit.edu Subject: [labnetwork] CMOS Clean in a MEMS Fab Facility Hi, I'm trying to track down potential sources of contamination for a CMOS process we are trying to run through our predominantly MEMS fab here at U of Louisville. Really the only pieces of equipment that are dedicated for CMOS type processes is our RCA bench, an older Technics sputterer, and our oxidation furnace (sort of, see below). So I have a few questions for those of you who have experience with this: 1) For HF etch/dips is there a particular polymer type or brand we should use for our containers that are known to be free of trace metals? Can I avoid PTFE as this is super expensive? 2) When you do litho do you have separate labware for developing? We currently use a Pyrex pan develop which I know is a No-No due to Na and other ions. What sort of container does your lab use (assuming pan develop)? 2 a) Do you have a dedicated spinner for CMOS? 2 b) Is there any danger that we are picking up contamination from the amber bottles we are temporarily storing our resists in? What about the polypropylene droppers we are dispensing resists with? 2 c) What about resist stripping after etching? We typically use a big warm vat of NMP that is shared by all users. We can also do a plasma etch but I worry about carry over from other folks as none of our plasma etchers are dedicated CMOS. 3) I presume quartz glassware works for my metal (usually aluminum) etching? Do you do regular aqua regia cleans on quartz-ware to scavenge other metals and potential contaminants? 4) We gravitate to peek tipped metal tweezers. Are they okay? Do you regularly run the tips through a RCA clean? 5) Oxidation furnace: Before trying to transition to CMOS like devices the tube was used with non-RCA cleaned wafers and a pyrex bubbler. After moving to a quartz bubbler with DI water we cleaned the 4" tube with HF. This is the one I'm really concerned about because I'm guessing that ionic contamination that might have been removed from the surface will readily diffuse back at 1000C. So should we just bite the bullet and buy a new tube? Any vendor suggestions for a 4" Blue-M? 6) Any other suggestions other than buying a dedicated CMOS tool set? I did find a very nice document from Stanford that has a lot of practical suggestions found here https://web.stanford.edu/class/ee410/cleaning.pdf ) Krishna Saraswa - Stanford University 6 tanford University araswat 11! Cleaning - Surface Issues Contaminant ? Organics ? Skin oils ? Resist ? Polymers ? Metals web.stanford.edu Thank you in advance, Michael _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.jpg Type: image/jpeg Size: 13188 bytes Desc: image001.jpg URL: From ahryciw at ualberta.ca Wed Apr 3 22:56:13 2019 From: ahryciw at ualberta.ca (Aaron Hryciw) Date: Wed, 3 Apr 2019 20:56:13 -0600 Subject: [labnetwork] Use of forming gas in cryo-pumped sputtering system In-Reply-To: References: Message-ID: Dear colleagues, Many thanks for your recommendations to ensure safe regeneration of a cryopump containing oxygen and hydrogen. We'll run some numbers to ensure we remain outside the flammability window for the hydrogen/oxygen mixture released during regen, and take other prudent precautions (no fast regen with heaters, venting purge gas to exhaust, etc.). Cheers, ? Aaron Aaron Hryciw, PhD, PEng Fabrication Group Manager University of Alberta - nanoFAB W1-060 ECERF Building 9107 - 116 Street Edmonton, Alberta Canada T6G 2V4 Ph: 780-940-7938 www.nanofab.ualberta.ca On Fri, Mar 15, 2019 at 10:12 AM Aaron Hryciw wrote: > Dear colleagues, > > Our open-access facility has a cryo-pumped, manual sputtering system > plumbed with argon, oxygen, and nitrogen, which is often used for reactive > sputtering (mostly oxides). One of our users has requested the addition of > forming gas (5% H? + balance Ar) to enable sputtering of *a*-Si:H / SiO? > multilayers, as described in this paper > . A > concern was raised, however, about the possibility of explosions in the > cryo during regeneration, as the frozen mixture of argon, oxygen, ozone, > and hydrogen is released as the pump is warmed up. > > Does anyone have experience with using forming gas in a cryo-pumped > system, and/or know of any measures that could be taken to ensure these > sputtering processes could be performed safely? Doing this on a system > equipped with a turbo pump would be better, but we are leery of putting a > turbo on a manual system, where users fairly routinely crash the cryo. As > always, any advice would be greatly appreciated. > > Many thanks. > > Cheers, > > ? Aaron > > > > Aaron Hryciw, PhD, PEng > > Fabrication Group Manager > > University of Alberta - nanoFAB > > W1-060 ECERF Building > > 9107 - 116 Street > > Edmonton, Alberta > > Canada T6G 2V4 Ph: 780-940-7938 > www.nanofab.ualberta.ca > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From sreevyas at gmail.com Thu Apr 4 01:41:48 2019 From: sreevyas at gmail.com (Srinivasa Reddy) Date: Thu, 4 Apr 2019 11:11:48 +0530 Subject: [labnetwork] Wafer specification requirement for RIE & DRIE cleaning recopies Message-ID: HI, I'm Srinivasa Reddy, Manger, Microfabrication Lab, Indian Institute of Technology, Madras, Chennai. This is regarding Wafers specifications for Dummy wafers for RIE & DRIE process. 1. Some times we stick *small prices* to f*ull 4 inch wafer* and do the etching process. Currently we are using *Prime Wafers* ( which costly) and I'm looking to replace with Mechanical grade or Test grade wafers. 2. We also do chamber cleaning runs with the wafers and this also consumes significant number of wafers. Here also want to replace the Prime wafer with Test or Mechanical grade wafer. I've doubt about the Bending/Warping or TTV or backside roughness of the wafer and It may lead to higher helium leak rate and process may abort. Could some one throw light on this issue Thanks & Regards Srinivasa Reddy Kuppireddi Project Manager Center for NEMS & Nano Photonics (CNNP) ESB 225, Dept. of Electrical Engineering Indian Institute of Technology(IIT) Madras Chennai-600036, Indian +91 44 2257 5493 (O) +91 789 326 8010(M) -------------- next part -------------- An HTML attachment was scrubbed... URL: From fabien at edgehogtech.com Thu Apr 4 08:03:50 2019 From: fabien at edgehogtech.com (Fabien Dauzou) Date: Thu, 4 Apr 2019 12:03:50 +0000 Subject: [labnetwork] Wafer specification requirement for RIE & DRIE cleaning recopies In-Reply-To: References: Message-ID: Hi Srinivasa, In the past we have been using alumina wafer carrier [1-2mm] to proceed with cleaning of RIE and DRIE. You can also use standard wafer with a photoresist or certain coating (SiO2, Cr?) to avoid wafer consumption. It should be fine with the helium backside cooling. Best regards, Bien cordialement, Fabien Dauzou (Jr. Eng.) R&D Process Engineer fabien at edgehogtech.com Mob: 438-868-1657 https://www.edgehogtech.com/ [cid:image002.png at 01D4EABC.F20322B0] 780 Av. Brewster, Montreal, QC, Canada, H4C 2K1 Think green, before printing this email. From: labnetwork-bounces at mtl.mit.edu On Behalf Of Srinivasa Reddy Sent: April 4, 2019 1:42 AM To: labnetwork at mtl.mit.edu Subject: [labnetwork] Wafer specification requirement for RIE & DRIE cleaning recopies HI, I'm Srinivasa Reddy, Manger, Microfabrication Lab, Indian Institute of Technology, Madras, Chennai. This is regarding Wafers specifications for Dummy wafers for RIE & DRIE process. 1. Some times we stick small prices to full 4 inch wafer and do the etching process. Currently we are using Prime Wafers ( which costly) and I'm looking to replace with Mechanical grade or Test grade wafers. 2. We also do chamber cleaning runs with the wafers and this also consumes significant number of wafers. Here also want to replace the Prime wafer with Test or Mechanical grade wafer. I've doubt about the Bending/Warping or TTV or backside roughness of the wafer and It may lead to higher helium leak rate and process may abort. Could some one throw light on this issue Thanks & Regards Srinivasa Reddy Kuppireddi Project Manager Center for NEMS & Nano Photonics (CNNP) ESB 225, Dept. of Electrical Engineering Indian Institute of Technology(IIT) Madras Chennai-600036, Indian +91 44 2257 5493 (O) +91 789 326 8010(M) -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image002.png Type: image/png Size: 62372 bytes Desc: image002.png URL: From shimonel at savion.huji.ac.il Thu Apr 4 08:43:41 2019 From: shimonel at savion.huji.ac.il (Shimon Eliav) Date: Thu, 4 Apr 2019 12:43:41 +0000 Subject: [labnetwork] Wafer specification requirement for RIE & DRIE cleaning recopies In-Reply-To: References: Message-ID: Hi Srinivasa, Answering your questions, following our experience: 1. We use Sapphire wafers as carriers. They have good heat conductance and can be used for many many times. 2. Also for cleaning we use a Sapphire wafer. They are more expensive than Si, but can be used indefinitely and provides a better cleaning process. Regards, Shimon The Hebrew University of Jerusalem The Unit for Nano Fabrication ISRAEL From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Srinivasa Reddy Sent: Thursday, 4 April 2019 8:42 To: labnetwork at mtl.mit.edu Subject: [labnetwork] Wafer specification requirement for RIE & DRIE cleaning recopies HI, I'm Srinivasa Reddy, Manger, Microfabrication Lab, Indian Institute of Technology, Madras, Chennai. This is regarding Wafers specifications for Dummy wafers for RIE & DRIE process. 1. Some times we stick small prices to full 4 inch wafer and do the etching process. Currently we are using Prime Wafers ( which costly) and I'm looking to replace with Mechanical grade or Test grade wafers. 2. We also do chamber cleaning runs with the wafers and this also consumes significant number of wafers. Here also want to replace the Prime wafer with Test or Mechanical grade wafer. I've doubt about the Bending/Warping or TTV or backside roughness of the wafer and It may lead to higher helium leak rate and process may abort. Could some one throw light on this issue Thanks & Regards Srinivasa Reddy Kuppireddi Project Manager Center for NEMS & Nano Photonics (CNNP) ESB 225, Dept. of Electrical Engineering Indian Institute of Technology(IIT) Madras Chennai-600036, Indian +91 44 2257 5493 (O) +91 789 326 8010(M) -------------- next part -------------- An HTML attachment was scrubbed... URL: From xklu at eng.ucsd.edu Thu Apr 4 15:38:10 2019 From: xklu at eng.ucsd.edu (Xuekun Lu) Date: Thu, 4 Apr 2019 12:38:10 -0700 Subject: [labnetwork] Wafer specification requirement for RIE & DRIE cleaning recopies In-Reply-To: References: Message-ID: Dear colleagues, I am sorry to borrow this thread to ask this question, but it is a related question. Please let me know if I should start a separate subject. We have an Oxford PlasmalabSystem 100 with ICP180. Whenever we use a insulating carrier wafer (fused silica wafer, or silicon wafer coated with thick SiO2 film), the DC bias reading would be zero. As everybody knows that this does not mean the sample is subject to zero bias, but in our case, it seems that the sample DOES subject to zero bias. The etch result will be more isotropic with very low etch rate. This is even more a problem when running SiO2 etch with CHF3/Ar plasma, because this process highly relies on DC bias (ion bombardment), we got almost no etching when using insulating carrier wafers. If we use silicon wafer as carrier, everything would be fine. For other owners of this machine, I am wondering if you have the same issue or it is just our machine. I had asked Oxford for this, but had not been able to get an explanation. Any input would be greatly appreciated! Thanks, Xuekun On Thu, Apr 4, 2019 at 9:58 AM Fabien Dauzou wrote: > Hi Srinivasa, > > > > In the past we have been using alumina wafer carrier [1-2mm] to proceed > with cleaning of RIE and DRIE. > > You can also use standard wafer with a photoresist or certain coating > (SiO2, Cr?) to avoid wafer consumption. It should be fine with the helium > backside cooling. > > > > Best regards, Bien cordialement, > > > > Fabien Dauzou (Jr. Eng.) > > R&D Process Engineer > > fabien at edgehogtech.com > > Mob: 438-868-1657 > > https://www.edgehogtech.com/ > > 780 Av. Brewster, Montreal, QC, Canada, H4C 2K1 > > Think green, before printing this email. > > > > > > > > *From:* labnetwork-bounces at mtl.mit.edu *On > Behalf Of *Srinivasa Reddy > *Sent:* April 4, 2019 1:42 AM > *To:* labnetwork at mtl.mit.edu > *Subject:* [labnetwork] Wafer specification requirement for RIE & DRIE > cleaning recopies > > > > HI, > > I'm Srinivasa Reddy, Manger, Microfabrication Lab, Indian Institute of > Technology, Madras, Chennai. > > This is regarding Wafers specifications for Dummy wafers for RIE & DRIE > process. > > 1. Some times we stick *small prices* to f*ull 4 inch wafer* and do the > etching process. > > Currently we are using *Prime Wafers* ( which costly) and I'm looking to > replace with Mechanical grade or Test grade wafers. > > 2. We also do chamber cleaning runs with the wafers and this also consumes > significant number of wafers. Here also want to replace the Prime wafer > with Test or Mechanical grade wafer. > > > > I've doubt about the Bending/Warping or TTV or backside roughness of the > wafer and It may lead to higher helium leak rate and process may abort. > > Could some one throw light on this issue > > > > > Thanks & Regards > > Srinivasa Reddy Kuppireddi > > Project Manager > > Center for NEMS & Nano Photonics (CNNP) > > ESB 225, Dept. of Electrical Engineering > > Indian Institute of Technology(IIT) Madras > > Chennai-600036, Indian > > +91 44 2257 5493 (O) > > +91 789 326 8010(M) > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > -- ---------------------------------------- Dr. Xuekun Lu University of California, San Diego Calit2 M/C 0436 9500 Gilman Drive La Jolla, CA 92093-0436 For Fedex Shipping: Dr. Xuekun Lu University of California, San Diego Atkinson Hall 5th Floor Front Desk 9500 Gilman Drive La Jolla, CA 92093 Phone: (858) 246-0411 Fax: (858) 246-0408 E-mail: xklu at ucsd.edu http://nano3.calit2.net/ -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image002.png Type: image/png Size: 62372 bytes Desc: not available URL: From vamsinittala at gmail.com Fri Apr 5 01:20:06 2019 From: vamsinittala at gmail.com (N P VAMSI KRISHNA) Date: Fri, 5 Apr 2019 10:50:06 +0530 Subject: [labnetwork] Wafer specification requirement for RIE & DRIE cleaning recopies In-Reply-To: References: Message-ID: Dear Dr. Xuekun Lu, I guess there may be a thick polymer deposition on the table (mechanical chuck). This polymer could be from C4F8. If someone used your tool for polymer depositions or if the plasma is turned on without a wafer on the mechanical chuck, this can happen. I suggest you may want to do a mild rub on the table (chuck) using IPA+DI water and see if there is any DC bias. Thanks & best regards, vamsi On Fri, Apr 5, 2019 at 5:25 AM Xuekun Lu wrote: > Dear colleagues, > > I am sorry to borrow this thread to ask this question, but it is a related > question. Please let me know if I should start a separate subject. > > We have an Oxford PlasmalabSystem 100 with ICP180. Whenever we use a > insulating carrier wafer (fused silica wafer, or silicon wafer coated with > thick SiO2 film), the DC bias reading would be zero. As everybody knows > that this does not mean the sample is subject to zero bias, but in our > case, it seems that the sample DOES subject to zero bias. The etch result > will be more isotropic with very low etch rate. This is even more a problem > when running SiO2 etch with CHF3/Ar plasma, because this process highly > relies on DC bias (ion bombardment), we got almost no etching when using > insulating carrier wafers. If we use silicon wafer as carrier, everything > would be fine. For other owners of this machine, I am wondering if you have > the same issue or it is just our machine. I had asked Oxford for this, but > had not been able to get an explanation. > > Any input would be greatly appreciated! > > Thanks, > Xuekun > > > On Thu, Apr 4, 2019 at 9:58 AM Fabien Dauzou > wrote: > >> Hi Srinivasa, >> >> >> >> In the past we have been using alumina wafer carrier [1-2mm] to proceed >> with cleaning of RIE and DRIE. >> >> You can also use standard wafer with a photoresist or certain coating >> (SiO2, Cr?) to avoid wafer consumption. It should be fine with the helium >> backside cooling. >> >> >> >> Best regards, Bien cordialement, >> >> >> >> Fabien Dauzou (Jr. Eng.) >> >> R&D Process Engineer >> >> fabien at edgehogtech.com >> >> Mob: 438-868-1657 >> >> https://www.edgehogtech.com/ >> >> 780 Av. Brewster, Montreal, QC, Canada, H4C 2K1 >> >> Think green, before printing this email. >> >> >> >> >> >> >> >> *From:* labnetwork-bounces at mtl.mit.edu *On >> Behalf Of *Srinivasa Reddy >> *Sent:* April 4, 2019 1:42 AM >> *To:* labnetwork at mtl.mit.edu >> *Subject:* [labnetwork] Wafer specification requirement for RIE & DRIE >> cleaning recopies >> >> >> >> HI, >> >> I'm Srinivasa Reddy, Manger, Microfabrication Lab, Indian Institute of >> Technology, Madras, Chennai. >> >> This is regarding Wafers specifications for Dummy wafers for RIE & DRIE >> process. >> >> 1. Some times we stick *small prices* to f*ull 4 inch wafer* and do the >> etching process. >> >> Currently we are using *Prime Wafers* ( which costly) and I'm looking to >> replace with Mechanical grade or Test grade wafers. >> >> 2. We also do chamber cleaning runs with the wafers and this also >> consumes significant number of wafers. Here also want to replace the Prime >> wafer with Test or Mechanical grade wafer. >> >> >> >> I've doubt about the Bending/Warping or TTV or backside roughness of the >> wafer and It may lead to higher helium leak rate and process may abort. >> >> Could some one throw light on this issue >> >> >> >> >> Thanks & Regards >> >> Srinivasa Reddy Kuppireddi >> >> Project Manager >> >> Center for NEMS & Nano Photonics (CNNP) >> >> ESB 225, Dept. of Electrical Engineering >> >> Indian Institute of Technology(IIT) Madras >> >> Chennai-600036, Indian >> >> +91 44 2257 5493 (O) >> >> +91 789 326 8010(M) >> _______________________________________________ >> labnetwork mailing list >> labnetwork at mtl.mit.edu >> https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork >> > > > -- > ---------------------------------------- > Dr. Xuekun Lu > > University of California, San Diego > Calit2 M/C0436 > 9500 Gilman Drive > La Jolla, CA 92093-0436 > > For Fedex Shipping: > Dr. Xuekun Lu > University of California, San Diego > Atkinson Hall 5th Floor Front Desk > 9500 Gilman Drive > La Jolla, CA 92093 > > Phone: (858) 246-0411 > Fax: (858) 246-0408 > E-mail: xklu at ucsd.edu > http://nano3.calit2.net/ > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > -- -- Thanks & Best Regards, ----------------- * Dr. N.P.Vamsi Krishna* 3D Heterogeneous Integration and System Scaling Lab, Center for Nano Science and Engineering (CeNSE), Indian Institute of Science(IISc), Bangalore. INDIA-560012 -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image002.png Type: image/png Size: 62372 bytes Desc: not available URL: From barrj at pitt.edu Fri Apr 5 10:27:45 2019 From: barrj at pitt.edu (Barr, Joanna Margaert) Date: Fri, 5 Apr 2019 14:27:45 +0000 Subject: [labnetwork] Position Opening - Technical Director NanoScale Facility Message-ID: Dear LabNetwork Members, The NanoScale Fabrication and Characterization Facility at the University of Pittsburgh would like to share the following opening with you. Information about our facility can be found at our website here: http://www.nano.pitt.edu/ Please feel free to forward to anyone that you believe may be interested. We will be happy to address any questions you may have as well, should you need any clarification. Applicants should submit electronically to PinseSearch at pitt.edu The application should include the following materials in PDF form: a curriculum vitae, a 1-2 page description of work/research experience in a cleanroom environment (as well as nanoscale characterization), and three letters of reference. Review of applications will begin on May 1, 2019 and continue until the position is filled. The below is extracted text from our posting, which can additionally be found at the following link: https://cfopitt.taleo.net/careersection/pitt_faculty_external/jobdetail.ftl?job=19001927&lang=en#.XHbvop5LqWU.link Thank you, ~Joanna ________________________________________________________________ Joanna Barr, Administrative Coordinator NanoScale Fabrication and Characterization Facility 3700 O'Hara St, Rm SB 60-63 | barrj at pitt.edu Desk: 412-624-8394 | Deliveries: 412-383-8001 Technical Director PINSE Swanson School of Engineering-RC - United States-Pennsylvania-Pittsburgh - (19001927) The Petersen Institute of Nanoscience and Engineering (PINSE) at the University of Pittsburgh seeks a Scientific/Technical Director to lead its nanoscale fabrication and characterization user facility (NFCF). As such, the Technical Director will be responsible for ensuring that the NFCF meets its mission of providing scientific/technical expertise and a first class clean room facility in support of users' research programs in nanoscience and engineering. This permanent, full-time research professor position is non-tenure stream (rank is dependent on qualifications and experience). Qualified applicants should submit their applications electronically to PinseSearch at pitt.edu. The application should include the following materials in PDF form: a curriculum vitae, a 1-2 page description of work/research experience in a cleanroom environment (as well as nanoscale characterization), and three letters of reference. Review of applications will begin on May 1, 2019 and continue until the position is filled. The University of Pittsburgh is an Affirmative Action/Equal Opportunity Employer and values equality of opportunity, human dignity and diversity. EEO/AA/M/F/Vets/Disabled Primary Duties - Elements The Technical Director will be responsible for the management, smooth operation, and development of the nanofabrication and characterization facility (NFCF).This includes the hiring, training and supervision of facility personnel; determining responsibilities of assigned staff positions to accomplish service and growth objectives; budget allocation of resources; billing for services rendered; establishing policies for effective operation of the facility; and assisting in securing funds for the expansion of PINSE/NFCF capabilities. The technical director is also expected to provide direct user support in lithography, thin film deposition, and processing technologies. The Technical Director will report directly to the Academic Director of PINSE and will be expected to manage the NFCF's scientific and support staff with the goals of (1) enhancing the strengths and visibility of existing multidisciplinary staff and user research programs; (2) identifying new directions that are strategically aligned with PINSE/NFCF mission; (3) enabling a world-class user program with an engaged, satisfied, and diverse user community; (4) promoting interactions with other programmatic Centers and user facilities; (5) interfacing effectively with the University of Pittsburgh educational programs in nanoscience and technology;; and (6) ensuring high standards in Environmental, Safety, and Health and quality assurance for all of the PINSE/NFCF's activities. Requirements & Minimum Qualifications -- Elements A Ph.D. degree in science or engineering and extensive experience and expertise in micro-nanofabrication technologies and materials characterization. Demonstrated experience in management and clean room experience. Enter qualifications Assignment Category Fulltime-Regular Application Process Please refer to job description. Campus Pittsburgh Required Attachments Other (see application process for details) -------------- next part -------------- An HTML attachment was scrubbed... URL: From codreanu at udel.edu Tue Apr 9 12:54:51 2019 From: codreanu at udel.edu (Iulian Codreanu) Date: Tue, 9 Apr 2019 12:54:51 -0400 Subject: [labnetwork] ITO deposition Message-ID: <86778cba-b514-ce74-89bb-b418d6d350ed@udel.edu> Dear Colleagues, We have received a number of requests to provide ITO deposition capabilities. We have a sputterer but are concerned with the low melting points for Indium and Tin.? I am under the impression that ITO needs a dedicated deposition system. What is your experience/advice? Thank you, Iulian -- iulian Codreanu, Ph.D. Director of Operations, Nanofabrication Facility University of Delaware Harker ISE Lab, Room 163 221 Academy Street Newark, DE 19716 302-831-2784 http://udnf.udel.edu From bgila at ufl.edu Tue Apr 9 16:14:20 2019 From: bgila at ufl.edu (Brent Gila) Date: Tue, 9 Apr 2019 16:14:20 -0400 Subject: [labnetwork] ITO deposition In-Reply-To: <86778cba-b514-ce74-89bb-b418d6d350ed@udel.edu> References: <86778cba-b514-ce74-89bb-b418d6d350ed@udel.edu> Message-ID: <8fe34a91-f048-b0d1-cff5-ad636d820e07@ufl.edu> Hello Iulian, We have sputtered ITO here in our multi-user sputter tool without any indium or tin issues.? However, there are some tricks to controlling the conductivity of the sputtered ITO and that involves dialing in just the right amount of O2 background in the system.? We would load the ITO target overnight and run the dep first thing the following morning to ensure a low O2 and H2O background.? Our tool is a KJL CMS 18 sputter tool and KJL was helpful in providing some starting points with the recipe.? We had to still tweak the recipe, but that is not uncommon. Best Regards, Brent -- Brent P. Gila, PhD. Director, Nanoscale Research Facility 1041 Center Drive University of Florida Gainesville, Florida 32611 Tel:352-273-2245 Fax:352-846-2877 email:bgila at ufl.edu On 4/9/2019 12:54 PM, Iulian Codreanu wrote: > Dear Colleagues, > > We have received a number of requests to provide ITO deposition > capabilities. We have a sputterer but are concerned with the low > melting points for Indium and Tin.? I am under the impression that ITO > needs a dedicated deposition system. What is your experience/advice? > > Thank you, > > Iulian > From fouad.karouta at anu.edu.au Tue Apr 9 19:18:11 2019 From: fouad.karouta at anu.edu.au (Fouad Karouta) Date: Tue, 9 Apr 2019 23:18:11 +0000 Subject: [labnetwork] ITO deposition In-Reply-To: <86778cba-b514-ce74-89bb-b418d6d350ed@udel.edu> References: <86778cba-b514-ce74-89bb-b418d6d350ed@udel.edu> Message-ID: Hi Julian, We do regularly use ITO in our sputter and we have no particular issues/concerns. We have users who use the target with an RF source and some with a DC source. We've tried originally ITO in an old e-beam evaporator but the layer wasn't conductive while the sputtered layer is conductive. Regards, Fouad ************************************* Manager ANFF ACT Node Australian National Fabrication Facility Research School of Physics and Engineering L. Huxley Building (#56), Mills Road, Room 4.02 Australian National University ACT 2601, Canberra, Australia Tel: + 61 2 6125 7174 Mob: + 61 451 046 412 Email: fouad.karouta at anu.edu.au http://anff-act.anu.edu.au/ -----Original Message----- From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Iulian Codreanu Sent: Wednesday, 10 April 2019 2:55 AM To: Fab Network Subject: [labnetwork] ITO deposition Dear Colleagues, We have received a number of requests to provide ITO deposition capabilities. We have a sputterer but are concerned with the low melting points for Indium and Tin.? I am under the impression that ITO needs a dedicated deposition system. What is your experience/advice? Thank you, Iulian -- iulian Codreanu, Ph.D. Director of Operations, Nanofabrication Facility University of Delaware Harker ISE Lab, Room 163 221 Academy Street Newark, DE 19716 302-831-2784 http://udnf.udel.edu _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork From fouad.karouta at anu.edu.au Tue Apr 9 19:33:53 2019 From: fouad.karouta at anu.edu.au (Fouad Karouta) Date: Tue, 9 Apr 2019 23:33:53 +0000 Subject: [labnetwork] Wafer specification requirement for RIE & DRIE cleaning recopies In-Reply-To: References: Message-ID: Dear Xuekun, In general DC bias reading is a reading and depends on machine configuration and used carrier wafer. We do use a quartz carrier wafer in our system (it has a metal coating on the backside as we have an electro-static chuck) and DC reading is quite low. Recently we switched to a sapphire carrier and we get etching. Note when you use a Si wafer (coated with oxide or not) you obtain different etch rate on small pieces related to the loading effect and diffusion of reactants (in case of sapphire) causing higher etch rate than with Si where reactants are consumed at the Si surface. As Vamsi said, cleaning process with O2 does not consume the sapphire. Regards, Fouad ************************************* Manager ANFF ACT Node Australian National Fabrication Facility Research School of Physics and Engineering L. Huxley Building (#56), Mills Road, Room 4.02 Australian National University ACT 2601, Canberra, Australia Tel: + 61 2 6125 7174 Mob: + 61 451 046 412 Email: fouad.karouta at anu.edu.au http://anff-act.anu.edu.au/ From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of N P VAMSI KRISHNA Sent: Friday, 5 April 2019 4:20 PM To: Xuekun Lu Cc: labnetwork at mtl.mit.edu Subject: Re: [labnetwork] Wafer specification requirement for RIE & DRIE cleaning recopies Dear Dr. Xuekun Lu, I guess there may be a thick polymer deposition on the table (mechanical chuck). This polymer could be from C4F8. If someone used your tool for polymer depositions or if the plasma is turned on without a wafer on the mechanical chuck, this can happen. I suggest you may want to do a mild rub on the table (chuck) using IPA+DI water and see if there is any DC bias. Thanks & best regards, vamsi On Fri, Apr 5, 2019 at 5:25 AM Xuekun Lu > wrote: Dear colleagues, I am sorry to borrow this thread to ask this question, but it is a related question. Please let me know if I should start a separate subject. We have an Oxford PlasmalabSystem 100 with ICP180. Whenever we use a insulating carrier wafer (fused silica wafer, or silicon wafer coated with thick SiO2 film), the DC bias reading would be zero. As everybody knows that this does not mean the sample is subject to zero bias, but in our case, it seems that the sample DOES subject to zero bias. The etch result will be more isotropic with very low etch rate. This is even more a problem when running SiO2 etch with CHF3/Ar plasma, because this process highly relies on DC bias (ion bombardment), we got almost no etching when using insulating carrier wafers. If we use silicon wafer as carrier, everything would be fine. For other owners of this machine, I am wondering if you have the same issue or it is just our machine. I had asked Oxford for this, but had not been able to get an explanation. Any input would be greatly appreciated! Thanks, Xuekun On Thu, Apr 4, 2019 at 9:58 AM Fabien Dauzou > wrote: Hi Srinivasa, In the past we have been using alumina wafer carrier [1-2mm] to proceed with cleaning of RIE and DRIE. You can also use standard wafer with a photoresist or certain coating (SiO2, Cr?) to avoid wafer consumption. It should be fine with the helium backside cooling. Best regards, Bien cordialement, Fabien Dauzou (Jr. Eng.) R&D Process Engineer fabien at edgehogtech.com Mob: 438-868-1657 https://www.edgehogtech.com/ [cid:image001.png at 01D4EF80.836EB530] 780 Av. Brewster, Montreal, QC, Canada, H4C 2K1 Think green, before printing this email. From: labnetwork-bounces at mtl.mit.edu > On Behalf Of Srinivasa Reddy Sent: April 4, 2019 1:42 AM To: labnetwork at mtl.mit.edu Subject: [labnetwork] Wafer specification requirement for RIE & DRIE cleaning recopies HI, I'm Srinivasa Reddy, Manger, Microfabrication Lab, Indian Institute of Technology, Madras, Chennai. This is regarding Wafers specifications for Dummy wafers for RIE & DRIE process. 1. Some times we stick small prices to full 4 inch wafer and do the etching process. Currently we are using Prime Wafers ( which costly) and I'm looking to replace with Mechanical grade or Test grade wafers. 2. We also do chamber cleaning runs with the wafers and this also consumes significant number of wafers. Here also want to replace the Prime wafer with Test or Mechanical grade wafer. I've doubt about the Bending/Warping or TTV or backside roughness of the wafer and It may lead to higher helium leak rate and process may abort. Could some one throw light on this issue Thanks & Regards Srinivasa Reddy Kuppireddi Project Manager Center for NEMS & Nano Photonics (CNNP) ESB 225, Dept. of Electrical Engineering Indian Institute of Technology(IIT) Madras Chennai-600036, Indian +91 44 2257 5493 (O) +91 789 326 8010(M) _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -- ---------------------------------------- Dr. Xuekun Lu University of California, San Diego Calit2 M/C0436 9500 Gilman Drive La Jolla, CA 92093-0436 For Fedex Shipping: Dr. Xuekun Lu University of California, San Diego Atkinson Hall 5th Floor Front Desk 9500 Gilman Drive La Jolla, CA 92093 Phone: (858) 246-0411 Fax: (858) 246-0408 E-mail: xklu at ucsd.edu http://nano3.calit2.net/ _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -- -- Thanks & Best Regards, ----------------- Dr. N.P.Vamsi Krishna 3D Heterogeneous Integration and System Scaling Lab, Center for Nano Science and Engineering (CeNSE), Indian Institute of Science(IISc), Bangalore. INDIA-560012 -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.png Type: image/png Size: 29560 bytes Desc: image001.png URL: From nnelsonfitzpatrick at uwaterloo.ca Wed Apr 10 09:29:03 2019 From: nnelsonfitzpatrick at uwaterloo.ca (Nathan Nelson - Fitzpatrick) Date: Wed, 10 Apr 2019 13:29:03 +0000 Subject: [labnetwork] ITO deposition In-Reply-To: <86778cba-b514-ce74-89bb-b418d6d350ed@udel.edu> References: <86778cba-b514-ce74-89bb-b418d6d350ed@udel.edu> Message-ID: Hi Iulian, We run an ITO deposition process in our loadlocked multi-user sputter tool, this was developed by one of our co-op students. We have a number of different deposition processes available in this tool and no observed problems caused by the ITO process. As Brent Gila mentioned, the presence of O2 and H2O has an effect on the properties of the ITO films. We noted that adding O2 in a reactive sputter process made the optical transmission better but also increased electrical resistivity. We settled on a room temperature or mildly heated RF sputter deposition of the ITO (with only Ar gas), followed up by a brief anneal in our RTP in an O2 environment to get the best combination of transmission and electrical conductivity. I would be happy to share our co-op's report offline if you would like a starting point for your process. Best, -Nathan -- Nathan Nelson-Fitzpatrick PhD Nanofabrication Process & Characterization Engineering Manager Quantum-Nano Fabrication and Characterization Facility (QNFCF) Office of Research University of Waterloo 200 University Avenue West, Waterloo, ON N2L 3G1 P: 519-888-4567 ext. 31796 C: 226-218-3206 https://fab.qnc.uwaterloo.ca ?On 2019-04-09, 4:03 PM, "labnetwork-bounces at mtl.mit.edu on behalf of Iulian Codreanu" wrote: Dear Colleagues, We have received a number of requests to provide ITO deposition capabilities. We have a sputterer but are concerned with the low melting points for Indium and Tin. I am under the impression that ITO needs a dedicated deposition system. What is your experience/advice? Thank you, Iulian -- iulian Codreanu, Ph.D. Director of Operations, Nanofabrication Facility University of Delaware Harker ISE Lab, Room 163 221 Academy Street Newark, DE 19716 302-831-2784 http://udnf.udel.edu _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork From julia.aebersold at louisville.edu Wed Apr 10 14:01:16 2019 From: julia.aebersold at louisville.edu (Aebersold,Julia W.) Date: Wed, 10 Apr 2019 18:01:16 +0000 Subject: [labnetwork] ITO deposition In-Reply-To: <8fe34a91-f048-b0d1-cff5-ad636d820e07@ufl.edu> References: <86778cba-b514-ce74-89bb-b418d6d350ed@udel.edu>, <8fe34a91-f048-b0d1-cff5-ad636d820e07@ufl.edu> Message-ID: Sometimes we will run the sample in our anneal furnace with O2 flowing if extra transparency and lower resistivity is needed. Cheers! Julia Aebersold, Ph.D. MNTC Cleanroom Manager University of Louisville 2210 South Brook Street Shumaker Research Building, Room 233 Louisville, KY 40292 (502) 852-1572 http://louisville.edu/micronano/ ________________________________ From: labnetwork-bounces at mtl.mit.edu on behalf of Brent Gila Sent: Tuesday, April 9, 2019 4:14:20 PM To: Iulian Codreanu Cc: labnetwork at mtl.mit.edu Subject: Re: [labnetwork] ITO deposition Hello Iulian, We have sputtered ITO here in our multi-user sputter tool without any indium or tin issues. However, there are some tricks to controlling the conductivity of the sputtered ITO and that involves dialing in just the right amount of O2 background in the system. We would load the ITO target overnight and run the dep first thing the following morning to ensure a low O2 and H2O background. Our tool is a KJL CMS 18 sputter tool and KJL was helpful in providing some starting points with the recipe. We had to still tweak the recipe, but that is not uncommon. Best Regards, Brent -- Brent P. Gila, PhD. Director, Nanoscale Research Facility 1041 Center Drive University of Florida Gainesville, Florida 32611 Tel:352-273-2245 Fax:352-846-2877 email:bgila at ufl.edu On 4/9/2019 12:54 PM, Iulian Codreanu wrote: > Dear Colleagues, > > We have received a number of requests to provide ITO deposition > capabilities. We have a sputterer but are concerned with the low > melting points for Indium and Tin. I am under the impression that ITO > needs a dedicated deposition system. What is your experience/advice? > > Thank you, > > Iulian > _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://urldefense.proofpoint.com/v2/url?u=https-3A__mtl.mit.edu_mailman_listinfo.cgi_labnetwork&d=DwIGaQ&c=OAG1LQNACBDguGvBeNj18Swhr9TMTjS-x4O_KuapPgY&r=l9C3cuOkWyGd6C0ye_FDTBHMFl4lPXPJztVHQPL_Bao&m=R8VLgtzFxhKKBctZR9_MbeCxFMOotulOC9zzqpPBDsU&s=4F17KB6_tPpJA7ld_DZuWWDliqJ8SZXKY7-9C1wFGuY&e= -------------- next part -------------- An HTML attachment was scrubbed... URL: From shimonel at savion.huji.ac.il Thu Apr 11 01:43:53 2019 From: shimonel at savion.huji.ac.il (Shimon Eliav) Date: Thu, 11 Apr 2019 05:43:53 +0000 Subject: [labnetwork] ITO deposition In-Reply-To: <86778cba-b514-ce74-89bb-b418d6d350ed@udel.edu> References: <86778cba-b514-ce74-89bb-b418d6d350ed@udel.edu> Message-ID: Hi Iulian, We have a multi target, multi user Sputtering System. We do ITO deposition with no problem. From our experience we recommend you "to go easy" on power (DC or RF) in order not to melt the Indium bonding to the Copper Back Plate or to crack the ITO target itself. Regards, Shimon The Hebrew University of Jerusalem The Unit for Nano Fabrication ISRAEL -----Original Message----- From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Iulian Codreanu Sent: Tuesday, 9 April 2019 19:55 To: Fab Network Subject: [labnetwork] ITO deposition Dear Colleagues, We have received a number of requests to provide ITO deposition capabilities. We have a sputterer but are concerned with the low melting points for Indium and Tin.? I am under the impression that ITO needs a dedicated deposition system. What is your experience/advice? Thank you, Iulian -- iulian Codreanu, Ph.D. Director of Operations, Nanofabrication Facility University of Delaware Harker ISE Lab, Room 163 221 Academy Street Newark, DE 19716 302-831-2784 http://udnf.udel.edu _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork From odc1n08 at soton.ac.uk Thu Apr 11 03:18:52 2019 From: odc1n08 at soton.ac.uk (Clark O.D.) Date: Thu, 11 Apr 2019 07:18:52 +0000 Subject: [labnetwork] ITO deposition In-Reply-To: References: <86778cba-b514-ce74-89bb-b418d6d350ed@udel.edu>, <8fe34a91-f048-b0d1-cff5-ad636d820e07@ufl.edu> Message-ID: We have had success also with Ar/O2 room temperature ion assisted e-beam depositions of ITO, resistivity was quite low and the user is happy. We have not conducted a full process space investigation though. Regards, Owain From: labnetwork-bounces at mtl.mit.edu On Behalf Of Aebersold,Julia W. Sent: 10 April 2019 19:01 To: Iulian Codreanu ; bgila at ufl.edu Cc: labnetwork at mtl.mit.edu Subject: Re: [labnetwork] ITO deposition Sometimes we will run the sample in our anneal furnace with O2 flowing if extra transparency and lower resistivity is needed. Cheers! Julia Aebersold, Ph.D. MNTC Cleanroom Manager University of Louisville 2210 South Brook Street Shumaker Research Building, Room 233 Louisville, KY 40292 (502) 852-1572 http://louisville.edu/micronano/ ________________________________ From: labnetwork-bounces at mtl.mit.edu > on behalf of Brent Gila > Sent: Tuesday, April 9, 2019 4:14:20 PM To: Iulian Codreanu Cc: labnetwork at mtl.mit.edu Subject: Re: [labnetwork] ITO deposition Hello Iulian, We have sputtered ITO here in our multi-user sputter tool without any indium or tin issues. However, there are some tricks to controlling the conductivity of the sputtered ITO and that involves dialing in just the right amount of O2 background in the system. We would load the ITO target overnight and run the dep first thing the following morning to ensure a low O2 and H2O background. Our tool is a KJL CMS 18 sputter tool and KJL was helpful in providing some starting points with the recipe. We had to still tweak the recipe, but that is not uncommon. Best Regards, Brent -- Brent P. Gila, PhD. Director, Nanoscale Research Facility 1041 Center Drive University of Florida Gainesville, Florida 32611 Tel:352-273-2245 Fax:352-846-2877 email:bgila at ufl.edu On 4/9/2019 12:54 PM, Iulian Codreanu wrote: > Dear Colleagues, > > We have received a number of requests to provide ITO deposition > capabilities. We have a sputterer but are concerned with the low > melting points for Indium and Tin. I am under the impression that ITO > needs a dedicated deposition system. What is your experience/advice? > > Thank you, > > Iulian > _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://urldefense.proofpoint.com/v2/url?u=https-3A__mtl.mit.edu_mailman_listinfo.cgi_labnetwork&d=DwIGaQ&c=OAG1LQNACBDguGvBeNj18Swhr9TMTjS-x4O_KuapPgY&r=l9C3cuOkWyGd6C0ye_FDTBHMFl4lPXPJztVHQPL_Bao&m=R8VLgtzFxhKKBctZR9_MbeCxFMOotulOC9zzqpPBDsU&s=4F17KB6_tPpJA7ld_DZuWWDliqJ8SZXKY7-9C1wFGuY&e= -------------- next part -------------- An HTML attachment was scrubbed... URL: From mwoonk at umich.edu Thu Apr 11 08:13:55 2019 From: mwoonk at umich.edu (Matthew Oonk) Date: Thu, 11 Apr 2019 08:13:55 -0400 Subject: [labnetwork] ITO deposition In-Reply-To: References: <86778cba-b514-ce74-89bb-b418d6d350ed@udel.edu> Message-ID: We are like everyone else: we regularly deposit ITO in a shared system (Lesker Lab-18 loadlock, 5 sources, turbo pumped tool.) The best "as-deposited" film in terms of transmission and resitivity is ~300C with a tiny bit of O2 (2-4%) Our sputter tool heats/cools so slowly that most users just do 2.5% at room temp and either anneal it (if their substrate allows) or live with the results as-deposited. We do DC but when I started up the tool 10 years ago I did RF and it was similar (our old sputter tool we did RF.) Any amount of annealing helps the film - even a hotplate at 180C can lower the resistivity. Ours is a tiny bit O2 rich so 450C + FG RTP was the best for us. -Matt Matthew Oonk Research Engineer Lurie Nanofabrication Facility University of Michigan 734-646-1275 mwoonk at umich.edu On Thu, Apr 11, 2019 at 7:45 AM Shimon Eliav wrote: > Hi Iulian, > > We have a multi target, multi user Sputtering System. We do ITO deposition > with no problem. > From our experience we recommend you "to go easy" on power (DC or RF) in > order not to melt the Indium bonding to the Copper Back Plate or to crack > the ITO target itself. > Regards, > > Shimon > The Hebrew University of Jerusalem > The Unit for Nano Fabrication > ISRAEL > > -----Original Message----- > From: labnetwork-bounces at mtl.mit.edu [mailto: > labnetwork-bounces at mtl.mit.edu] On Behalf Of Iulian Codreanu > Sent: Tuesday, 9 April 2019 19:55 > To: Fab Network > Subject: [labnetwork] ITO deposition > > Dear Colleagues, > > We have received a number of requests to provide ITO deposition > capabilities. We have a sputterer but are concerned with the low melting > points for Indium and Tin. I am under the impression that ITO needs a > dedicated deposition system. What is your experience/advice? > > Thank you, > > Iulian > > -- > iulian Codreanu, Ph.D. > Director of Operations, Nanofabrication Facility University of Delaware > Harker ISE Lab, Room 163 > 221 Academy Street > Newark, DE 19716 > 302-831-2784 > http://udnf.udel.edu > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > -------------- next part -------------- An HTML attachment was scrubbed... URL: From barrj at pitt.edu Thu Apr 11 10:27:48 2019 From: barrj at pitt.edu (Barr, Joanna Margaert) Date: Thu, 11 Apr 2019 14:27:48 +0000 Subject: [labnetwork] Position Opening - Technical Director NanoScale Facility Message-ID: Dear LabNetwork Members, I wanted to alert you to a revision in the posting for the Technical Director opening at Pinse NanoScale Fabrication and Characterization Facility, based on a suggestion from our community: Letters of Reference will not be required for initial application. The request for letters is now only requested of those selected as final candidates, not at time of initial application. We hope this will be of assistance in applicants consideration of the position we have open here at the University of Pittsburgh NanoScale Facility. Please feel free to distribute this announcement to any individuals that you believe may be interested to apply, and we will be happy to hear from anyone interested in the opening. The following link directs to our posting with revised language, and also I am providing the excerpt of the revised language here. https://cfopitt.taleo.net/careersection/pitt_faculty_external/jobdetail.ftl?job=19001927&lang=en#.XHbvop5LqWU.link Qualified applicants should submit their applications electronically to PinseSearch at pitt.edu. The application should include the following materials in PDF form: a curriculum vitae, a 1-2 page description of work/research experience in a cleanroom environment (as well as nanoscale characterization), and list of three references. If selected as a final candidate, three (3) letters of reference will be required. Review of applications will begin on May 1, 2019 and continue until the position is filled. Thank you for your consideration, and if you have any questions I'll be happy to help. Best Regards, ~Joanna ________________________________________________________________ Joanna Barr | NFCF | Desk: 412-624-8394 | Deliveries: 412-383-8001 | barrj at pitt.edu From: Barr, Joanna Margaert Sent: Friday, April 5, 2019 10:28 AM To: 'labnetwork at mtl.mit.edu' Subject: Position Opening - Technical Director NanoScale Facility Dear LabNetwork Members, The NanoScale Fabrication and Characterization Facility at the University of Pittsburgh would like to share the following opening with you. Information about our facility can be found at our website here: http://www.nano.pitt.edu/ Please feel free to forward to anyone that you believe may be interested. We will be happy to address any questions you may have as well, should you need any clarification. Applicants should submit electronically to PinseSearch at pitt.edu The application should include the following materials in PDF form: a curriculum vitae, a 1-2 page description of work/research experience in a cleanroom environment (as well as nanoscale characterization), and three letters of reference. Review of applications will begin on May 1, 2019 and continue until the position is filled. The below is extracted text from our posting, which can additionally be found at the following link: https://cfopitt.taleo.net/careersection/pitt_faculty_external/jobdetail.ftl?job=19001927&lang=en#.XHbvop5LqWU.link Thank you, ~Joanna ________________________________________________________________ Joanna Barr, Administrative Coordinator NanoScale Fabrication and Characterization Facility 3700 O'Hara St, Rm SB 60-63 | barrj at pitt.edu Desk: 412-624-8394 | Deliveries: 412-383-8001 Technical Director PINSE Swanson School of Engineering-RC - United States-Pennsylvania-Pittsburgh - (19001927) The Petersen Institute of Nanoscience and Engineering (PINSE) at the University of Pittsburgh seeks a Scientific/Technical Director to lead its nanoscale fabrication and characterization user facility (NFCF). As such, the Technical Director will be responsible for ensuring that the NFCF meets its mission of providing scientific/technical expertise and a first class clean room facility in support of users' research programs in nanoscience and engineering. This permanent, full-time research professor position is non-tenure stream (rank is dependent on qualifications and experience). Qualified applicants should submit their applications electronically to PinseSearch at pitt.edu. The application should include the following materials in PDF form: a curriculum vitae, a 1-2 page description of work/research experience in a cleanroom environment (as well as nanoscale characterization), and three letters of reference. Review of applications will begin on May 1, 2019 and continue until the position is filled. The University of Pittsburgh is an Affirmative Action/Equal Opportunity Employer and values equality of opportunity, human dignity and diversity. EEO/AA/M/F/Vets/Disabled Primary Duties - Elements The Technical Director will be responsible for the management, smooth operation, and development of the nanofabrication and characterization facility (NFCF).This includes the hiring, training and supervision of facility personnel; determining responsibilities of assigned staff positions to accomplish service and growth objectives; budget allocation of resources; billing for services rendered; establishing policies for effective operation of the facility; and assisting in securing funds for the expansion of PINSE/NFCF capabilities. The technical director is also expected to provide direct user support in lithography, thin film deposition, and processing technologies. The Technical Director will report directly to the Academic Director of PINSE and will be expected to manage the NFCF's scientific and support staff with the goals of (1) enhancing the strengths and visibility of existing multidisciplinary staff and user research programs; (2) identifying new directions that are strategically aligned with PINSE/NFCF mission; (3) enabling a world-class user program with an engaged, satisfied, and diverse user community; (4) promoting interactions with other programmatic Centers and user facilities; (5) interfacing effectively with the University of Pittsburgh educational programs in nanoscience and technology;; and (6) ensuring high standards in Environmental, Safety, and Health and quality assurance for all of the PINSE/NFCF's activities. Requirements & Minimum Qualifications -- Elements A Ph.D. degree in science or engineering and extensive experience and expertise in micro-nanofabrication technologies and materials characterization. Demonstrated experience in management and clean room experience. Enter qualifications Assignment Category Fulltime-Regular Application Process Please refer to job description. Campus Pittsburgh Required Attachments Other (see application process for details) -------------- next part -------------- An HTML attachment was scrubbed... URL: From jane.fitzpatrick at anff.org.au Tue Apr 16 19:25:13 2019 From: jane.fitzpatrick at anff.org.au (Jane Fitzpatrick) Date: Wed, 17 Apr 2019 09:25:13 +1000 Subject: [labnetwork] CEO vacancy - Australian National Fabrication Facility Message-ID: Hello, Just to let you all knwo that the ANFF has a vacancy for a CEO. The advert and PD can be found here if anyone is interested, http://www.brookerconsulting.com.au/positions.html. The closing date is the 23rd April. Kind regards Jane Jane Fitzpatrick, PhD Chief Operating Officer, ANFF Tel: +61 7 334 69360 Mob: +61 439 778 766 Web: www.anff.org.au Australian National Fabrication Facility CAI, Building 57 Research Road UQ, St Lucia, QLD 4072 This email (and any attachments) is intended for the addressee named and may contain privileged/confidential information. If you are not the intended recipient, please notify the sender and delete the message and attachments immediately and be advised that its use, disclosure or copying is unauthorised. The views expressed, unless you are otherwise advised, are those of the sender and not necessarily the views of the ANFF Ltd. -------------- next part -------------- An HTML attachment was scrubbed... URL: From barrj at pitt.edu Fri Apr 26 09:42:11 2019 From: barrj at pitt.edu (Barr, Joanna Margaert) Date: Fri, 26 Apr 2019 13:42:11 +0000 Subject: [labnetwork] Position Opening - Technical Director NanoScale Facility Message-ID: Dear Lab Network Members, On May 6th we will be holding our first applicant review committee meeting for the position opening of Technical Director of the NanoScale Fabrication and Characterization Facility for the Petersen Institute of NanoScience and Engineering (NFCF PINSE) for the University of Pittsburgh. If you are interested in applying to this position, please consider doing so prior to our meeting date for best consideration. Required elements of application are CV, letter of experience, and list of references. Application documents may be emailed to PinseSearch at pitt.edu. Further detail related to these document requirements is included in the posting text below. Our facility's website can be viewed here: http://www.nano.pitt.edu/ Our position posting can be viewed here: https://cfopitt.taleo.net/careersection/pitt_faculty_external/jobdetail.ftl?job=19001927&lang=en#.XHbvop5LqWU.link -------------------------------------------------------------------------------------------------------- Technical Director PINSE Swanson School of Engineering-RC - Pennsylvania-Pittsburgh - (19001927) Technical Director PINSE Swanson School of Engineering-RC - United States-Pennsylvania-Pittsburgh - (19001927) The Petersen Institute of Nanoscience and Engineering (PINSE) at the University of Pittsburgh seeks a Scientific/Technical Director to lead its nanofabrication and characterization user facility (NFCF). As such, the Technical Director will be responsible for ensuring that the NFCF meets its mission of providing scientific/technical expertise and a first class clean room facility in support of users' research programs in nanoscience and engineering. This permanent, full-time research professor position is non-tenure stream (rank is dependent on qualifications and experience). Qualified applicants should submit their applications electronically to PinseSearch at pitt.edu. The application should include the following materials in PDF form: a curriculum vitae, a 1-2 page description of work/research experience in a cleanroom environment (as well as nanoscale characterization), and list of three references. If selected as a final candidate, three (3) letters of reference will be required. Review of applications will begin on May 1, 2019 and continue until the position is filled. The University of Pittsburgh is an Affirmative Action/Equal Opportunity Employer and values equality of opportunity, human dignity and diversity. EEO/AA/M/F/Vets/Disabled Primary Duties - Elements The Technical Director will be responsible for the management, smooth operation, and development of the nanofabrication and characterization facility (NFCF).This includes the hiring, training and supervision of facility personnel; determining responsibilities of assigned staff positions to accomplish service and growth objectives; budget allocation of resources; billing for services rendered; establishing policies for effective operation of the facility; and assisting in securing funds for the expansion of PINSE/NFCF capabilities. The technical director is also expected to provide direct user support in lithography, thin film deposition, and processing technologies. The Technical Director will report directly to the Academic Director of PINSE and will be expected to manage the NFCF's scientific and support staff with the goals of (1) enhancing the strengths and visibility of existing multidisciplinary staff and user research programs; (2) identifying new directions that are strategically aligned with PINSE/NFCF mission; (3) enabling a world-class user program with an engaged, satisfied, and diverse user community; (4) promoting interactions with other programmatic Centers and user facilities; (5) interfacing effectively with the University of Pittsburgh educational programs in nanoscience and technology; and (6) ensuring high standards in Environmental, Safety, and Health and quality assurance for all of the PINSE/NFCF's activities. Requirements & Minimum Qualifications -- Elements A Ph.D. degree in science or engineering and extensive experience and expertise in micro-nanofabrication technologies and materials characterization. Demonstrated experience in management and clean room experience. Assignment Category Fulltime-Regular Application Process Please refer to job description. Campus Pittsburgh Required Attachments Other (see application process for details) ~Jo ________________________________________________________________ Joanna Barr | NFCF | Desk: 412-624-8394 | Deliveries: 412-383-8001 | barrj at pitt.edu From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Barr, Joanna Margaert Sent: Thursday, April 11, 2019 10:28 AM To: labnetwork at mtl.mit.edu Subject: Re: [labnetwork] Position Opening - Technical Director NanoScale Facility Dear LabNetwork Members, I wanted to alert you to a revision in the posting for the Technical Director opening at Pinse NanoScale Fabrication and Characterization Facility, based on a suggestion from our community: Letters of Reference will not be required for initial application. The request for letters is now only requested of those selected as final candidates, not at time of initial application. We hope this will be of assistance in applicants consideration of the position we have open here at the University of Pittsburgh NanoScale Facility. Please feel free to distribute this announcement to any individuals that you believe may be interested to apply, and we will be happy to hear from anyone interested in the opening. The following link directs to our posting with revised language, and also I am providing the excerpt of the revised language here. https://cfopitt.taleo.net/careersection/pitt_faculty_external/jobdetail.ftl?job=19001927&lang=en#.XHbvop5LqWU.link Qualified applicants should submit their applications electronically to PinseSearch at pitt.edu. The application should include the following materials in PDF form: a curriculum vitae, a 1-2 page description of work/research experience in a cleanroom environment (as well as nanoscale characterization), and list of three references. If selected as a final candidate, three (3) letters of reference will be required. Review of applications will begin on May 1, 2019 and continue until the position is filled. Thank you for your consideration, and if you have any questions I'll be happy to help. Best Regards, ~Joanna ________________________________________________________________ Joanna Barr | NFCF | Desk: 412-624-8394 | Deliveries: 412-383-8001 | barrj at pitt.edu From: Barr, Joanna Margaert Sent: Friday, April 5, 2019 10:28 AM To: 'labnetwork at mtl.mit.edu' > Subject: Position Opening - Technical Director NanoScale Facility Dear LabNetwork Members, The NanoScale Fabrication and Characterization Facility at the University of Pittsburgh would like to share the following opening with you. Information about our facility can be found at our website here: http://www.nano.pitt.edu/ Please feel free to forward to anyone that you believe may be interested. We will be happy to address any questions you may have as well, should you need any clarification. Applicants should submit electronically to PinseSearch at pitt.edu The application should include the following materials in PDF form: a curriculum vitae, a 1-2 page description of work/research experience in a cleanroom environment (as well as nanoscale characterization), and three letters of reference. Review of applications will begin on May 1, 2019 and continue until the position is filled. The below is extracted text from our posting, which can additionally be found at the following link: https://cfopitt.taleo.net/careersection/pitt_faculty_external/jobdetail.ftl?job=19001927&lang=en#.XHbvop5LqWU.link Thank you, ~Joanna ________________________________________________________________ Joanna Barr, Administrative Coordinator NanoScale Fabrication and Characterization Facility 3700 O'Hara St, Rm SB 60-63 | barrj at pitt.edu Desk: 412-624-8394 | Deliveries: 412-383-8001 Technical Director PINSE Swanson School of Engineering-RC - United States-Pennsylvania-Pittsburgh - (19001927) The Petersen Institute of Nanoscience and Engineering (PINSE) at the University of Pittsburgh seeks a Scientific/Technical Director to lead its nanoscale fabrication and characterization user facility (NFCF). As such, the Technical Director will be responsible for ensuring that the NFCF meets its mission of providing scientific/technical expertise and a first class clean room facility in support of users' research programs in nanoscience and engineering. This permanent, full-time research professor position is non-tenure stream (rank is dependent on qualifications and experience). Qualified applicants should submit their applications electronically to PinseSearch at pitt.edu. The application should include the following materials in PDF form: a curriculum vitae, a 1-2 page description of work/research experience in a cleanroom environment (as well as nanoscale characterization), and three letters of reference. Review of applications will begin on May 1, 2019 and continue until the position is filled. The University of Pittsburgh is an Affirmative Action/Equal Opportunity Employer and values equality of opportunity, human dignity and diversity. EEO/AA/M/F/Vets/Disabled Primary Duties - Elements The Technical Director will be responsible for the management, smooth operation, and development of the nanofabrication and characterization facility (NFCF).This includes the hiring, training and supervision of facility personnel; determining responsibilities of assigned staff positions to accomplish service and growth objectives; budget allocation of resources; billing for services rendered; establishing policies for effective operation of the facility; and assisting in securing funds for the expansion of PINSE/NFCF capabilities. The technical director is also expected to provide direct user support in lithography, thin film deposition, and processing technologies. The Technical Director will report directly to the Academic Director of PINSE and will be expected to manage the NFCF's scientific and support staff with the goals of (1) enhancing the strengths and visibility of existing multidisciplinary staff and user research programs; (2) identifying new directions that are strategically aligned with PINSE/NFCF mission; (3) enabling a world-class user program with an engaged, satisfied, and diverse user community; (4) promoting interactions with other programmatic Centers and user facilities; (5) interfacing effectively with the University of Pittsburgh educational programs in nanoscience and technology;; and (6) ensuring high standards in Environmental, Safety, and Health and quality assurance for all of the PINSE/NFCF's activities. Requirements & Minimum Qualifications -- Elements A Ph.D. degree in science or engineering and extensive experience and expertise in micro-nanofabrication technologies and materials characterization. Demonstrated experience in management and clean room experience. Enter qualifications Assignment Category Fulltime-Regular Application Process Please refer to job description. Campus Pittsburgh Required Attachments Other (see application process for details) -------------- next part -------------- An HTML attachment was scrubbed... URL: From na2661 at columbia.edu Fri Apr 26 11:10:59 2019 From: na2661 at columbia.edu (Nava Ariel-Sternberg) Date: Fri, 26 Apr 2019 11:10:59 -0400 Subject: [labnetwork] Position open - Columbia University Clean room In-Reply-To: <4E03D4FF-4958-4E29-A559-3EA16EFBF8DB@cornell.edu> Message-ID: <5cc31f86.1c69fb81.d0823.3610@mx.google.com> Dear all,Columbia Nano Initiative is seeking for a cleanroom engineer to come and work with us in the big apple. Experience of working in a cleanroom is required.?For more information and in order to apply go to:http://pa334.peopleadmin.com/postings/3033Thanks?NavaNava Ariel-Sternberg, Ph.D.Director of CNI labsColumbia UniversitySent from my Verizon, Samsung Galaxy smartphone -------------- next part -------------- An HTML attachment was scrubbed... URL: From michael.martin at louisville.edu Mon Apr 29 10:06:52 2019 From: michael.martin at louisville.edu (Martin,Michael David) Date: Mon, 29 Apr 2019 14:06:52 +0000 Subject: [labnetwork] Boat advice for semiconductor anneals Message-ID: Hi all, At U of L, we are considering switching to a non-quartz boat for our mixed use anneal furnace. In an effort to improve our semiconductor processing, we thought it might be better to have boats that do not let metal contamination diffuse so readily from the tube to the wafers. Initially, we thought that a nitride coated SiO2 would be ideal as the silicon nitride would act as a diffusion barrier. However, after spending some time looking on-line it looks like there are boats in SiC, Saphire, and silicon but I don't see any mention of SiN coated oxide. Do you have any recommendations for boat options in a mixed use anneal furnace? Eventually, I suppose we will just have to put in a semiconductor only anneal furnace. Regards, Michael -------------- next part -------------- An HTML attachment was scrubbed... URL: