From Aju.Jugessur at Colorado.EDU Wed Jan 2 13:10:38 2019 From: Aju.Jugessur at Colorado.EDU (Aju Jugessur) Date: Wed, 2 Jan 2019 18:10:38 +0000 Subject: [labnetwork] Core-Facilities Advisory Committee Message-ID: <427C7D12-986D-4482-A9CC-0CCFBD732551@colorado.edu> Hi all, I am reaching out to the labs in this network to find out if anyone has a generic document that they may want to share, on the terms for membership of an Advisory Committee that provide strategic guidance to Core labs in Nanofabrication and Characterization. I have created one from scratch but I wanted to obtain some more ideas on what may need to go in this document. The plan is to formalize the commitment and time/efforts by the advisory committee members by having this document for them to review. Any help on this will be much appreciated. Thanks, Regards Aju Aju Jugessur Ph.D. Director, Colorado Nanofabrication and Characterization Center Discovery Learning Center University of Colorado Boulder | College of Engineering & Applied Science 1111 Engineering Drive ? 1B09 DLC | Boulder, CO 80309-0422 | P: 303.735.5019| F: 303.492.2199 E-mail: aju.jugessur at colorado.edu [cid:clip_image002.jpg] Signature-Strengths: Focus, Activator, Futuristic, Strategic, Achiever (CliftonStrengths) -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: clip_image002.jpeg Type: image/jpeg Size: 5533 bytes Desc: clip_image002.jpeg URL: From uadithi at iisc.ac.in Fri Jan 4 00:54:57 2019 From: uadithi at iisc.ac.in (ADITHI U) Date: Fri, 4 Jan 2019 05:54:57 +0000 Subject: [labnetwork] Metallization on rough ceramic substrates Message-ID: Dear All, We are having difficulties in doing metal(Ti/Pt) lift off on ceramic substrates. Does any of you have experience on fabricating metal patterns on the rough Ceramic Substrates. Below are the details of the process done. The roughness of the ceramic substrates were approximately 400nm. We had used HMDS as adhesion promoter for lithography, the thickness of the Photoresist was ~ 1.5um.The thickness of the Ti/Pt layer was ~ 250nm. Immediately after lithography the deposition was done followed by 48 hours of lift off(Acetone) process. Ultrasonication(5-10mins) in Acetone was done after 48hours. Best Regards Adithi.U Senior Facility Technologist, National Nano Fabrication Centre, CeNSE, Indian Institute of Science Bangalore -------------- next part -------------- An HTML attachment was scrubbed... URL: From hit.kamble at gmail.com Fri Jan 4 08:51:35 2019 From: hit.kamble at gmail.com (Hitesh Kamble) Date: Fri, 4 Jan 2019 19:21:35 +0530 Subject: [labnetwork] Metallization on rough ceramic substrates In-Reply-To: References: Message-ID: Hello Adithi, In case of HMDS ,it will improve adhesion but resists will not remove easily from surafce.HMDS is mostly use in etching. Since you're having rough surface, Instead of HMDS use LOR 3B or say liftOFF resists which helps to improve liftoff process. Also for 250nm metallization you need more than 2um thick resists. We did not do this on ceramic samples exactly but successfully did liftoff on etched/textured glass and etched samples(roughness more than~400nm). Following are my suggestions: -Time Interval between litho and deposition should be lowest as possible - Dehydration at higher temp and for longer time. -LOR 3B coating at lower rpm and gradually increase rpm. -Keep sample in Remover PG and heat at 80C for 5min or more if metal not lifted,(Sonication not recquired in most cases) Thanks, Hitesh Kamble IITBNF-IIT Bombay On Fri 4 Jan, 2019, 6:08 PM ADITHI U Dear All, > > > We are having difficulties in doing metal(Ti/Pt) lift off on ceramic > substrates. Does any of you have experience on fabricating metal patterns > on the rough Ceramic Substrates. Below are the details of the process done. > > > The roughness of the ceramic substrates were approximately 400nm. We > had used HMDS as adhesion promoter for lithography, the thickness of the > Photoresist was ~ 1.5um.The thickness of the Ti/Pt layer was ~ 250nm. > Immediately after lithography the deposition was done followed by 48 hours > of lift off(Acetone) process. Ultrasonication(5-10mins) in Acetone was done > after 48hours. > > > *Best Regards* > > > > > > > *Adithi.USenior Facility Technologist,National Nano Fabrication Centre,CeNSE, Indian Institute of ScienceBangalore* > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > -------------- next part -------------- An HTML attachment was scrubbed... URL: From sangeethk9 at gmail.com Fri Jan 4 12:42:16 2019 From: sangeethk9 at gmail.com (sangeeth kallatt) Date: Fri, 4 Jan 2019 23:12:16 +0530 Subject: [labnetwork] Metallization on rough ceramic substrates In-Reply-To: References: Message-ID: Hi ADITHI, Could you please describe a little what exactly the problem is? Do you face delamination of metal? What is the technique used for deposition? On Fri, Jan 4, 2019 at 10:12 PM Hitesh Kamble wrote: > Hello Adithi, > In case of HMDS ,it will improve adhesion but resists will not remove > easily from surafce.HMDS is mostly use in etching. Since you're having > rough surface, Instead of HMDS use LOR 3B or say liftOFF resists which > helps to improve liftoff process. > Also for 250nm metallization you need more than 2um thick resists. > > We did not do this on ceramic samples exactly but successfully did liftoff > on etched/textured glass and etched samples(roughness more than~400nm). > Following are my suggestions: > -Time Interval between litho and deposition should be lowest as possible > - Dehydration at higher temp and for longer time. > -LOR 3B coating at lower rpm and gradually increase rpm. > -Keep sample in Remover PG and heat at 80C for 5min or more if metal not > lifted,(Sonication not recquired in most cases) > > > Thanks, > Hitesh Kamble > IITBNF-IIT Bombay > > > > On Fri 4 Jan, 2019, 6:08 PM ADITHI U >> Dear All, >> >> >> We are having difficulties in doing metal(Ti/Pt) lift off on >> ceramic substrates. Does any of you have experience on fabricating metal >> patterns on the rough Ceramic Substrates. Below are the details of the >> process done. >> >> >> The roughness of the ceramic substrates were approximately 400nm. We >> had used HMDS as adhesion promoter for lithography, the thickness of the >> Photoresist was ~ 1.5um.The thickness of the Ti/Pt layer was ~ 250nm. >> Immediately after lithography the deposition was done followed by 48 hours >> of lift off(Acetone) process. Ultrasonication(5-10mins) in Acetone was done >> after 48hours. >> >> >> *Best Regards* >> >> >> >> >> >> >> *Adithi.USenior Facility Technologist,National Nano Fabrication Centre,CeNSE, Indian Institute of ScienceBangalore* >> >> >> _______________________________________________ >> labnetwork mailing list >> labnetwork at mtl.mit.edu >> https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork >> > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > -- Sangeeth Kallatt -------------- next part -------------- An HTML attachment was scrubbed... URL: From sandrine at umich.edu Fri Jan 4 13:49:18 2019 From: sandrine at umich.edu (Sandrine Martin) Date: Fri, 4 Jan 2019 13:49:18 -0500 Subject: [labnetwork] Core-Facilities Advisory Committee In-Reply-To: <427C7D12-986D-4482-A9CC-0CCFBD732551@colorado.edu> References: <427C7D12-986D-4482-A9CC-0CCFBD732551@colorado.edu> Message-ID: Hello Aju, Here is what we have regarding our advisory Council at U Michigan LNF http://lnf-wiki.eecs.umich.edu/wiki/LNF_Council. Let me know if you have any question or want more details. Thanks Sandrine On Wed, Jan 2, 2019 at 4:12 PM Aju Jugessur wrote: > Hi all, > > I am reaching out to the labs in this network to find out if anyone has a > generic document that they may want to share, on the terms for membership > of an Advisory Committee that provide strategic guidance to Core labs in > Nanofabrication and Characterization. I have created one from scratch but I > wanted to obtain some more ideas on what may need to go in this document. > The plan is to formalize the commitment and time/efforts by the advisory > committee members by having this document for them to review. > > Any help on this will be much appreciated. > > Thanks, > Regards > Aju > > > Aju Jugessur Ph.D. > Director, Colorado Nanofabrication and Characterization Center > Discovery Learning Center > University of Colorado Boulder | College of Engineering & Applied Science > > 1111 Engineering Drive ? 1B09 DLC | Boulder, CO > 80309-0422 | P: 303.735.5019| F: 303.492.2199 > > E-mail: aju.jugessur at colorado.edu > > > > > > > Signature-Strengths: Focus, Activator, Futuristic, Strategic, Achiever > (CliftonStrengths) > > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > -- Sandrine Martin, Ph.D. University of Michigan LNF Managing Director 1246D EECS, 1301 Beal Ave Ann Arbor, MI 48109 Cell 734-277-2365 Fax 734-647-1781 www.LNF.umich.edu @LurieNanofab -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: clip_image002.jpeg Type: image/jpeg Size: 5533 bytes Desc: not available URL: From nclay at upenn.edu Fri Jan 4 14:16:50 2019 From: nclay at upenn.edu (Noah Clay) Date: Fri, 4 Jan 2019 14:16:50 -0500 Subject: [labnetwork] Metallization on rough ceramic substrates In-Reply-To: References: Message-ID: <95E37FB5-C122-4884-893F-E242840A46E3@upenn.edu> Hello Adithi, As you know, ceramics can be quite porous and metal adhesion can be diminished by surface/internally adsorbed water, organics, etc. Therefore, you may consider deep solvent cleaning, other surface treatments as appropriate (e.g., plasma) for your material and a lengthy dehydration bake prior to resist application. If pre-resist cleaning proves ineffective, then after resist development, you may consider O2 plasma or, if available, in-situ ion bombardment. Lastly, given the rough topography of your substrate, there may be undeveloped or underexposed pockets of resist on the substrate, which necessitate optimizing bake, exposure and develop conditions. As for HMDS (mainly used for Si), without knowing the type of ceramic you?re using, I can?t say that it will be effective as an adhesion promoter. I very humbly/respectfully disagree with previous comments that HMDS is used mostly for etching, but agree that to facilitate liftoff, a relatively thick LOR layer should be spun and baked before application of imaging resist. Best, Noah Clay Singh Center for Nanotechnology University of Pennsylvania Philadelphia, PA Sent from my iPhone > On Jan 4, 2019, at 08:51, Hitesh Kamble wrote: > > Hello Adithi, > In case of HMDS ,it will improve adhesion but resists will not remove easily from surafce.HMDS is mostly use in etching. Since you're having rough surface, Instead of HMDS use LOR 3B or say liftOFF resists which helps to improve liftoff process. > Also for 250nm metallization you need more than 2um thick resists. > > We did not do this on ceramic samples exactly but successfully did liftoff on etched/textured glass and etched samples(roughness more than~400nm). > Following are my suggestions: > -Time Interval between litho and deposition should be lowest as possible > - Dehydration at higher temp and for longer time. > -LOR 3B coating at lower rpm and gradually increase rpm. > -Keep sample in Remover PG and heat at 80C for 5min or more if metal not lifted,(Sonication not recquired in most cases) > > > Thanks, > Hitesh Kamble > IITBNF-IIT Bombay > > > >> On Fri 4 Jan, 2019, 6:08 PM ADITHI U > Dear All, >> >> We are having difficulties in doing metal(Ti/Pt) lift off on ceramic substrates. Does any of you have experience on fabricating metal patterns on the rough Ceramic Substrates. Below are the details of the process done. >> >> The roughness of the ceramic substrates were approximately 400nm. We had used HMDS as adhesion promoter for lithography, the thickness of the Photoresist was ~ 1.5um.The thickness of the Ti/Pt layer was ~ 250nm. Immediately after lithography the deposition was done followed by 48 hours of lift off(Acetone) process. Ultrasonication(5-10mins) in Acetone was done after 48hours. >> Best Regards >> >> >> Adithi.U >> Senior Facility Technologist, >> National Nano Fabrication Centre, >> CeNSE, Indian Institute of Science >> Bangalore >> >> _______________________________________________ >> labnetwork mailing list >> labnetwork at mtl.mit.edu >> https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From mondol at mit.edu Fri Jan 4 16:04:01 2019 From: mondol at mit.edu (Mark K Mondol) Date: Fri, 4 Jan 2019 16:04:01 -0500 Subject: [labnetwork] Metallization on rough ceramic substrates In-Reply-To: <95E37FB5-C122-4884-893F-E242840A46E3@upenn.edu> References: <95E37FB5-C122-4884-893F-E242840A46E3@upenn.edu> Message-ID: <6890cfa0-d113-7251-a896-d1c95167026a@mit.edu> I agree with Noah Clay, he identifies the issues correctly, in my view. I would add that a general rule of thumb for liftoff is to spin resist about 3X thicker than the metal layer you want to liftoff. Regards, Mark K Mondol On 1/4/2019 2:16 PM, Noah Clay wrote: > Hello Adithi, > > As you know, ceramics can be quite porous and metal adhesion can be > diminished by surface/internally adsorbed water, organics, etc. > Therefore, you may consider deep solvent cleaning, other surface > treatments as appropriate (e.g., plasma) for your material and a > lengthy dehydration bake prior to resist application. ?If pre-resist > cleaning proves ineffective, then after resist development, you may > consider O2 plasma or, if available, in-situ ion bombardment. ?Lastly, > given the rough topography of your substrate, there may be undeveloped > or underexposed pockets of resist on the substrate, which necessitate > optimizing bake, exposure and develop conditions. > > As for HMDS (mainly used for Si), without knowing the type of ceramic > you?re using, I can?t say that it will be effective as an adhesion > promoter. ?I very humbly/respectfully disagree with previous comments > that HMDS is used mostly for etching, but agree that?to facilitate > liftoff, a relatively thick LOR layer should be spun and baked before > application of imaging resist. > > Best, > Noah Clay > / > / > /Singh Center for Nanotechnology / > /University of Pennsylvania / > /Philadelphia, PA/ > > Sent from my iPhone > > On Jan 4, 2019, at 08:51, Hitesh Kamble > wrote: > >> Hello Adithi, >> ?In case of HMDS ,it will improve adhesion but resists will not >> remove easily from surafce.HMDS is mostly use in etching. Since >> you're having rough surface, Instead of HMDS use LOR 3B or say >> liftOFF resists which helps to improve liftoff process. >> Also for 250nm metallization you need more than 2um thick resists. >> >> We did not do this on ceramic samples exactly but successfully did >> liftoff on etched/textured glass and etched samples(roughness more >> than~400nm). >> Following are my suggestions: >> -Time Interval between litho and deposition should be lowest as possible >> - Dehydration at higher temp and for longer time. >> -LOR 3B coating at lower rpm and gradually increase rpm. >> -Keep sample in Remover PG and heat at 80C for 5min or more if metal >> not lifted,(Sonication not recquired in most cases) >> >> >> Thanks, >> Hitesh Kamble >> IITBNF-IIT Bombay >> >> >> >> On Fri 4 Jan, 2019, 6:08 PM ADITHI U > wrote: >> >> Dear All, >> >> >> ? ? ? We are having?difficulties in doing metal(Ti/Pt) lift >> off?on ceramic substrates. Does any of you have experience on >> fabricating metal patterns on the rough Ceramic Substrates. Below >> are the details of the process done. >> >> >> ? ?The roughness of the ceramic substrates were approximately >> 400nm. We had used HMDS?as adhesion promoter for lithography, the >> thickness of the Photoresist was ~ 1.5um.The thickness of the >> Ti/Pt layer was ~ 250nm. Immediately after lithography the >> deposition was done ?followed by 48 hours of lift off(Acetone) >> process. Ultrasonication(5-10mins) in Acetone was done after >> 48hours. >> >> *Best Regards* >> *Adithi.U Senior Facility Technologist, National Nano Fabrication >> Centre, CeNSE, Indian Institute of Science Bangalore* >> >> >> _______________________________________________ >> labnetwork mailing list >> labnetwork at mtl.mit.edu >> https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork >> >> _______________________________________________ >> labnetwork mailing list >> labnetwork at mtl.mit.edu >> https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -- Mark K Mondol Assistant Director NanoStructures Laboratory And Facility Manager Scanning Electron Beam Lithography Facility Bldg 36 Room 229 www.rle.mit.edu/sebl mondol at mit.edu office - 617-253-9617 cell - 617-224-8756 -------------- next part -------------- An HTML attachment was scrubbed... URL: From kamal.yadav at gmail.com Fri Jan 4 20:37:01 2019 From: kamal.yadav at gmail.com (Kamal Yadav) Date: Fri, 4 Jan 2019 20:37:01 -0500 Subject: [labnetwork] Metallization on rough ceramic substrates In-Reply-To: <6890cfa0-d113-7251-a896-d1c95167026a@mit.edu> References: <95E37FB5-C122-4884-893F-E242840A46E3@upenn.edu> <6890cfa0-d113-7251-a896-d1c95167026a@mit.edu> Message-ID: Dear Aditi, Are you observing undercut in your resist profile before you put metal. Without sufficient undercut [~ 1um] lift off would be challenging regardless of other issues. The total resist stack should be > 3X the metal you intend to deposit. If you are using LOR, the LOR thx should be > 1.4 times the metal thickness. Bilayer lithography [LOR + Imaging], is little better option for lift off, [however you can still do with single layer provided you have undercut]. The imaging resist to LOR thickness ratio is usually 3:1 or 4:1. I observed it to be a little more challenging in process with ratio of 1:1 or 1:2 as advertised in the LOR datasheets. Thanks, Kamal On Fri, Jan 4, 2019 at 7:52 PM Mark K Mondol wrote: > I agree with Noah Clay, he identifies the issues correctly, in my view. > > I would add that a general rule of thumb for liftoff is to spin resist > about 3X thicker than the metal layer you want to liftoff. > > Regards, > > Mark K Mondol > On 1/4/2019 2:16 PM, Noah Clay wrote: > > Hello Adithi, > > As you know, ceramics can be quite porous and metal adhesion can be > diminished by surface/internally adsorbed water, organics, etc. Therefore, > you may consider deep solvent cleaning, other surface treatments as > appropriate (e.g., plasma) for your material and a lengthy dehydration bake > prior to resist application. If pre-resist cleaning proves ineffective, > then after resist development, you may consider O2 plasma or, if available, > in-situ ion bombardment. Lastly, given the rough topography of your > substrate, there may be undeveloped or underexposed pockets of resist on > the substrate, which necessitate optimizing bake, exposure and develop > conditions. > > As for HMDS (mainly used for Si), without knowing the type of ceramic > you?re using, I can?t say that it will be effective as an adhesion > promoter. I very humbly/respectfully disagree with previous comments that > HMDS is used mostly for etching, but agree that to facilitate liftoff, a > relatively thick LOR layer should be spun and baked before application of > imaging resist. > > Best, > Noah Clay > > *Singh Center for Nanotechnology * > *University of Pennsylvania * > *Philadelphia, PA* > > Sent from my iPhone > > On Jan 4, 2019, at 08:51, Hitesh Kamble wrote: > > Hello Adithi, > In case of HMDS ,it will improve adhesion but resists will not remove > easily from surafce.HMDS is mostly use in etching. Since you're having > rough surface, Instead of HMDS use LOR 3B or say liftOFF resists which > helps to improve liftoff process. > Also for 250nm metallization you need more than 2um thick resists. > > We did not do this on ceramic samples exactly but successfully did liftoff > on etched/textured glass and etched samples(roughness more than~400nm). > Following are my suggestions: > -Time Interval between litho and deposition should be lowest as possible > - Dehydration at higher temp and for longer time. > -LOR 3B coating at lower rpm and gradually increase rpm. > -Keep sample in Remover PG and heat at 80C for 5min or more if metal not > lifted,(Sonication not recquired in most cases) > > > Thanks, > Hitesh Kamble > IITBNF-IIT Bombay > > > > On Fri 4 Jan, 2019, 6:08 PM ADITHI U >> Dear All, >> >> >> We are having difficulties in doing metal(Ti/Pt) lift off on >> ceramic substrates. Does any of you have experience on fabricating metal >> patterns on the rough Ceramic Substrates. Below are the details of the >> process done. >> >> >> The roughness of the ceramic substrates were approximately 400nm. We >> had used HMDS as adhesion promoter for lithography, the thickness of the >> Photoresist was ~ 1.5um.The thickness of the Ti/Pt layer was ~ 250nm. >> Immediately after lithography the deposition was done followed by 48 hours >> of lift off(Acetone) process. Ultrasonication(5-10mins) in Acetone was done >> after 48hours. >> >> *Best Regards >> * >> * >> >> Adithi.U >> Senior Facility Technologist, >> National Nano Fabrication Centre, >> CeNSE, Indian Institute of Science >> Bangalore* >> >> >> _______________________________________________ >> labnetwork mailing list >> labnetwork at mtl.mit.edu >> https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork >> > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > > > _______________________________________________ > labnetwork mailing listlabnetwork at mtl.mit.eduhttps://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > > -- > Mark K Mondol > Assistant Director NanoStructures Laboratory > And > Facility Manager > Scanning Electron Beam Lithography Facility > Bldg 36 Room 229www.rle.mit.edu/seblmondol at mit.edu > office - 617-253-9617 > cell - 617-224-8756 > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > -- Thanks, Kamal -------------- next part -------------- An HTML attachment was scrubbed... URL: From elliscd at auburn.edu Sat Jan 5 23:31:17 2019 From: elliscd at auburn.edu (Charles Ellis) Date: Sun, 6 Jan 2019 04:31:17 +0000 Subject: [labnetwork] Metallization on rough ceramic substrates In-Reply-To: References: <95E37FB5-C122-4884-893F-E242840A46E3@upenn.edu> <6890cfa0-d113-7251-a896-d1c95167026a@mit.edu>, Message-ID: <1546749076898.2569@auburn.edu> You did not say what problem you were having, is the photoresist not coming off? Probably getting too hot during metal dep- need to slow down dep rate. Is the deposited metal coming off as well? Need to plasma etch the ?open? area with a short O2 clean before deposition. Good luck.... Charles Ellis, retired Formally Auburn University Microlab Manager ________________________________ From: labnetwork-bounces at mtl.mit.edu on behalf of Kamal Yadav Sent: Friday, January 4, 2019 7:37:01 PM To: Mark K Mondol Cc: labnetwork at mtl.mit.edu Subject: Re: [labnetwork] Metallization on rough ceramic substrates Dear Aditi, Are you observing undercut in your resist profile before you put metal. Without sufficient undercut [~ 1um] lift off would be challenging regardless of other issues. The total resist stack should be > 3X the metal you intend to deposit. If you are using LOR, the LOR thx should be > 1.4 times the metal thickness. Bilayer lithography [LOR + Imaging], is little better option for lift off, [however you can still do with single layer provided you have undercut]. The imaging resist to LOR thickness ratio is usually 3:1 or 4:1. I observed it to be a little more challenging in process with ratio of 1:1 or 1:2 as advertised in the LOR datasheets. Thanks, Kamal On Fri, Jan 4, 2019 at 7:52 PM Mark K Mondol > wrote: I agree with Noah Clay, he identifies the issues correctly, in my view. I would add that a general rule of thumb for liftoff is to spin resist about 3X thicker than the metal layer you want to liftoff. Regards, Mark K Mondol On 1/4/2019 2:16 PM, Noah Clay wrote: Hello Adithi, As you know, ceramics can be quite porous and metal adhesion can be diminished by surface/internally adsorbed water, organics, etc. Therefore, you may consider deep solvent cleaning, other surface treatments as appropriate (e.g., plasma) for your material and a lengthy dehydration bake prior to resist application. If pre-resist cleaning proves ineffective, then after resist development, you may consider O2 plasma or, if available, in-situ ion bombardment. Lastly, given the rough topography of your substrate, there may be undeveloped or underexposed pockets of resist on the substrate, which necessitate optimizing bake, exposure and develop conditions. As for HMDS (mainly used for Si), without knowing the type of ceramic you?re using, I can?t say that it will be effective as an adhesion promoter. I very humbly/respectfully disagree with previous comments that HMDS is used mostly for etching, but agree that to facilitate liftoff, a relatively thick LOR layer should be spun and baked before application of imaging resist. Best, Noah Clay Singh Center for Nanotechnology University of Pennsylvania Philadelphia, PA Sent from my iPhone On Jan 4, 2019, at 08:51, Hitesh Kamble > wrote: Hello Adithi, In case of HMDS ,it will improve adhesion but resists will not remove easily from surafce.HMDS is mostly use in etching. Since you're having rough surface, Instead of HMDS use LOR 3B or say liftOFF resists which helps to improve liftoff process. Also for 250nm metallization you need more than 2um thick resists. We did not do this on ceramic samples exactly but successfully did liftoff on etched/textured glass and etched samples(roughness more than~400nm). Following are my suggestions: -Time Interval between litho and deposition should be lowest as possible - Dehydration at higher temp and for longer time. -LOR 3B coating at lower rpm and gradually increase rpm. -Keep sample in Remover PG and heat at 80C for 5min or more if metal not lifted,(Sonication not recquired in most cases) Thanks, Hitesh Kamble IITBNF-IIT Bombay On Fri 4 Jan, 2019, 6:08 PM ADITHI U wrote: Dear All, We are having difficulties in doing metal(Ti/Pt) lift off on ceramic substrates. Does any of you have experience on fabricating metal patterns on the rough Ceramic Substrates. Below are the details of the process done. The roughness of the ceramic substrates were approximately 400nm. We had used HMDS as adhesion promoter for lithography, the thickness of the Photoresist was ~ 1.5um.The thickness of the Ti/Pt layer was ~ 250nm. Immediately after lithography the deposition was done followed by 48 hours of lift off(Acetone) process. Ultrasonication(5-10mins) in Acetone was done after 48hours. Best Regards Adithi.U Senior Facility Technologist, National Nano Fabrication Centre, CeNSE, Indian Institute of Science Bangalore _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -- Mark K Mondol Assistant Director NanoStructures Laboratory And Facility Manager Scanning Electron Beam Lithography Facility Bldg 36 Room 229 www.rle.mit.edu/sebl mondol at mit.edu office - 617-253-9617 cell - 617-224-8756 _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -- Thanks, Kamal -------------- next part -------------- An HTML attachment was scrubbed... URL: From mdwyer87 at gmail.com Sun Jan 6 09:47:32 2019 From: mdwyer87 at gmail.com (mdwyer87 at gmail.com) Date: Sun, 6 Jan 2019 08:47:32 -0600 Subject: [labnetwork] Metallization on rough ceramic substrates In-Reply-To: <95E37FB5-C122-4884-893F-E242840A46E3@upenn.edu> References: <95E37FB5-C122-4884-893F-E242840A46E3@upenn.edu> Message-ID: <021d01d4a5ce$c22c5bc0$46851340$@gmail.com> Hi Adithi, In addition to the good advice already given, you might also consider thermal issues if your problem is the metal not lifting off. Evaporating Pt (especially up to 250 nm) can result in significant substrate heating, particularly if your samples are not heatsinked. I clamp my samples to a large block of aluminum flattened on a surface plate and that solved my thermal issues (along with sensible deposition rates). Matt Postdoc van der Weide Group UW-Madison From: labnetwork-bounces at mtl.mit.edu On Behalf Of Noah Clay Sent: Friday, January 4, 2019 1:17 PM To: ADITHI U Cc: labnetwork at mtl.mit.edu Subject: Re: [labnetwork] Metallization on rough ceramic substrates Hello Adithi, As you know, ceramics can be quite porous and metal adhesion can be diminished by surface/internally adsorbed water, organics, etc. Therefore, you may consider deep solvent cleaning, other surface treatments as appropriate (e.g., plasma) for your material and a lengthy dehydration bake prior to resist application. If pre-resist cleaning proves ineffective, then after resist development, you may consider O2 plasma or, if available, in-situ ion bombardment. Lastly, given the rough topography of your substrate, there may be undeveloped or underexposed pockets of resist on the substrate, which necessitate optimizing bake, exposure and develop conditions. As for HMDS (mainly used for Si), without knowing the type of ceramic you?re using, I can?t say that it will be effective as an adhesion promoter. I very humbly/respectfully disagree with previous comments that HMDS is used mostly for etching, but agree that to facilitate liftoff, a relatively thick LOR layer should be spun and baked before application of imaging resist. Best, Noah Clay Singh Center for Nanotechnology University of Pennsylvania Philadelphia, PA Sent from my iPhone On Jan 4, 2019, at 08:51, Hitesh Kamble > wrote: Hello Adithi, In case of HMDS ,it will improve adhesion but resists will not remove easily from surafce.HMDS is mostly use in etching. Since you're having rough surface, Instead of HMDS use LOR 3B or say liftOFF resists which helps to improve liftoff process. Also for 250nm metallization you need more than 2um thick resists. We did not do this on ceramic samples exactly but successfully did liftoff on etched/textured glass and etched samples(roughness more than~400nm). Following are my suggestions: -Time Interval between litho and deposition should be lowest as possible - Dehydration at higher temp and for longer time. -LOR 3B coating at lower rpm and gradually increase rpm. -Keep sample in Remover PG and heat at 80C for 5min or more if metal not lifted,(Sonication not recquired in most cases) Thanks, Hitesh Kamble IITBNF-IIT Bombay On Fri 4 Jan, 2019, 6:08 PM ADITHI U wrote: Dear All, We are having difficulties in doing metal(Ti/Pt) lift off on ceramic substrates. Does any of you have experience on fabricating metal patterns on the rough Ceramic Substrates. Below are the details of the process done. The roughness of the ceramic substrates were approximately 400nm. We had used HMDS as adhesion promoter for lithography, the thickness of the Photoresist was ~ 1.5um.The thickness of the Ti/Pt layer was ~ 250nm. Immediately after lithography the deposition was done followed by 48 hours of lift off(Acetone) process. Ultrasonication(5-10mins) in Acetone was done after 48hours. Best Regards Adithi.U Senior Facility Technologist, National Nano Fabrication Centre, CeNSE, Indian Institute of Science Bangalore _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From fouad.karouta at anu.edu.au Sun Jan 6 17:54:31 2019 From: fouad.karouta at anu.edu.au (Fouad Karouta) Date: Sun, 6 Jan 2019 22:54:31 +0000 Subject: [labnetwork] Metallization on rough ceramic substrates In-Reply-To: <021d01d4a5ce$c22c5bc0$46851340$@gmail.com> References: <95E37FB5-C122-4884-893F-E242840A46E3@upenn.edu> <021d01d4a5ce$c22c5bc0$46851340$@gmail.com> Message-ID: Hi Adithi, Adding to all other comments and in particular you need to pay attention to the profile of the photoresist: for a good lift-off you need some undercut. You didn?t mention the feature size of the metallisation pads but assuming it is more than 3 ?m in any dimension you may need to consider using a negative resist as the undercut can be tailored to your need using longer development time. We use maN 1420 (about 2 ?0m thick) for lift-off processes and that works fine. Regards, Fouad Karouta ************************************* Manager ANFF ACT Node Australian National Fabrication Facility Research School of Physics and Engineering L. Huxley Building (#56), Mills Road, Room 4.02 Australian National University ACT 2601, Canberra, Australia Tel: + 61 2 6125 7174 Mob: + 61 451 046 412 Email: fouad.karouta at anu.edu.au http://anff-act.anu.edu.au/ From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of mdwyer87 at gmail.com Sent: Monday, 7 January 2019 1:48 AM To: 'ADITHI U' Cc: labnetwork at mtl.mit.edu Subject: Re: [labnetwork] Metallization on rough ceramic substrates Hi Adithi, In addition to the good advice already given, you might also consider thermal issues if your problem is the metal not lifting off. Evaporating Pt (especially up to 250 nm) can result in significant substrate heating, particularly if your samples are not heatsinked. I clamp my samples to a large block of aluminum flattened on a surface plate and that solved my thermal issues (along with sensible deposition rates). Matt Postdoc van der Weide Group UW-Madison From: labnetwork-bounces at mtl.mit.edu > On Behalf Of Noah Clay Sent: Friday, January 4, 2019 1:17 PM To: ADITHI U > Cc: labnetwork at mtl.mit.edu Subject: Re: [labnetwork] Metallization on rough ceramic substrates Hello Adithi, As you know, ceramics can be quite porous and metal adhesion can be diminished by surface/internally adsorbed water, organics, etc. Therefore, you may consider deep solvent cleaning, other surface treatments as appropriate (e.g., plasma) for your material and a lengthy dehydration bake prior to resist application. If pre-resist cleaning proves ineffective, then after resist development, you may consider O2 plasma or, if available, in-situ ion bombardment. Lastly, given the rough topography of your substrate, there may be undeveloped or underexposed pockets of resist on the substrate, which necessitate optimizing bake, exposure and develop conditions. As for HMDS (mainly used for Si), without knowing the type of ceramic you?re using, I can?t say that it will be effective as an adhesion promoter. I very humbly/respectfully disagree with previous comments that HMDS is used mostly for etching, but agree that to facilitate liftoff, a relatively thick LOR layer should be spun and baked before application of imaging resist. Best, Noah Clay Singh Center for Nanotechnology University of Pennsylvania Philadelphia, PA Sent from my iPhone On Jan 4, 2019, at 08:51, Hitesh Kamble > wrote: Hello Adithi, In case of HMDS ,it will improve adhesion but resists will not remove easily from surafce.HMDS is mostly use in etching. Since you're having rough surface, Instead of HMDS use LOR 3B or say liftOFF resists which helps to improve liftoff process. Also for 250nm metallization you need more than 2um thick resists. We did not do this on ceramic samples exactly but successfully did liftoff on etched/textured glass and etched samples(roughness more than~400nm). Following are my suggestions: -Time Interval between litho and deposition should be lowest as possible - Dehydration at higher temp and for longer time. -LOR 3B coating at lower rpm and gradually increase rpm. -Keep sample in Remover PG and heat at 80C for 5min or more if metal not lifted,(Sonication not recquired in most cases) Thanks, Hitesh Kamble IITBNF-IIT Bombay On Fri 4 Jan, 2019, 6:08 PM ADITHI U wrote: Dear All, We are having difficulties in doing metal(Ti/Pt) lift off on ceramic substrates. Does any of you have experience on fabricating metal patterns on the rough Ceramic Substrates. Below are the details of the process done. The roughness of the ceramic substrates were approximately 400nm. We had used HMDS as adhesion promoter for lithography, the thickness of the Photoresist was ~ 1.5um.The thickness of the Ti/Pt layer was ~ 250nm. Immediately after lithography the deposition was done followed by 48 hours of lift off(Acetone) process. Ultrasonication(5-10mins) in Acetone was done after 48hours. Best Regards Adithi.U Senior Facility Technologist, National Nano Fabrication Centre, CeNSE, Indian Institute of Science Bangalore _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From codreanu at udel.edu Tue Jan 8 11:25:27 2019 From: codreanu at udel.edu (Iulian Codreanu) Date: Tue, 8 Jan 2019 11:25:27 -0500 Subject: [labnetwork] Silicon wafer doping service Message-ID: <7979a6c6-479e-fb9a-b8ea-3b4123d6cc9e@udel.edu> Hello, We are preparing for a fabrication class that aims to make solar cells. We are using solid sources for Phosphorous doping and am I preparing for Plan B in case we are not successful in time for the lab session of the class. I am looking to have p-type 4" wafers doped with Phosphorous. Does anyone offer this service? Thank you, Iulian -- iulian Codreanu, Ph.D. Director of Operations, Nanofabrication Facility University of Delaware Harker ISE Lab, Room 163 221 Academy Street Newark, DE 19716 302-831-2784 http://udnf.udel.edu From mpleil at unm.edu Tue Jan 8 12:30:52 2019 From: mpleil at unm.edu (Matthias Pleil) Date: Tue, 8 Jan 2019 17:30:52 +0000 Subject: [labnetwork] Silicon wafer doping service In-Reply-To: <7979a6c6-479e-fb9a-b8ea-3b4123d6cc9e@udel.edu> References: <7979a6c6-479e-fb9a-b8ea-3b4123d6cc9e@udel.edu> Message-ID: Try: https://www.universitywafer.com/ Your Silicon Wafer and wafer services | UniversityWafer,Inc. www.universitywafer.com Your leading silicon-wafer and services provider. Helping university research since 1997. Kind Regards, Matthias Pleil, Ph.D. Research Professor & Lecturer III of Mech. Eng - UNM UNM MTTC Cleanroom Manager PI - Southwest Center for Microsystems Education, Support Center for Microsystems Education scme-nm.org, scme-support.org (505)272-7157 ________________________________ From: labnetwork-bounces at mtl.mit.edu on behalf of Iulian Codreanu Sent: Tuesday, January 8, 2019 9:25:27 AM To: Fab Network Subject: [labnetwork] Silicon wafer doping service Hello, We are preparing for a fabrication class that aims to make solar cells. We are using solid sources for Phosphorous doping and am I preparing for Plan B in case we are not successful in time for the lab session of the class. I am looking to have p-type 4" wafers doped with Phosphorous. Does anyone offer this service? Thank you, Iulian -- iulian Codreanu, Ph.D. Director of Operations, Nanofabrication Facility University of Delaware Harker ISE Lab, Room 163 221 Academy Street Newark, DE 19716 302-831-2784 http://udnf.udel.edu _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From pilarhf at umich.edu Tue Jan 8 14:29:18 2019 From: pilarhf at umich.edu (Pilar Herrera-Fierro) Date: Tue, 8 Jan 2019 14:29:18 -0500 Subject: [labnetwork] Silicon wafer doping service In-Reply-To: <7979a6c6-479e-fb9a-b8ea-3b4123d6cc9e@udel.edu> References: <7979a6c6-479e-fb9a-b8ea-3b4123d6cc9e@udel.edu> Message-ID: Hello Iulian, This is Pilar from the Lurie Nanofabrication Facility at the University of Michigan (LNF). The U-M EECS department offers a Summer camp where students build a solar car. The students make the solar cell in the LNF clean room. We do have the furnace capabilities to do n (and p) doping on 4" wafers as well as any needed post processing (PSG removal, etc). As a matter of fact, we have characterized our doping quite extensively and we do offer shallow and deep doping processes. We would be happy to help you. Best, Pilar On Tue, Jan 8, 2019 at 12:22 PM Iulian Codreanu wrote: > Hello, > > We are preparing for a fabrication class that aims to make solar cells. > We are using solid sources for Phosphorous doping and am I preparing for > Plan B in case we are not successful in time for the lab session of the > class. > > I am looking to have p-type 4" wafers doped with Phosphorous. Does > anyone offer this service? > > Thank you, > > Iulian > > > -- > iulian Codreanu, Ph.D. > Director of Operations, Nanofabrication Facility > University of Delaware > Harker ISE Lab, Room 163 > 221 Academy Street > Newark, DE 19716 > 302-831-2784 > http://udnf.udel.edu > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > -- Pilar Herrera-Fierro, Ph.D. LNF User Services Director Lurie Nanofabrication Facility University of Michigan RM 1239 EECS Building 1301 Beal Ave. Ann Arbor, MI 48109-2122 *Cell* 734 646 1399 (734) 646 1399 www.lnf.umich.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From tobi at stanford.edu Wed Jan 9 23:15:29 2019 From: tobi at stanford.edu (Tobi Beetz) Date: Thu, 10 Jan 2019 04:15:29 +0000 Subject: [labnetwork] Jobs at Stanford Nano Shared Facilities: Electron Beam Lithography Manager & Lab Operations Engineer Message-ID: Dear All - we have 2 openings at SNSF. Please help us spread the word. Thanks, Tobi Electron Beam Lithography Manager The Stanford Nano Shared Facilities (SNSF) is seeking an Electron Beam Lithography (EBL) scientist to lead the operations of the facilities' Raith 150 EBL system, located at the Stanford Nanofabrication Facility (SNF), lead the operations of a new EBL system, as well as assist with the JEOL 6300FS EBL system, both located at SNSF. The successful candidate will manage the day-to-day operations, and maintenance of the instruments. S(he) will provide training and support to researchers, develop and implement advanced techniques and also be involved in planning for upgrades and new equipment. The EBL manager will report to the Associate Director of SNSF. More information and application portal: https://careersearch.stanford.edu/jobs/electron-beam-lithography-manager-4055 Lab Operations Engineer The Stanford Nano Shared Facilities (SNSF) is seeking a Lab Operations Engineer to support research operations within the Stanford Nanopatterning Cleanroom. The successful candidate will manage the day-to-day operations, and maintenance of a number of fabrication and characterization instruments with the cleanroom. S(he) will provide training and support to researchers, develop and implement advanced techniques and also be involved in planning for upgrades and new equipment. The Lab Operations Engineer will report to the Associate Director of SNSF. More information and application portal: https://careersearch.stanford.edu/jobs/lab-operations-engineer-5077 Tobi Tobi Beetz, Ph.D., Associate Director, Stanford Nano Shared Facilities, Stanford University 348 Via Pueblo, Spilker Building, Room 105, Stanford, CA 94305-4088, 650-644-9541, http://snsf.stanford.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From nclay at seas.upenn.edu Mon Jan 14 11:58:49 2019 From: nclay at seas.upenn.edu (Noah Clay) Date: Mon, 14 Jan 2019 11:58:49 -0500 Subject: [labnetwork] ENRIS 2019 @ University of Twente, June 16-18, 2019. Message-ID: Dear All, ENRIS 2019 (European Nanofabrication Research Infrastructure Symposium) will be held at the University of Twente, Enschede, the Netherlands, from June 16-18, 2019. https://www.enris2019.com The call for presentations is now open for the following topics: Processes: Control & quality, Standardization, Registration, Software development & control, Process data logging Emerging fabrication technologies: Quantum, Integrated photonics, Technology development Infrastructure: Lab design, Maintenance, Safety, Software & control, Energy, Vibration control, Sustainability, Re-use of chemicals, Quality of electricity supply Management: Marketing, Governance, Entrepreneurship, Ecosystems, Funding, IP, Knowhow Staff: Organization. Development, Training, Education For questions about the conference, please visit the web site or contact Gerard Roelofs: enris2019 at utwente.nl Kind regards, Noah Clay Noah Clay Director, Quattrone Nanofabrication Facility School of Engineering & Applied Science University of Pennsylvania Philadelphia, PA (215) 898-9308 nclay at upenn.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: ENRIS 2019.pdf Type: application/pdf Size: 100994 bytes Desc: not available URL: -------------- next part -------------- An HTML attachment was scrubbed... URL: From thieber at ksu.edu Tue Jan 15 13:20:52 2019 From: thieber at ksu.edu (Tyler Hieber) Date: Tue, 15 Jan 2019 18:20:52 +0000 Subject: [labnetwork] Pinholes in SiO2 from TMAH Etching Message-ID: Dear Colleagues, We have been attempting to etch Si SOI wafers in TMAH with an SiO2 mask that was wet grown. The wafer layer we are etching is 300 microns thick, the other Si layer is 40 microns thick and the mask is approximately 1.7 microns thick. We have noticed etch pit in the 40 micron side of the wafer (non-etched side) and originally thought that it was due to microbubbles in the photoresist that allowed BOE to reach the SiO2 layer during the pattern transfer step. We have since ruled this out since we did not submerge the wafer in BOE for pattern transfer this time. Regardless, we are still seeing obvious etch pits in what should have been a continuous SiO2 layer on the 40 micron side. If anyone has some experience with this phenomena, your assistance would be greatly appreciated. The best, Tyler J. Hieber Ph.D. Graduate Student Kansas State University Department of Mechanical and Nuclear Engineering thieber at ksu.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From p.kollensperger at ntnu.no Thu Jan 17 16:38:27 2019 From: p.kollensperger at ntnu.no (=?utf-8?B?UGV0ZXIgS8O2bGxlbnNwZXJnZXI=?=) Date: Thu, 17 Jan 2019 21:38:27 +0000 Subject: [labnetwork] Head of Laboratory at NTNU NanoLab Message-ID: We have an opening for the position as Head of Laboratory at NTNU NanoLab: https://www.jobbnorge.no/en/available-jobs/job/161996/head-of-laboratory If you?re interested in leading a growing lab with a great team at Norway?s top technical university make sure to apply before the deadline on January 21st. Do get in touch if you have any questions. Best regards, Peter ?????????????????????????????????????????????? Dr. Peter A. K?llensperger Director NTNU NanoLab Norwegian University of Science and Technology (NTNU) 7491 Trondheim Tel: +47 913 70 718 -------------- next part -------------- An HTML attachment was scrubbed... URL: From bob.geil at unc.edu Fri Jan 18 16:34:55 2019 From: bob.geil at unc.edu (Geil, Bob) Date: Fri, 18 Jan 2019 21:34:55 +0000 Subject: [labnetwork] SU8 processing: throughput advice Message-ID: Hey folks, I have done a lot of SU8 processing, but primarily on a small scale. We have received a request for a few hundred(!) SU8 molds (one layer, ~100um thick, same pattern). I'm looking for advice on increasing throughput by speeding up the various stages of the process. My current constraints are: 1) the mask design from the client is fixed (for now, at least); 2) the substrates must be 2" x 3" glass slides. A few ideas I already have in mind are: - apply the SU8 using SU-EX from DJ Laminates - buy an orbital shaker for the development step - change the mask design to accommodate more devices on a single substrate, then dice. - hire an undergrad Let me know your thoughts. Best, Bob Bob Geil, PhD Applied Physical Sciences ? UNC-CH 223 Chapman Hall, CB3216 (919) 843-6555 https://chanl.unc.edu/ [cid:b14021c9-b8c5-45fc-8715-44b651b13e60] -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: Outlook-ezoqxwoa.png Type: image/png Size: 5201 bytes Desc: Outlook-ezoqxwoa.png URL: From optotinker at yahoo.com Mon Jan 21 02:02:19 2019 From: optotinker at yahoo.com (Opto Tinker) Date: Mon, 21 Jan 2019 07:02:19 +0000 (UTC) Subject: [labnetwork] Manual User Guide for Shimadzu SPD-6A HPLC Detector References: <1837364696.890195.1548054139564.ref@mail.yahoo.com> Message-ID: <1837364696.890195.1548054139564@mail.yahoo.com> Hi, I contacted Shimadzu application support and they asked me for the product serial number that "starts with a letter followed by 11 digits, next to the Shimadzu logo". Mine only has 5 digits followed by "LP" below the logo, so they ignored me. I would appreciate any documentation on this unit. Can anyone give me a pointer? Thanks. From mweiler at andrew.cmu.edu Thu Jan 24 12:41:28 2019 From: mweiler at andrew.cmu.edu (Mark Weiler) Date: Thu, 24 Jan 2019 17:41:28 +0000 Subject: [labnetwork] MDC power supply, source controller and X-Y sweep manual Message-ID: <21D5AD71-5CDF-40E7-97D7-747C3D42EE96@andrew.cmu.edu> Hello Everyone, I am hoping to find someone in our network who has the manuals for the MDC e-Vap CVS electron beam 10kV power supply, the MDC e-Vap source controller and the MDC e-Vap x-y Programmable Sweep controller. Additionally, I do not have the output cabling for the e-Vap sweep controller and will need to fabricate them. I believe the Sweep Output cable connector was made by AMP (the rear bulkhead receptacle is AMP). Thanks in advance, Mark ________________________________________________________________ Mark Weiler Equipment & Facilites Manager Clair and John Bertucci Nanotechnology Laboratory Eden Hall Nanofabrication Cleanroom Carnegie Mellon University P: 412-268-2471 http://www.nanofab.ece.cmu.edu [cid:2D2E01E3-CEC1-4F48-A845-224D8D7CED12 at wv.cc.cmu.edu] -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: images.png Type: image/png Size: 720 bytes Desc: images.png URL: From rdevito at draper.com Thu Jan 24 16:05:21 2019 From: rdevito at draper.com (DeVito, Richard) Date: Thu, 24 Jan 2019 21:05:21 +0000 Subject: [labnetwork] MDC power supply, source controller and X-Y sweep manual In-Reply-To: <21D5AD71-5CDF-40E7-97D7-747C3D42EE96@andrew.cmu.edu> References: <21D5AD71-5CDF-40E7-97D7-747C3D42EE96@andrew.cmu.edu> Message-ID: <8190ddb7e8c24d2e826cd8f2522da6ea@draper.com> Call Dave Ferguson at http://www.islandebeam.com/ They used to make the MDC sources back when...he may be able to help Rich Devito From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Mark Weiler Sent: Thursday, January 24, 2019 12:41 PM To: Fab Network Subject: [labnetwork] MDC power supply, source controller and X-Y sweep manual Hello Everyone, I am hoping to find someone in our network who has the manuals for the MDC e-Vap CVS electron beam 10kV power supply, the MDC e-Vap source controller and the MDC e-Vap x-y Programmable Sweep controller. Additionally, I do not have the output cabling for the e-Vap sweep controller and will need to fabricate them. I believe the Sweep Output cable connector was made by AMP (the rear bulkhead receptacle is AMP). Thanks in advance, Mark ________________________________________________________________ Mark Weiler Equipment & Facilites Manager Clair and John Bertucci Nanotechnology Laboratory Eden Hall Nanofabrication Cleanroom Carnegie Mellon University P: 412-268-2471 http://www.nanofab.ece.cmu.edu [cid:image001.png at 01D4B3FE.9B05F130] ________________________________ Notice: This email and any attachments may contain proprietary (Draper non-public) and/or export-controlled information of Draper. If you are not the intended recipient of this email, please immediately notify the sender by replying to this email and immediately destroy all copies of this email. ________________________________ -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.png Type: image/png Size: 720 bytes Desc: image001.png URL: From John.Watson at microsoft.com Sun Jan 27 03:00:18 2019 From: John.Watson at microsoft.com (John Watson) Date: Sun, 27 Jan 2019 08:00:18 +0000 Subject: [labnetwork] Microsoft Quantum fabrication positions Message-ID: Dear colleagues, The Microsoft Quantum program currently has two job openings which may be of interest to this network. The first is Fabrication Process Integration Lead, and the second is Quantum Fabrication Engineer. The full job descriptions are available at the links below: https://careers.microsoft.com/us/en/job/577053/Fabrication-Process-Integration-Lead https://careers.microsoft.com/us/en/job/577477/Quantum-Fabrication-Engineer If you know of any candidates who may be interested in either of these postings, I would appreciate it if you would forward to them. Kind regards, John -- John Watson Researcher Microsoft Station Q, Delft Lorentzweg 1 2628CJ Delft The Netherlands +031-0654924465 john.watson at microsoft.com -------------- next part -------------- An HTML attachment was scrubbed... URL: From rjlad at maine.edu Tue Jan 29 16:27:42 2019 From: rjlad at maine.edu (Robert Lad) Date: Tue, 29 Jan 2019 16:27:42 -0500 Subject: [labnetwork] Tenured faculty opening at UMaine - Director of FIRST Message-ID: ______________________________________________________________ Open Tenured Faculty Position Director of the Frontier Institute for Research in Sensor Technologies (FIRST) University of Maine ______________________________________________________________ UMaine is currently carrying out a search for a tenured faculty member to be the Director of FIRST (Frontier Institute for Research in Sensor Technologies), which is new multidisciplinary research center involving several science and engineering disciplines. I want to make you aware of this opportunity and ask your help in identifying any of your colleagues who may be suited for the position. The job announcement including the application procedure is at *https://umaine.hiretouch.com/job-details?jobid=53164 * Feel free to contact me for additional information. ************************************************************* Robert J. Lad Professor of Physics Member, Frontier Institute for Research in Sensor Technologies (FIRST) University of Maine 5708 ESRB-Barrows Hall, Orono, ME 04469-5708 Phone:(207) 581-2257 rjlad at maine.edu ************************************************************* -------------- next part -------------- An HTML attachment was scrubbed... URL: From sguo18 at yorku.ca Wed Jan 30 14:04:46 2019 From: sguo18 at yorku.ca (Xin (Shane) Guo) Date: Wed, 30 Jan 2019 19:04:46 +0000 Subject: [labnetwork] Cost-recovery model Message-ID: Hi Colleagues, We are building a microfabrication lab (small scale, standard basic instruments such as ebeam, sputtering, RIE, PECVD, lithography tools, etc). We are trying to understand how each facility recovers their cost on supplies, labour, maintenance, etc. Is your annual user fee collected sufficient to cover all your expenses including salary payment of the lab manager? Does your institution or department subsidise your facility? What is your financial model? All suggestions are welcome, especially those from Canadian institutions. Cheers Shane -------------- next part -------------- An HTML attachment was scrubbed... URL: From fouad.karouta at anu.edu.au Wed Jan 30 17:13:26 2019 From: fouad.karouta at anu.edu.au (Fouad Karouta) Date: Wed, 30 Jan 2019 22:13:26 +0000 Subject: [labnetwork] TiB2 Message-ID: Dear all, We have a sputter system with a large choice of targets and we exchange targets regularly depending on requests. We have recently received a request to sputter TiB2. We couldn't find its SDS but that of TiB which shows some toxicity. Has anyone used TiB2 in a sputter system and any thoughts/concerns about safety and possible contamination of the system? Thanks, Fouad Karouta ************************************* Manager ANFF ACT Node Australian National Fabrication Facility Research School of Physics and Engineering L. Huxley Building (#56), Mills Road, Room 4.02 Australian National University ACT 2601, Canberra, Australia Tel: + 61 2 6125 7174 Mob: + 61 451 046 412 Email: fouad.karouta at anu.edu.au http://anff-act.anu.edu.au/ -------------- next part -------------- An HTML attachment was scrubbed... URL: From hower at umich.edu Wed Jan 30 17:18:06 2019 From: hower at umich.edu (Robert Hower) Date: Wed, 30 Jan 2019 17:18:06 -0500 Subject: [labnetwork] Cost-recovery model In-Reply-To: References: Message-ID: The paper we wrote is a good start. Hower R, Martin S, Grimard D. Comparison of Eight Academic Cost Models: A Detailed Study of User Costs, Impact on Laboratory Operations, User Behavior, and User Experience. Journal of the IEST, V. 58, No 1. 2015. > On Jan 30, 2019, at 2:04 PM, Xin (Shane) Guo wrote: > > Hi Colleagues, > > We are building a microfabrication lab (small scale, standard basic instruments such as ebeam, sputtering, RIE, PECVD, lithography tools, etc). > > We are trying to understand how each facility recovers their cost on supplies, labour, maintenance, etc. > > Is your annual user fee collected sufficient to cover all your expenses including salary payment of the lab manager? > > Does your institution or department subsidise your facility? What is your financial model? > > All suggestions are welcome, especially those from Canadian institutions. > > Cheers > > Shane > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From cekendri at mtu.edu Wed Jan 30 18:02:10 2019 From: cekendri at mtu.edu (Chito Kendrick) Date: Wed, 30 Jan 2019 18:02:10 -0500 Subject: [labnetwork] Cost-recovery model In-Reply-To: References: Message-ID: Hi Shane, I run a small microfab with the systems that you listed and a few analysis tools as well. Enough to do fabrication down to 1-2 um litho features , but nothing super fancy. The lab is also used for classes, I currently teach a microfabrication class on using the tools to make a photovoltaic cell that is way over engineered. I also have a faculty member using part of my facility running a lab on multiple layer PCB fabrication. The courses are used to train students, bring in some income, and get students aware of the facility to chase that research direction. We are currently in a research slump (people want sub-micron fabrication - but the cost would be to great for my user base) so recovering all costs just through use fees is not an option. We do get some funds from the VPR that we need to compete for with other shared facilities. I do external work for small companies and even a university in Canada, but it is still not enough to cover the bills - especially if something breaks. What our use fees cover are a percentage of my salary (1/3), a set supply list (basically anything the microfab class does not use it is not consider essential so users need to buy those supplies - there are a few supplies I keep that the class does not use but we have enough turn over to make it worth it), maintenance, repairs, and acquisition of new systems. We have some issues with setting use fees to represent actual costs per tool, as our accountants have set a $5000 min limit per use fee - therefore I have to bundle similar systems to get their use fee or bill only for supplies used. I am trying to resolve this and several have tried for awhile at my Michigan Tech University. Send me any questions if you have them. Regards, Chito Kendrick On 1/30/2019 2:04 PM, Xin (Shane) Guo wrote: > Hi Colleagues, > > We are building a microfabrication lab (small scale, standard basic > instruments such as ebeam, sputtering, RIE, PECVD, lithography tools, > etc). > > We are trying to understand how each facility recovers their cost on > supplies, labour, maintenance, etc. > > Is your annual user fee collected sufficient to cover all your > expenses including salary payment of the lab manager? > > Does your institution or department subsidise your facility? What is > your financial model? > > All suggestions are welcome, especially those from Canadian institutions. > > Cheers > > Shane > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -- Chito Kendrick Ph.D. Chito Kendrick Website MTU Microfabrication Website Managing Director of the Microfabrication Facility Research Assistant Professor Electrical and Computer Engineering Michigan Technological University Room 436 M&M Building 1400 Townsend Dr. Houghton, Michigan 49931-1295 814-308-4255 -------------- next part -------------- An HTML attachment was scrubbed... URL: From hengyuw at mit.edu Wed Jan 30 21:59:37 2019 From: hengyuw at mit.edu (Hengyu Wang) Date: Thu, 31 Jan 2019 02:59:37 +0000 Subject: [labnetwork] Composition of Mg/Au alloy Message-ID: Hi all, We are trying to deposit Mg to our substrate by Ebeam evaporator. But since Mg is reactive and maybe dangerous, we are thinking adding some Au to make it a stabilized alloy. The problem is that we have no experience on how much gold do we need to add into this alloy? Since what we really need is Mg, the lesser gold the better as long as it is stable and safe. Does anyone has any experience on this Mg/Au alloy? What composition of this alloy should be to make it stable? Thanks. Best regards, Hengyu -------------- next part -------------- An HTML attachment was scrubbed... URL: