From pfluegl at pendar.tech Fri Mar 1 10:01:04 2019 From: pfluegl at pendar.tech (Christian Pfluegl) Date: Fri, 1 Mar 2019 15:01:04 +0000 Subject: [labnetwork] heat load of MA6 mask aligner and Oxford RIE 80 Message-ID: Dear colleagues, We are planning to setup a Karl Suess MA6 maskaligner and a small Oxford RIE 80 in our facility. Does anyone know what the heat loads of those systems are (both idling and operating)? The Oxford manual says 1.5kW when idling but I am not sure how they arrive at such a high value when the RF is off. Thanks, Christian Dr. Christian Pfluegl Pendar Technologies LLC tel.: (857) 413-9339 www.pendartechnologies.com CONFIDENTIALITY NOTICE: This message contains confidential information and is intended only for the individual(s) addressed in the message. If you are not the named addressee, you should not disseminate, distribute, or copy this e-mail. If you are not the intended recipient, you are notified that disclosing, distributing, or copying this e-mail is strictly prohibited. -------------- next part -------------- An HTML attachment was scrubbed... URL: From M.G.Perry at soton.ac.uk Fri Mar 1 16:13:44 2019 From: M.G.Perry at soton.ac.uk (Perry M.G.) Date: Fri, 1 Mar 2019 21:13:44 +0000 Subject: [labnetwork] heat load of MA6 mask aligner and Oxford RIE 80 In-Reply-To: References: Message-ID: Hi Christian, Can you confirm age of RIE? At idle the PLC is the thing that kicks out the most heat. There's no other idle heat load i can think of and 1.5kw does seem a lot. regards Mike ________________________________ From: labnetwork-bounces at mtl.mit.edu on behalf of Christian Pfluegl Sent: 01 March 2019 15:01:04 To: labnetwork at mtl.mit.edu Subject: [labnetwork] heat load of MA6 mask aligner and Oxford RIE 80 Dear colleagues, We are planning to setup a Karl Suess MA6 maskaligner and a small Oxford RIE 80 in our facility. Does anyone know what the heat loads of those systems are (both idling and operating)? The Oxford manual says 1.5kW when idling but I am not sure how they arrive at such a high value when the RF is off. Thanks, Christian Dr. Christian Pfluegl Pendar Technologies LLC tel.: (857) 413-9339 www.pendartechnologies.com CONFIDENTIALITY NOTICE: This message contains confidential information and is intended only for the individual(s) addressed in the message. If you are not the named addressee, you should not disseminate, distribute, or copy this e-mail. If you are not the intended recipient, you are notified that disclosing, distributing, or copying this e-mail is strictly prohibited. -------------- next part -------------- An HTML attachment was scrubbed... URL: From M.G.Perry at soton.ac.uk Fri Mar 1 16:15:19 2019 From: M.G.Perry at soton.ac.uk (Perry M.G.) Date: Fri, 1 Mar 2019 21:15:19 +0000 Subject: [labnetwork] heat load of MA6 mask aligner and Oxford RIE 80 In-Reply-To: References: , Message-ID: (unless spec includes pump!) ________________________________ From: Perry M.G. Sent: 01 March 2019 21:13:44 To: Christian Pfluegl; labnetwork at mtl.mit.edu Subject: Re: heat load of MA6 mask aligner and Oxford RIE 80 Hi Christian, Can you confirm age of RIE? At idle the PLC is the thing that kicks out the most heat. There's no other idle heat load i can think of and 1.5kw does seem a lot. regards Mike ________________________________ From: labnetwork-bounces at mtl.mit.edu on behalf of Christian Pfluegl Sent: 01 March 2019 15:01:04 To: labnetwork at mtl.mit.edu Subject: [labnetwork] heat load of MA6 mask aligner and Oxford RIE 80 Dear colleagues, We are planning to setup a Karl Suess MA6 maskaligner and a small Oxford RIE 80 in our facility. Does anyone know what the heat loads of those systems are (both idling and operating)? The Oxford manual says 1.5kW when idling but I am not sure how they arrive at such a high value when the RF is off. Thanks, Christian Dr. Christian Pfluegl Pendar Technologies LLC tel.: (857) 413-9339 www.pendartechnologies.com CONFIDENTIALITY NOTICE: This message contains confidential information and is intended only for the individual(s) addressed in the message. If you are not the named addressee, you should not disseminate, distribute, or copy this e-mail. If you are not the intended recipient, you are notified that disclosing, distributing, or copying this e-mail is strictly prohibited. -------------- next part -------------- An HTML attachment was scrubbed... URL: From qleonard at wisc.edu Fri Mar 1 16:20:17 2019 From: qleonard at wisc.edu (Quinn Leonard) Date: Fri, 1 Mar 2019 21:20:17 +0000 Subject: [labnetwork] heat load of MA6 mask aligner and Oxford RIE 80 In-Reply-To: References: Message-ID: <29ad3b9c-72d4-28ae-22a2-54bee66e3363@wisc.edu> The installation requirements for our MA6 say, "max power requirement 2.5 kW (BA mode max 1 kW)". On 3/1/2019 9:01 AM, Christian Pfluegl wrote: Dear colleagues, We are planning to setup a Karl Suess MA6 maskaligner and a small Oxford RIE 80 in our facility. Does anyone know what the heat loads of those systems are (both idling and operating)? The Oxford manual says 1.5kW when idling but I am not sure how they arrive at such a high value when the RF is off. Thanks, Christian Dr. Christian Pfluegl Pendar Technologies LLC tel.: (857) 413-9339 www.pendartechnologies.com CONFIDENTIALITY NOTICE: This message contains confidential information and is intended only for the individual(s) addressed in the message. If you are not the named addressee, you should not disseminate, distribute, or copy this e-mail. If you are not the intended recipient, you are notified that disclosing, distributing, or copying this e-mail is strictly prohibited. _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -- Quinn Leonard Technical Staff Nanoscale Fabrication Center University of Wisconsin Room 3112 Engineering Centers Building 1550 Engineering Drive Madison, WI 53706 (608) 890-3030 qleonard at wisc.edu https://wcnt.wisc.edu/ -------------- next part -------------- An HTML attachment was scrubbed... URL: From JUC48 at pitt.edu Mon Mar 4 14:54:19 2019 From: JUC48 at pitt.edu (Chen, Jun) Date: Mon, 4 Mar 2019 19:54:19 +0000 Subject: [labnetwork] Position opening: Technical director PINSE (Peterson Institute of NanoScience and Engineering) at University of Pittsburgh Message-ID: The Petersen Institute of Nanoscience and Engineering (PINSE) at the University of Pittsburgh seeks a Scientific/Technical Director to lead its nanofabrication and characterization user facility (NFCF). As such, the Technical Director will be responsible for ensuring that the NFCF meets its mission of providing scientific/technical expertise and a first class clean room facility in support of users' research programs in nanoscience and engineering. This permanent, full-time research professor position is non-tenure stream (rank is dependent on qualifications and experience). Qualified applicants should submit their applications electronically to PinseSearch at pitt.edu. The application should include the following materials in PDF form: a curriculum vitae, a 1-2 page description of work/research experience in a cleanroom environment (as well as nanoscale characterization), and three letters of reference. Review of applications will begin on May 1, 2019 and continue until the position is filled. The University of Pittsburgh is an Affirmative Action/Equal Opportunity Employer and values equality of opportunity, human dignity and diversity. For more details, please go to the link: https://cfopitt.taleo.net/careersection/pitt_faculty_external/jobdetail.ftl?job=19001927&lang=en#.XHbvop5LqWU.link Jun Chen, Ph.D. Nanofabrication Scientist, NFCF Petersen Institute of NanoScience and Engineering, and Department of Electrical and Computer Engineering | University of Pittsburgh 3700 O'Hara Street, Pittsburgh, PA 15261 T: 412.383.3282 http://www.nano.pitt.edu/ -------------- next part -------------- An HTML attachment was scrubbed... URL: From kjvowen at lnf.umich.edu Tue Mar 5 09:05:41 2019 From: kjvowen at lnf.umich.edu (Kevin Owen) Date: Tue, 5 Mar 2019 09:05:41 -0500 Subject: [labnetwork] Source for Suss SB6 wafer bonder parts In-Reply-To: <02E5A928-7566-407E-87F7-2238BD63D4CA@cnsi.ucla.edu> References: <02E5A928-7566-407E-87F7-2238BD63D4CA@cnsi.ucla.edu> Message-ID: Adam, I've actually had reasonable luck dealing directy with Suss for our SB-6e. Their bonding group is actually located in the US (Vermont) and is pretty responsive. I'm sure you pay more for the parts (and I'm not sure how "far back" they go, if they'd have parts for your tool), but might be worth contacting them. TechSupportNA at suss.com -Kevin (P.S. The same can not be said for trying to get help with our ACS from their litho group in Germany...) On Tue, Feb 26, 2019 at 3:58 PM Stieg, Adam wrote: > Hi All, > > I would greatly appreciate any information on where we might be able to > source parts for our Suss bonder. The top-side heater has failed (twice) > and is not readily repairable due to the nature of the electrical > connection to the heating element. We have sourced this part through > ClassOne in the past via Germany but are having no luck this time. Any info > would great. > > Best, > Adam > > Adam Stieg Ph.D. > Associate Director > California NanoSystems Institute > UCLA > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > -- Kevin Owen Senior Engineer in Research Operations Group, Lurie Nanofabrication Facility University of Michigan (734) 545-4014 -------------- next part -------------- An HTML attachment was scrubbed... URL: From mweiler at andrew.cmu.edu Tue Mar 5 15:44:32 2019 From: mweiler at andrew.cmu.edu (Mark Weiler) Date: Tue, 5 Mar 2019 20:44:32 +0000 Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures Message-ID: Hello Everyone, We have gone through seven new lip seals purchased form Orbotech/SPTS. They are often failing before we even finish qualifying the system, or within a month thereafter. Our our process is stable with power and parameters not deviating over the past decade. However, I ordered the most recent batch of lip seals because the wafer seals we had been using were coming out with black residue after only a few runs? however, the current ones do the same. Not only have the lips seals disintegrated, but the chamber lid o-ring and bottom ceramic spool o-ring have also failed with black rubber material shedding off. It?s as if they are made of Buna and not meant for this application. Our process is typical Bosch with 100 sccm C4F8 and 20 sccm O2 for etching switching off with ~50 Sccm SF6 for passivation at a processing pressure of 15 mTorr, Coil power 600-800W, Platen power 100-150W, Bias voltage 50-100v (up to 200 peak-to-peak), Platen temp at 19 degrees, Lid temp 41 degrees. Qual wafers are new bare Silicon. Etch rates are normal and stable with 10+ years of data?. we just can?t complete the work due to failing seals. Our chamber base pressure is between 1E-8 and 5E-8 Torr each morning. When we put in a brand new seal and run only the LUR, it passes with 0.00 mTorr/minute leak rate. That jumps to 3.00 mTorr/m after only 30 minutes of the SPTS recommended O2 Clean? then rises as time and more runs progress. Wafers are coming out with black rings on their backsides. This should not be happening, and I believe it is due to incorrect material of the lip seals and o-rings. I am pinging the network, though, to see if there might be a parameter change we need to effect that may assist us. Have any of you seen this before? Best regards, Mark ________________________________________________________________ Mark Weiler Equipment & Facilites Manager Clair and John Bertucci Nanotechnology Laboratory Eden Hall Nanofabrication Cleanroom Carnegie Mellon University P: 412-268-2471 http://www.nanofab.ece.cmu.edu [cid:2D2E01E3-CEC1-4F48-A845-224D8D7CED12 at wv.cc.cmu.edu] -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: images.png Type: image/png Size: 720 bytes Desc: images.png URL: From mweiler at andrew.cmu.edu Tue Mar 5 19:04:59 2019 From: mweiler at andrew.cmu.edu (Mark Weiler) Date: Wed, 6 Mar 2019 00:04:59 +0000 Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures In-Reply-To: References: Message-ID: <69FD30F0-35D1-417C-8C07-5F70F5530F9F@andrew.cmu.edu> Correction... In my haste to write something up and get out the door I mixed up the gas is in the problem description. Our process is typical Bosch SF6 and O2 for etching .... switching off with C4F8 for passivation... Mark Mark Weiler Equipment & Facilities Manager Claire and John Bertucci Nanotechnology Laboratory Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.2471 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu On Mar 5, 2019, at 18:42, Mark Weiler > wrote: Hello Everyone, We have gone through seven new lip seals purchased form Orbotech/SPTS. They are often failing before we even finish qualifying the system, or within a month thereafter. Our our process is stable with power and parameters not deviating over the past decade. However, I ordered the most recent batch of lip seals because the wafer seals we had been using were coming out with black residue after only a few runs? however, the current ones do the same. Not only have the lips seals disintegrated, but the chamber lid o-ring and bottom ceramic spool o-ring have also failed with black rubber material shedding off. It?s as if they are made of Buna and not meant for this application. Our process is typical Bosch with 100 sccm C4F8 and 20 sccm O2 for etching switching off with ~50 Sccm SF6 for passivation at a processing pressure of 15 mTorr, Coil power 600-800W, Platen power 100-150W, Bias voltage 50-100v (up to 200 peak-to-peak), Platen temp at 19 degrees, Lid temp 41 degrees. Qual wafers are new bare Silicon. Etch rates are normal and stable with 10+ years of data?. we just can?t complete the work due to failing seals. Our chamber base pressure is between 1E-8 and 5E-8 Torr each morning. When we put in a brand new seal and run only the LUR, it passes with 0.00 mTorr/minute leak rate. That jumps to 3.00 mTorr/m after only 30 minutes of the SPTS recommended O2 Clean? then rises as time and more runs progress. Wafers are coming out with black rings on their backsides. This should not be happening, and I believe it is due to incorrect material of the lip seals and o-rings. I am pinging the network, though, to see if there might be a parameter change we need to effect that may assist us. Have any of you seen this before? Best regards, Mark ________________________________________________________________ Mark Weiler Equipment & Facilites Manager Clair and John Bertucci Nanotechnology Laboratory Eden Hall Nanofabrication Cleanroom Carnegie Mellon University P: 412-268-2471 http://www.nanofab.ece.cmu.edu [cid:2D2E01E3-CEC1-4F48-A845-224D8D7CED12 at wv.cc.cmu.edu] _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: images.png Type: image/png Size: 720 bytes Desc: images.png URL: From vamsinittala at gmail.com Tue Mar 5 20:25:38 2019 From: vamsinittala at gmail.com (N P VAMSI KRISHNA) Date: Wed, 6 Mar 2019 06:55:38 +0530 Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures In-Reply-To: <69FD30F0-35D1-417C-8C07-5F70F5530F9F@andrew.cmu.edu> References: <69FD30F0-35D1-417C-8C07-5F70F5530F9F@andrew.cmu.edu> Message-ID: Hi Mark Weiler, In my experience, the chamber O-rings should be Kalrez O-Rings, which can withstand very high temperatures (white color O-ring). I request you to check once if SPTS is supplying you the right one. Please check all the 4 chamber heaters (inner wall, chamber, and others) and confirm if the temperatures (~120 deg C) and the respective voltages are within the spec. Maybe one of the heaters is getting a higher voltage. Hope this helps. Thanks and best regards, vamsi On Wed, Mar 6, 2019 at 6:11 AM Mark Weiler wrote: > Correction... > > In my haste to write something up and get out the door I mixed up the gas > is in the problem description. > > Our process is typical Bosch SF6 and O2 for etching .... switching off > with C4F8 for passivation... > > Mark > > *Mark Weiler* > Equipment & Facilities Manager > Claire and John Bertucci Nanotechnology Laboratory > Electrical and Computer Engineering | Carnegie Mellon University > 5000 Forbes Ave., Pittsburgh, PA 15213-3890 > T: 412.268.2471 <412.268.5430> > F: 412.268.3497 > www.ece.cmu.edu > nanofab.ece.cmu.edu > > On Mar 5, 2019, at 18:42, Mark Weiler wrote: > > Hello Everyone, > > We have gone through seven new lip seals purchased form Orbotech/SPTS. > They are often failing before we even finish qualifying the system, or > within a month thereafter. > > Our our process is stable with power and parameters not deviating over the > past decade. However, I ordered the most recent batch of lip seals because > the wafer seals we had been using were coming out with black residue after > only a few runs? however, the current ones do the same. Not only have the > lips seals disintegrated, but the chamber lid o-ring and bottom ceramic > spool o-ring have also failed with black rubber material shedding off. > It?s as if they are made of Buna and not meant for this application. > > Our process is typical Bosch with 100 sccm C4F8 and 20 sccm O2 for etching > switching off with ~50 Sccm SF6 for passivation at a processing pressure of > 15 mTorr, Coil power 600-800W, Platen power 100-150W, Bias voltage 50-100v > (up to 200 peak-to-peak), Platen temp at 19 degrees, Lid temp 41 degrees. > Qual wafers are new bare Silicon. Etch rates are normal and stable with > 10+ years of data?. we just can?t complete the work due to failing seals. > > Our chamber base pressure is between 1E-8 and 5E-8 Torr each morning. > When we put in a brand new seal and run only the LUR, it passes with 0.00 > mTorr/minute leak rate. That jumps to 3.00 mTorr/m after only 30 minutes > of the SPTS recommended O2 Clean? then rises as time and more runs > progress. Wafers are coming out with black rings on their backsides. > > This should not be happening, and I believe it is due to incorrect > material of the lip seals and o-rings. I am pinging the network, though, > to see if there might be a parameter change we need to effect that may > assist us. > > Have any of you seen this before? > > Best regards, > > Mark > > > ________________________________________________________________ > > Mark Weiler > Equipment & Facilites Manager > Clair and John Bertucci Nanotechnology Laboratory > Eden Hall Nanofabrication Cleanroom > Carnegie Mellon University > P: 412-268-2471 > http://www.nanofab.ece.cmu.edu > > > > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > -- -- Thanks & Best Regards, ----------------- *N.P.Vamsi Krishna* 3D Heterogeneous Integration and System Scaling Lab, Center for Nano Science and Engineering (CeNSE), Indian Institute of Science(IISc), Bangalore. INDIA-560012 -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: images.png Type: image/png Size: 720 bytes Desc: not available URL: From roco at dtu.dk Wed Mar 6 02:30:02 2019 From: roco at dtu.dk (Roy Cork) Date: Wed, 6 Mar 2019 07:30:02 +0000 Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures In-Reply-To: <69FD30F0-35D1-417C-8C07-5F70F5530F9F@andrew.cmu.edu> References: <69FD30F0-35D1-417C-8C07-5F70F5530F9F@andrew.cmu.edu> Message-ID: <26b2846d16984b939c5f8ade9e7336a9@dtu.dk> Hi Mark, We (DTU Nanolab of Denmark) are not running the BOSCH process in our SPTS mechanically clamped ICP but we are etching III-V materials at elevated temperatures of up to 180?C on 100mm substrates. I would estimate that when the tool was initially installed the Viton lip seal would last for approximately 6 months and then become either brittle or etched and needed changing (HELUR became too high >15mT min). We were recommended by SPTS to change over to a new material called F70A which has a temperature range specified at -55?C to +225?C. The material is blue in colour and since the change we find our lip seals can easily last for one year or more. The black ring on the back of the wafer doesn?t sound too good. Some other things you should also look at is the flow of He and pressure, also the flow and cooling capacity of the chiller in case this is not the original that was shipped with the tool. If you need the part number from SPTS for the F70A 100mm lip seal I can dig it out for you, just let me know. Best regards Roy Cork From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Mark Weiler Sent: 6. marts 2019 01:05 To: Fab Network Subject: Re: [labnetwork] STS DRIE Multiplex Lip Seal failures Correction... In my haste to write something up and get out the door I mixed up the gas is in the problem description. Our process is typical Bosch SF6 and O2 for etching .... switching off with C4F8 for passivation... Mark Mark Weiler Equipment & Facilities Manager Claire and John Bertucci Nanotechnology Laboratory Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.2471 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu On Mar 5, 2019, at 18:42, Mark Weiler > wrote: Hello Everyone, We have gone through seven new lip seals purchased form Orbotech/SPTS. They are often failing before we even finish qualifying the system, or within a month thereafter. Our our process is stable with power and parameters not deviating over the past decade. However, I ordered the most recent batch of lip seals because the wafer seals we had been using were coming out with black residue after only a few runs? however, the current ones do the same. Not only have the lips seals disintegrated, but the chamber lid o-ring and bottom ceramic spool o-ring have also failed with black rubber material shedding off. It?s as if they are made of Buna and not meant for this application. Our process is typical Bosch with 100 sccm C4F8 and 20 sccm O2 for etching switching off with ~50 Sccm SF6 for passivation at a processing pressure of 15 mTorr, Coil power 600-800W, Platen power 100-150W, Bias voltage 50-100v (up to 200 peak-to-peak), Platen temp at 19 degrees, Lid temp 41 degrees. Qual wafers are new bare Silicon. Etch rates are normal and stable with 10+ years of data?. we just can?t complete the work due to failing seals. Our chamber base pressure is between 1E-8 and 5E-8 Torr each morning. When we put in a brand new seal and run only the LUR, it passes with 0.00 mTorr/minute leak rate. That jumps to 3.00 mTorr/m after only 30 minutes of the SPTS recommended O2 Clean? then rises as time and more runs progress. Wafers are coming out with black rings on their backsides. This should not be happening, and I believe it is due to incorrect material of the lip seals and o-rings. I am pinging the network, though, to see if there might be a parameter change we need to effect that may assist us. Have any of you seen this before? Best regards, Mark ________________________________________________________________ Mark Weiler Equipment & Facilites Manager Clair and John Bertucci Nanotechnology Laboratory Eden Hall Nanofabrication Cleanroom Carnegie Mellon University P: 412-268-2471 http://www.nanofab.ece.cmu.edu [cid:image001.png at 01D4D3F5.14205AE0] _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.png Type: image/png Size: 720 bytes Desc: image001.png URL: From dlafleur at cns.fas.harvard.edu Wed Mar 6 08:46:27 2019 From: dlafleur at cns.fas.harvard.edu (LaFleur, David W) Date: Wed, 6 Mar 2019 13:46:27 +0000 Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures Message-ID: <8395D872-145D-42D7-8D7D-558BAE91C048@cns.fas.harvard.edu> Hi Mark, We have an STS MP0579 ICP which uses the lip seals. It is used mostly for silicon and SiO2 etches with O2 cleans between uses. Most of our Bosch processes are run on SPTS Rapier which uses an ESC. That has its own set of issues. We find the lip seals don?t last more than 2-3 weeks in our system. Our chamber o-rings usually go for 2 months at best. I was thinking of changing to a kalrez o-ring and always wondered if they made a Kalrez lip seal. One suggestion on how to make them last longer is make sure they don?t get exposed to any solvents like Isopropyl when you are installing them. I want to say I am not happy with the longevity of the lip seals either and maybe we need to bring this to the attention of Orbotech/SPTS. Maybe they have a solution. Other than that they are good tools, very reliable, and heavily used here at Harvard. Because they are so heavily used with so many processes we find a biweekly chamber clean and lip seal replacement works well for everyone. This is why I have just lived with the lip seals as they are. Regards, David LaFleur Equipment Engineer CNS, Harvard University From: "labnetwork-bounces at mtl.mit.edu" on behalf of Mark Weiler Date: Tuesday, March 5, 2019 at 3:44 PM To: Fab Network Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures Hello Everyone, We have gone through seven new lip seals purchased form Orbotech/SPTS. They are often failing before we even finish qualifying the system, or within a month thereafter. Our our process is stable with power and parameters not deviating over the past decade. However, I ordered the most recent batch of lip seals because the wafer seals we had been using were coming out with black residue after only a few runs? however, the current ones do the same. Not only have the lips seals disintegrated, but the chamber lid o-ring and bottom ceramic spool o-ring have also failed with black rubber material shedding off. It?s as if they are made of Buna and not meant for this application. Our process is typical Bosch with 100 sccm C4F8 and 20 sccm O2 for etching switching off with ~50 Sccm SF6 for passivation at a processing pressure of 15 mTorr, Coil power 600-800W, Platen power 100-150W, Bias voltage 50-100v (up to 200 peak-to-peak), Platen temp at 19 degrees, Lid temp 41 degrees. Qual wafers are new bare Silicon. Etch rates are normal and stable with 10+ years of data?. we just can?t complete the work due to failing seals. Our chamber base pressure is between 1E-8 and 5E-8 Torr each morning. When we put in a brand new seal and run only the LUR, it passes with 0.00 mTorr/minute leak rate. That jumps to 3.00 mTorr/m after only 30 minutes of the SPTS recommended O2 Clean? then rises as time and more runs progress. Wafers are coming out with black rings on their backsides. This should not be happening, and I believe it is due to incorrect material of the lip seals and o-rings. I am pinging the network, though, to see if there might be a parameter change we need to effect that may assist us. Have any of you seen this before? Best regards, Mark ________________________________________________________________ Mark Weiler Equipment & Facilites Manager Clair and John Bertucci Nanotechnology Laboratory Eden Hall Nanofabrication Cleanroom Carnegie Mellon University P: 412-268-2471 http://www.nanofab.ece.cmu.edu [cid:image001.png at 01D4D3F9.24AA8760] -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.png Type: image/png Size: 721 bytes Desc: image001.png URL: From mweiler at andrew.cmu.edu Wed Mar 6 09:04:14 2019 From: mweiler at andrew.cmu.edu (Mark Weiler) Date: Wed, 6 Mar 2019 14:04:14 +0000 Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures In-Reply-To: <8395D872-145D-42D7-8D7D-558BAE91C048@cns.fas.harvard.edu> References: <8395D872-145D-42D7-8D7D-558BAE91C048@cns.fas.harvard.edu> Message-ID: <6181704F-4A5F-4A52-B386-7B6C505A5B1F@andrew.cmu.edu> Hi David, I am currently working with an elastomer manufacturer to produce O-Rings and seals for the systems of a material that can withstand better temperature ranges and chemical attacks. If you would like, I can share the information with you and maybe you can join us in this endeavor. The cost for the tooling and mold is now at ~1900 dollars, but I have negotiated the seal price to around 130.00 ea. I have not yet tested this material but we are having a seal made specifically for the Bosch process and 02 cleans. It is my believe that Orbotech has changed suppliers, or has allowed their supplier to switch their material source without testing, all in an effort to shave costs. My new efforts have also yielded a lower cost (50%) for the ceramic components in the chamber. I will test these and get back with the lab network sharing the source and part number. Thank you for sharing your info; now I know we are not the only ones ?feeling the pain? so to speak and can officially commiserate... LOL Best, Mark Mark Weiler Equipment & Facilities Manager Claire and John Bertucci Nanotechnology Laboratory Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.2471 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu On Mar 6, 2019, at 08:46, LaFleur, David W > wrote: Hi Mark, We have an STS MP0579 ICP which uses the lip seals. It is used mostly for silicon and SiO2 etches with O2 cleans between uses. Most of our Bosch processes are run on SPTS Rapier which uses an ESC. That has its own set of issues. We find the lip seals don?t last more than 2-3 weeks in our system. Our chamber o-rings usually go for 2 months at best. I was thinking of changing to a kalrez o-ring and always wondered if they made a Kalrez lip seal. One suggestion on how to make them last longer is make sure they don?t get exposed to any solvents like Isopropyl when you are installing them. I want to say I am not happy with the longevity of the lip seals either and maybe we need to bring this to the attention of Orbotech/SPTS. Maybe they have a solution. Other than that they are good tools, very reliable, and heavily used here at Harvard. Because they are so heavily used with so many processes we find a biweekly chamber clean and lip seal replacement works well for everyone. This is why I have just lived with the lip seals as they are. Regards, David LaFleur Equipment Engineer CNS, Harvard University From: "labnetwork-bounces at mtl.mit.edu" > on behalf of Mark Weiler > Date: Tuesday, March 5, 2019 at 3:44 PM To: Fab Network > Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures Hello Everyone, We have gone through seven new lip seals purchased form Orbotech/SPTS. They are often failing before we even finish qualifying the system, or within a month thereafter. Our our process is stable with power and parameters not deviating over the past decade. However, I ordered the most recent batch of lip seals because the wafer seals we had been using were coming out with black residue after only a few runs? however, the current ones do the same. Not only have the lips seals disintegrated, but the chamber lid o-ring and bottom ceramic spool o-ring have also failed with black rubber material shedding off. It?s as if they are made of Buna and not meant for this application. Our process is typical Bosch with 100 sccm C4F8 and 20 sccm O2 for etching switching off with ~50 Sccm SF6 for passivation at a processing pressure of 15 mTorr, Coil power 600-800W, Platen power 100-150W, Bias voltage 50-100v (up to 200 peak-to-peak), Platen temp at 19 degrees, Lid temp 41 degrees. Qual wafers are new bare Silicon. Etch rates are normal and stable with 10+ years of data?. we just can?t complete the work due to failing seals. Our chamber base pressure is between 1E-8 and 5E-8 Torr each morning. When we put in a brand new seal and run only the LUR, it passes with 0.00 mTorr/minute leak rate. That jumps to 3.00 mTorr/m after only 30 minutes of the SPTS recommended O2 Clean? then rises as time and more runs progress. Wafers are coming out with black rings on their backsides. This should not be happening, and I believe it is due to incorrect material of the lip seals and o-rings. I am pinging the network, though, to see if there might be a parameter change we need to effect that may assist us. Have any of you seen this before? Best regards, Mark ________________________________________________________________ Mark Weiler Equipment & Facilites Manager Clair and John Bertucci Nanotechnology Laboratory Eden Hall Nanofabrication Cleanroom Carnegie Mellon University P: 412-268-2471 http://www.nanofab.ece.cmu.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.png Type: image/png Size: 721 bytes Desc: image001.png URL: From dcchrist at wisc.edu Wed Mar 6 09:05:34 2019 From: dcchrist at wisc.edu (Daniel Christensen) Date: Wed, 6 Mar 2019 14:05:34 +0000 Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures In-Reply-To: References: Message-ID: Hi Mark, My etch staff person is out of the office or he would jump on this. He has been complaining about this to STS for a long time. We too at the Univ of Wisconsin have experienced a change in the behavior of our ASE STS lip seals. Our lip seals are for 100mm wafers. The change occurred a few (several?) years ago and is summarized below. I don?t know what happened ? if the seal vendor changed or the vendor had a material or manufacturing change but SOMETHING definitely changed. SPTS should just release the design of the lip seals to us and allow us to go and qualify a new vendor. The dang things cost >$200 apiece and sometimes don?t even last a dozen etches for us. Before * Lip seals delivered in a brown package * Lip seals lasted After * Lip seals delivered in plastic * Lip seals don?t last * Lip seals can be ?sticky? when first used. We had to institute a VERY short plasma on the lip seals without wafers present to ?un-sticky? them We have always had the chamber orings degrade and when you wipe the used ones the wipe is super black. we have always just changed them out when we open the chamber. This has not changed when the lip seal behavior changed. This isn?t as costly since we were able to determine the generic oring size. That is our experience, Dan Christensen Univ of Wisconsin-Madison From: labnetwork-bounces at mtl.mit.edu On Behalf Of Mark Weiler Sent: Tuesday, March 05, 2019 2:45 PM To: Fab Network Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures Hello Everyone, We have gone through seven new lip seals purchased form Orbotech/SPTS. They are often failing before we even finish qualifying the system, or within a month thereafter. Our our process is stable with power and parameters not deviating over the past decade. However, I ordered the most recent batch of lip seals because the wafer seals we had been using were coming out with black residue after only a few runs? however, the current ones do the same. Not only have the lips seals disintegrated, but the chamber lid o-ring and bottom ceramic spool o-ring have also failed with black rubber material shedding off. It?s as if they are made of Buna and not meant for this application. Our process is typical Bosch with 100 sccm C4F8 and 20 sccm O2 for etching switching off with ~50 Sccm SF6 for passivation at a processing pressure of 15 mTorr, Coil power 600-800W, Platen power 100-150W, Bias voltage 50-100v (up to 200 peak-to-peak), Platen temp at 19 degrees, Lid temp 41 degrees. Qual wafers are new bare Silicon. Etch rates are normal and stable with 10+ years of data?. we just can?t complete the work due to failing seals. Our chamber base pressure is between 1E-8 and 5E-8 Torr each morning. When we put in a brand new seal and run only the LUR, it passes with 0.00 mTorr/minute leak rate. That jumps to 3.00 mTorr/m after only 30 minutes of the SPTS recommended O2 Clean? then rises as time and more runs progress. Wafers are coming out with black rings on their backsides. This should not be happening, and I believe it is due to incorrect material of the lip seals and o-rings. I am pinging the network, though, to see if there might be a parameter change we need to effect that may assist us. Have any of you seen this before? Best regards, Mark ________________________________________________________________ Mark Weiler Equipment & Facilites Manager Clair and John Bertucci Nanotechnology Laboratory Eden Hall Nanofabrication Cleanroom Carnegie Mellon University P: 412-268-2471 http://www.nanofab.ece.cmu.edu [cid:image001.png at 01D4D3F1.3848EF30] -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.png Type: image/png Size: 720 bytes Desc: image001.png URL: From nclay at upenn.edu Wed Mar 6 09:19:32 2019 From: nclay at upenn.edu (Noah Clay) Date: Wed, 6 Mar 2019 09:19:32 -0500 Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures In-Reply-To: References: Message-ID: Mark, I have seen blackening on the back of the wafer when clamping is poor. Most recently, this was due the e-chuck having been etched excessively and/or polymer redep on the chuck from the endpoint clean step (cleans used to be run without a wafer; we now use SiC). What are your backside He leak rate set points and actual values? We run our etch process at -5C...(SPTS Rapier platform). Thanks, Noah Sent from my iPhone > On Mar 5, 2019, at 15:44, Mark Weiler wrote: > > Hello Everyone, > > We have gone through seven new lip seals purchased form Orbotech/SPTS. They are often failing before we even finish qualifying the system, or within a month thereafter. > > Our our process is stable with power and parameters not deviating over the past decade. However, I ordered the most recent batch of lip seals because the wafer seals we had been using were coming out with black residue after only a few runs? however, the current ones do the same. Not only have the lips seals disintegrated, but the chamber lid o-ring and bottom ceramic spool o-ring have also failed with black rubber material shedding off. It?s as if they are made of Buna and not meant for this application. > > Our process is typical Bosch with 100 sccm C4F8 and 20 sccm O2 for etching switching off with ~50 Sccm SF6 for passivation at a processing pressure of 15 mTorr, Coil power 600-800W, Platen power 100-150W, Bias voltage 50-100v (up to 200 peak-to-peak), Platen temp at 19 degrees, Lid temp 41 degrees. Qual wafers are new bare Silicon. Etch rates are normal and stable with 10+ years of data?. we just can?t complete the work due to failing seals. > > Our chamber base pressure is between 1E-8 and 5E-8 Torr each morning. When we put in a brand new seal and run only the LUR, it passes with 0.00 mTorr/minute leak rate. That jumps to 3.00 mTorr/m after only 30 minutes of the SPTS recommended O2 Clean? then rises as time and more runs progress. Wafers are coming out with black rings on their backsides. > > This should not be happening, and I believe it is due to incorrect material of the lip seals and o-rings. I am pinging the network, though, to see if there might be a parameter change we need to effect that may assist us. > > Have any of you seen this before? > > Best regards, > > Mark > > > ________________________________________________________________ > > Mark Weiler > Equipment & Facilites Manager > Clair and John Bertucci Nanotechnology Laboratory > Eden Hall Nanofabrication Cleanroom > Carnegie Mellon University > P: 412-268-2471 > http://www.nanofab.ece.cmu.edu > > > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From kchow10 at gmail.com Wed Mar 6 09:22:16 2019 From: kchow10 at gmail.com (Edmond Chow) Date: Wed, 6 Mar 2019 08:22:16 -0600 Subject: [labnetwork] HSQ developer compatible with AlN for electron beam lithography (EBL) In-Reply-To: <26b2846d16984b939c5f8ade9e7336a9@dtu.dk> References: <69FD30F0-35D1-417C-8C07-5F70F5530F9F@andrew.cmu.edu> <26b2846d16984b939c5f8ade9e7336a9@dtu.dk> Message-ID: Hello, We are trying to pattern HSQ with EBL on AlN film substrate,. We typically use 2.2%TMAH (MF 319)as our HSQ developer. However TMAH will attach AlN film and cause problem for our sample. Does anyone has some HSQ developer that is compatible with AlN? Thanks. Edmond -------------- next part -------------- An HTML attachment was scrubbed... URL: From mweiler at andrew.cmu.edu Wed Mar 6 10:17:52 2019 From: mweiler at andrew.cmu.edu (Mark Weiler) Date: Wed, 6 Mar 2019 15:17:52 +0000 Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures In-Reply-To: References: , Message-ID: <5BAB86D2-F5F3-42DB-B6EF-4B6DCF676555@andrew.cmu.edu> Hi Noah, We have the first version of the 100mm STS Multiplex DRIE whereby the wafer is mechanically clamped with weighted ceramic fingers, and the wafer is lifted with a tripod. Our LUR is 0.00 mTorr/min when new, but rises to 15-20 mT/m within a week. We have an older HBC controller that indicates 6.5 for pressure at 2.33 flow rate... I apologize but don?t know the units for either. If these values are incorrect, it could be because they were adjusted to ensure a leak rate would pass. I will need to go back over a decade in the logs to see if any changes were made over time...but, our rates and results have been consistent. I believe the issue is material related, because we have our chamber lid o-ring and bottom ceramic o-ring failing with the same symptoms. Thanks, Mark Mark Weiler Equipment & Facilities Manager Claire and John Bertucci Nanotechnology Laboratory Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.2471 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu On Mar 6, 2019, at 09:19, Noah Clay > wrote: Mark, I have seen blackening on the back of the wafer when clamping is poor. Most recently, this was due the e-chuck having been etched excessively and/or polymer redep on the chuck from the endpoint clean step (cleans used to be run without a wafer; we now use SiC). What are your backside He leak rate set points and actual values? We run our etch process at -5C...(SPTS Rapier platform). Thanks, Noah Sent from my iPhone On Mar 5, 2019, at 15:44, Mark Weiler > wrote: Hello Everyone, We have gone through seven new lip seals purchased form Orbotech/SPTS. They are often failing before we even finish qualifying the system, or within a month thereafter. Our our process is stable with power and parameters not deviating over the past decade. However, I ordered the most recent batch of lip seals because the wafer seals we had been using were coming out with black residue after only a few runs? however, the current ones do the same. Not only have the lips seals disintegrated, but the chamber lid o-ring and bottom ceramic spool o-ring have also failed with black rubber material shedding off. It?s as if they are made of Buna and not meant for this application. Our process is typical Bosch with 100 sccm C4F8 and 20 sccm O2 for etching switching off with ~50 Sccm SF6 for passivation at a processing pressure of 15 mTorr, Coil power 600-800W, Platen power 100-150W, Bias voltage 50-100v (up to 200 peak-to-peak), Platen temp at 19 degrees, Lid temp 41 degrees. Qual wafers are new bare Silicon. Etch rates are normal and stable with 10+ years of data?. we just can?t complete the work due to failing seals. Our chamber base pressure is between 1E-8 and 5E-8 Torr each morning. When we put in a brand new seal and run only the LUR, it passes with 0.00 mTorr/minute leak rate. That jumps to 3.00 mTorr/m after only 30 minutes of the SPTS recommended O2 Clean? then rises as time and more runs progress. Wafers are coming out with black rings on their backsides. This should not be happening, and I believe it is due to incorrect material of the lip seals and o-rings. I am pinging the network, though, to see if there might be a parameter change we need to effect that may assist us. Have any of you seen this before? Best regards, Mark ________________________________________________________________ Mark Weiler Equipment & Facilites Manager Clair and John Bertucci Nanotechnology Laboratory Eden Hall Nanofabrication Cleanroom Carnegie Mellon University P: 412-268-2471 http://www.nanofab.ece.cmu.edu _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From julia.aebersold at louisville.edu Wed Mar 6 11:08:43 2019 From: julia.aebersold at louisville.edu (Aebersold,Julia W.) Date: Wed, 6 Mar 2019 16:08:43 +0000 Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures In-Reply-To: References: <69FD30F0-35D1-417C-8C07-5F70F5530F9F@andrew.cmu.edu>, Message-ID: Keep in mind that the HeLUR is an overall pressure indicator. Your lip seal may be fine and your chamber may be leaking elsewhere. We have run into the same problem and have been performing an helium leak check. The lid seal could be a culprit, too. Also, make sure that your VAT gate valve door is holding good vacuum by checking your chamber pressure. If it goes up when the load lock is open then the gate valve door may be suspect. Cheers! Julia Aebersold, Ph.D. MNTC Cleanroom Manager University of Louisville 2210 South Brook Street Shumaker Research Building, Room 233 Louisville, KY 40292 (502) 852-1572 http://louisville.edu/micronano/ ________________________________ From: labnetwork-bounces at mtl.mit.edu on behalf of N P VAMSI KRISHNA Sent: Tuesday, March 5, 2019 8:25:38 PM To: Mark Weiler Cc: Fab Network Subject: Re: [labnetwork] STS DRIE Multiplex Lip Seal failures Hi Mark Weiler, In my experience, the chamber O-rings should be Kalrez O-Rings, which can withstand very high temperatures (white color O-ring). I request you to check once if SPTS is supplying you the right one. Please check all the 4 chamber heaters (inner wall, chamber, and others) and confirm if the temperatures (~120 deg C) and the respective voltages are within the spec. Maybe one of the heaters is getting a higher voltage. Hope this helps. Thanks and best regards, vamsi On Wed, Mar 6, 2019 at 6:11 AM Mark Weiler > wrote: Correction... In my haste to write something up and get out the door I mixed up the gas is in the problem description. Our process is typical Bosch SF6 and O2 for etching .... switching off with C4F8 for passivation... Mark Mark Weiler Equipment & Facilities Manager Claire and John Bertucci Nanotechnology Laboratory Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.2471 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu On Mar 5, 2019, at 18:42, Mark Weiler > wrote: Hello Everyone, We have gone through seven new lip seals purchased form Orbotech/SPTS. They are often failing before we even finish qualifying the system, or within a month thereafter. Our our process is stable with power and parameters not deviating over the past decade. However, I ordered the most recent batch of lip seals because the wafer seals we had been using were coming out with black residue after only a few runs? however, the current ones do the same. Not only have the lips seals disintegrated, but the chamber lid o-ring and bottom ceramic spool o-ring have also failed with black rubber material shedding off. It?s as if they are made of Buna and not meant for this application. Our process is typical Bosch with 100 sccm C4F8 and 20 sccm O2 for etching switching off with ~50 Sccm SF6 for passivation at a processing pressure of 15 mTorr, Coil power 600-800W, Platen power 100-150W, Bias voltage 50-100v (up to 200 peak-to-peak), Platen temp at 19 degrees, Lid temp 41 degrees. Qual wafers are new bare Silicon. Etch rates are normal and stable with 10+ years of data?. we just can?t complete the work due to failing seals. Our chamber base pressure is between 1E-8 and 5E-8 Torr each morning. When we put in a brand new seal and run only the LUR, it passes with 0.00 mTorr/minute leak rate. That jumps to 3.00 mTorr/m after only 30 minutes of the SPTS recommended O2 Clean? then rises as time and more runs progress. Wafers are coming out with black rings on their backsides. This should not be happening, and I believe it is due to incorrect material of the lip seals and o-rings. I am pinging the network, though, to see if there might be a parameter change we need to effect that may assist us. Have any of you seen this before? Best regards, Mark ________________________________________________________________ Mark Weiler Equipment & Facilites Manager Clair and John Bertucci Nanotechnology Laboratory Eden Hall Nanofabrication Cleanroom Carnegie Mellon University P: 412-268-2471 http://www.nanofab.ece.cmu.edu [cid:1695085976caafb21b31] _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -- -- Thanks & Best Regards, ----------------- N.P.Vamsi Krishna 3D Heterogeneous Integration and System Scaling Lab, Center for Nano Science and Engineering (CeNSE), Indian Institute of Science(IISc), Bangalore. INDIA-560012 -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: images.png Type: image/png Size: 720 bytes Desc: images.png URL: From sguo18 at yorku.ca Wed Mar 6 13:30:02 2019 From: sguo18 at yorku.ca (Xin (Shane) Guo) Date: Wed, 6 Mar 2019 18:30:02 +0000 Subject: [labnetwork] Universal standards of microfab enviornment Message-ID: Hi Colleagues, Is there a universal standard for microfabrication cleanroom, outlining the requirement of humidity, temperature, noise, etc? Any documentation available? Cheers Shane -------------- next part -------------- An HTML attachment was scrubbed... URL: From bill_flounders at berkeley.edu Wed Mar 6 17:01:22 2019 From: bill_flounders at berkeley.edu (A. William (Bill) FLOUNDERS) Date: Wed, 6 Mar 2019 14:01:22 -0800 Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures In-Reply-To: <6181704F-4A5F-4A52-B386-7B6C505A5B1F@andrew.cmu.edu> References: <8395D872-145D-42D7-8D7D-558BAE91C048@cns.fas.harvard.edu> <6181704F-4A5F-4A52-B386-7B6C505A5B1F@andrew.cmu.edu> Message-ID: If you are seeking an alternate supplier of improved o-rings, Berkeley NanoLab has had good experience with the cost competitive and Kalrez equivalent products offered by FloDynamix. Their FFKM versions "Kratos" and "Gumlast" have served us well in several applications. Bill Flounders UC Berkeley NanoLab On Wed, Mar 6, 2019 at 1:56 PM Mark Weiler wrote: > Hi David, > > I am currently working with an elastomer manufacturer to produce O-Rings > and seals for the systems of a material that can withstand better > temperature ranges and chemical attacks. If you would like, I can share > the information with you and maybe you can join us in this endeavor. The > cost for the tooling and mold is now at ~1900 dollars, but I have > negotiated the seal price to around 130.00 ea. I have not yet tested this > material but we are having a seal made specifically for the Bosch process > and 02 cleans. > > It is my believe that Orbotech has changed suppliers, or has allowed their > supplier to switch their material source without testing, all in an effort > to shave costs. > > My new efforts have also yielded a lower cost (50%) for the ceramic > components in the chamber. I will test these and get back with the lab > network sharing the source and part number. > > Thank you for sharing your info; now I know we are not the only ones > ?feeling the pain? so to speak and can officially commiserate... LOL > > Best, > > Mark > > *Mark Weiler* > Equipment & Facilities Manager > Claire and John Bertucci Nanotechnology Laboratory > Electrical and Computer Engineering | Carnegie Mellon University > 5000 Forbes Ave., Pittsburgh, PA 15213-3890 > T: 412.268.2471 <412.268.5430> > F: 412.268.3497 > www.ece.cmu.edu > nanofab.ece.cmu.edu > > On Mar 6, 2019, at 08:46, LaFleur, David W > wrote: > > Hi Mark, > > > > We have an STS MP0579 ICP which uses the lip seals. It is used mostly for > silicon and SiO2 etches with O2 cleans between uses. Most of our Bosch > processes are run on SPTS Rapier which uses an ESC. That has its own set of > issues. We find the lip seals don?t last more than 2-3 weeks in our system. > Our chamber o-rings usually go for 2 months at best. I was thinking of > changing to a kalrez o-ring and always wondered if they made a Kalrez lip > seal. One suggestion on how to make them last longer is make sure they > don?t get exposed to any solvents like Isopropyl when you are installing > them. I want to say I am not happy with the longevity of the lip seals > either and maybe we need to bring this to the attention of Orbotech/SPTS. > Maybe they have a solution. Other than that they are good tools, very > reliable, and heavily used here at Harvard. Because they are so heavily > used with so many processes we find a biweekly chamber clean and lip seal > replacement works well for everyone. This is why I have just lived with the > lip seals as they are. > > > > Regards, > > > > David LaFleur > > Equipment Engineer > > CNS, Harvard University > > > > *From: *"labnetwork-bounces at mtl.mit.edu" > on behalf of Mark Weiler > *Date: *Tuesday, March 5, 2019 at 3:44 PM > *To: *Fab Network > *Subject: *[labnetwork] STS DRIE Multiplex Lip Seal failures > > > > Hello Everyone, > > > > We have gone through seven new lip seals purchased form Orbotech/SPTS. > They are often failing before we even finish qualifying the system, or > within a month thereafter. > > > > Our our process is stable with power and parameters not deviating over the > past decade. However, I ordered the most recent batch of lip seals because > the wafer seals we had been using were coming out with black residue after > only a few runs? however, the current ones do the same. Not only have the > lips seals disintegrated, but the chamber lid o-ring and bottom ceramic > spool o-ring have also failed with black rubber material shedding off. > It?s as if they are made of Buna and not meant for this application. > > > > Our process is typical Bosch with 100 sccm C4F8 and 20 sccm O2 for etching > switching off with ~50 Sccm SF6 for passivation at a processing pressure of > 15 mTorr, Coil power 600-800W, Platen power 100-150W, Bias voltage 50-100v > (up to 200 peak-to-peak), Platen temp at 19 degrees, Lid temp 41 degrees. > Qual wafers are new bare Silicon. Etch rates are normal and stable with > 10+ years of data?. we just can?t complete the work due to failing seals. > > > > Our chamber base pressure is between 1E-8 and 5E-8 Torr each morning. > When we put in a brand new seal and run only the LUR, it passes with 0.00 > mTorr/minute leak rate. That jumps to 3.00 mTorr/m after only 30 minutes > of the SPTS recommended O2 Clean? then rises as time and more runs > progress. Wafers are coming out with black rings on their backsides. > > > > This should not be happening, and I believe it is due to incorrect > material of the lip seals and o-rings. I am pinging the network, though, > to see if there might be a parameter change we need to effect that may > assist us. > > > > Have any of you seen this before? > > > > Best regards, > > > > Mark > > > > ________________________________________________________________ > > > > Mark Weiler > > Equipment & Facilites Manager > > Clair and John Bertucci Nanotechnology Laboratory > > Eden Hall Nanofabrication Cleanroom > > Carnegie Mellon University > > P: 412-268-2471 > > http://www.nanofab.ece.cmu.edu > > > > > > > > > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > -------------- next part -------------- An HTML attachment was scrubbed... URL: From spaolini at cns.fas.harvard.edu Wed Mar 6 17:21:04 2019 From: spaolini at cns.fas.harvard.edu (Paolini, Steven) Date: Wed, 6 Mar 2019 22:21:04 +0000 Subject: [labnetwork] Universal standards of microfab enviornment In-Reply-To: References: Message-ID: Shane, The most often referenced material is from SEMI standards. Semistandards.org Whatever criteria you adopt, please note that it is of the utmost importance to ensure consistency. If temperature and RH vary, it will introduce unwanted variables in sensitive and complex processes. Another important point is to keep the RH relatively high (48%) to reduce ESD. If the RH and temperature fluctuate, you will encounter variation in your photo speed. Hope this helps. Steve Steve Paolini Principal Equipment Engineer Harvard University Center for Nanoscale Systems 11 Oxford St. Cambridge, MA 02138 617- 496- 9816 spaolini at cns.fas.harvard.edu www.cns.fas.harvard.edu From: labnetwork-bounces at mtl.mit.edu On Behalf Of Xin (Shane) Guo Sent: Wednesday, March 06, 2019 1:30 PM To: labnetwork at mtl.mit.edu Subject: [labnetwork] Universal standards of microfab enviornment Hi Colleagues, Is there a universal standard for microfabrication cleanroom, outlining the requirement of humidity, temperature, noise, etc? Any documentation available? Cheers Shane -------------- next part -------------- An HTML attachment was scrubbed... URL: From spaolini at cns.fas.harvard.edu Wed Mar 6 17:31:53 2019 From: spaolini at cns.fas.harvard.edu (Paolini, Steven) Date: Wed, 6 Mar 2019 22:31:53 +0000 Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures In-Reply-To: <5BAB86D2-F5F3-42DB-B6EF-4B6DCF676555@andrew.cmu.edu> References: , <5BAB86D2-F5F3-42DB-B6EF-4B6DCF676555@andrew.cmu.edu> Message-ID: My $0.02, Black marks on the back of a wafer are not normal. I agree that there must have been a material change by the supplier perhaps to ?value engineer? there consumables. What IS normal is O-rings growing a black crud on their surfaces. This is simply O2 attacking organics regardless of the O-rings being out of the ? line of sight? of the plasma. A downstream etcher (two 90 degree gas shifts), will experience the same effect at a slower rate. We inspect them and if not cracked, we clean them up until the wipes show minimum crud and put them back in for more service. Oh yeah, I wholeheartedly agree with Julia that we should not forget that the LUR with backside He is the overall LUR of the chamber and you could be mislead by some other fine leak not associated with the He seal. Steve Paolini Principal Equipment Engineer Harvard University Center for Nanoscale Systems 11 Oxford St. Cambridge, MA 02138 617- 496- 9816 spaolini at cns.fas.harvard.edu www.cns.fas.harvard.edu From: labnetwork-bounces at mtl.mit.edu On Behalf Of Mark Weiler Sent: Wednesday, March 06, 2019 10:18 AM To: Noah Clay Cc: Fab Network Subject: Re: [labnetwork] STS DRIE Multiplex Lip Seal failures Hi Noah, We have the first version of the 100mm STS Multiplex DRIE whereby the wafer is mechanically clamped with weighted ceramic fingers, and the wafer is lifted with a tripod. Our LUR is 0.00 mTorr/min when new, but rises to 15-20 mT/m within a week. We have an older HBC controller that indicates 6.5 for pressure at 2.33 flow rate... I apologize but don?t know the units for either. If these values are incorrect, it could be because they were adjusted to ensure a leak rate would pass. I will need to go back over a decade in the logs to see if any changes were made over time...but, our rates and results have been consistent. I believe the issue is material related, because we have our chamber lid o-ring and bottom ceramic o-ring failing with the same symptoms. Thanks, Mark Mark Weiler Equipment & Facilities Manager Claire and John Bertucci Nanotechnology Laboratory Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.2471 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu On Mar 6, 2019, at 09:19, Noah Clay > wrote: Mark, I have seen blackening on the back of the wafer when clamping is poor. Most recently, this was due the e-chuck having been etched excessively and/or polymer redep on the chuck from the endpoint clean step (cleans used to be run without a wafer; we now use SiC). What are your backside He leak rate set points and actual values? We run our etch process at -5C...(SPTS Rapier platform). Thanks, Noah Sent from my iPhone On Mar 5, 2019, at 15:44, Mark Weiler > wrote: Hello Everyone, We have gone through seven new lip seals purchased form Orbotech/SPTS. They are often failing before we even finish qualifying the system, or within a month thereafter. Our our process is stable with power and parameters not deviating over the past decade. However, I ordered the most recent batch of lip seals because the wafer seals we had been using were coming out with black residue after only a few runs? however, the current ones do the same. Not only have the lips seals disintegrated, but the chamber lid o-ring and bottom ceramic spool o-ring have also failed with black rubber material shedding off. It?s as if they are made of Buna and not meant for this application. Our process is typical Bosch with 100 sccm C4F8 and 20 sccm O2 for etching switching off with ~50 Sccm SF6 for passivation at a processing pressure of 15 mTorr, Coil power 600-800W, Platen power 100-150W, Bias voltage 50-100v (up to 200 peak-to-peak), Platen temp at 19 degrees, Lid temp 41 degrees. Qual wafers are new bare Silicon. Etch rates are normal and stable with 10+ years of data?. we just can?t complete the work due to failing seals. Our chamber base pressure is between 1E-8 and 5E-8 Torr each morning. When we put in a brand new seal and run only the LUR, it passes with 0.00 mTorr/minute leak rate. That jumps to 3.00 mTorr/m after only 30 minutes of the SPTS recommended O2 Clean? then rises as time and more runs progress. Wafers are coming out with black rings on their backsides. This should not be happening, and I believe it is due to incorrect material of the lip seals and o-rings. I am pinging the network, though, to see if there might be a parameter change we need to effect that may assist us. Have any of you seen this before? Best regards, Mark ________________________________________________________________ Mark Weiler Equipment & Facilites Manager Clair and John Bertucci Nanotechnology Laboratory Eden Hall Nanofabrication Cleanroom Carnegie Mellon University P: 412-268-2471 http://www.nanofab.ece.cmu.edu _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From mpleil at unm.edu Wed Mar 6 19:55:30 2019 From: mpleil at unm.edu (Matthias Pleil) Date: Thu, 7 Mar 2019 00:55:30 +0000 Subject: [labnetwork] Universal standards of microfab enviornment In-Reply-To: References: , Message-ID: In addition, relative humidity is critical in photolithography, many photoresists require re-hydration after soft bake and before exposure. Low humidity will cause patterning problems (been there, done that). Kind Regards, Matthias Pleil, Ph.D. Research Professor & Lecturer III of Mech. Eng - UNM UNM MTTC Cleanroom Manager PI - Southwest Center for Microsystems Education, Support Center for Microsystems Education scme-nm.org, scme-support.org (505)272-7157 ________________________________ From: labnetwork-bounces at mtl.mit.edu on behalf of Paolini, Steven Sent: Wednesday, March 6, 2019 3:21 PM To: Xin (Shane) Guo; labnetwork at mtl.mit.edu Subject: Re: [labnetwork] Universal standards of microfab enviornment Shane, The most often referenced material is from SEMI standards. Semistandards.org Whatever criteria you adopt, please note that it is of the utmost importance to ensure consistency. If temperature and RH vary, it will introduce unwanted variables in sensitive and complex processes. Another important point is to keep the RH relatively high (48%) to reduce ESD. If the RH and temperature fluctuate, you will encounter variation in your photo speed. Hope this helps. Steve Steve Paolini Principal Equipment Engineer Harvard University Center for Nanoscale Systems 11 Oxford St. Cambridge, MA 02138 617- 496- 9816 spaolini at cns.fas.harvard.edu www.cns.fas.harvard.edu From: labnetwork-bounces at mtl.mit.edu On Behalf Of Xin (Shane) Guo Sent: Wednesday, March 06, 2019 1:30 PM To: labnetwork at mtl.mit.edu Subject: [labnetwork] Universal standards of microfab enviornment Hi Colleagues, Is there a universal standard for microfabrication cleanroom, outlining the requirement of humidity, temperature, noise, etc? Any documentation available? Cheers Shane -------------- next part -------------- An HTML attachment was scrubbed... URL: From mweiler at andrew.cmu.edu Wed Mar 6 20:47:53 2019 From: mweiler at andrew.cmu.edu (Mark Weiler) Date: Thu, 7 Mar 2019 01:47:53 +0000 Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures In-Reply-To: References: <8395D872-145D-42D7-8D7D-558BAE91C048@cns.fas.harvard.edu> <6181704F-4A5F-4A52-B386-7B6C505A5B1F@andrew.cmu.edu>, Message-ID: <2F93F2AA-76E0-46FB-8747-0AB7CDCA8162@andrew.cmu.edu> Certainly... thanks for the lead, Bill. Best, Mark Mark Weiler Equipment & Facilities Manager Claire and John Bertucci Nanotechnology Laboratory Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.2471 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu On Mar 6, 2019, at 17:01, A. William (Bill) FLOUNDERS > wrote: If you are seeking an alternate supplier of improved o-rings, Berkeley NanoLab has had good experience with the cost competitive and Kalrez equivalent products offered by FloDynamix. Their FFKM versions "Kratos" and "Gumlast" have served us well in several applications. Bill Flounders UC Berkeley NanoLab On Wed, Mar 6, 2019 at 1:56 PM Mark Weiler > wrote: Hi David, I am currently working with an elastomer manufacturer to produce O-Rings and seals for the systems of a material that can withstand better temperature ranges and chemical attacks. If you would like, I can share the information with you and maybe you can join us in this endeavor. The cost for the tooling and mold is now at ~1900 dollars, but I have negotiated the seal price to around 130.00 ea. I have not yet tested this material but we are having a seal made specifically for the Bosch process and 02 cleans. It is my believe that Orbotech has changed suppliers, or has allowed their supplier to switch their material source without testing, all in an effort to shave costs. My new efforts have also yielded a lower cost (50%) for the ceramic components in the chamber. I will test these and get back with the lab network sharing the source and part number. Thank you for sharing your info; now I know we are not the only ones ?feeling the pain? so to speak and can officially commiserate... LOL Best, Mark Mark Weiler Equipment & Facilities Manager Claire and John Bertucci Nanotechnology Laboratory Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.2471 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu On Mar 6, 2019, at 08:46, LaFleur, David W > wrote: Hi Mark, We have an STS MP0579 ICP which uses the lip seals. It is used mostly for silicon and SiO2 etches with O2 cleans between uses. Most of our Bosch processes are run on SPTS Rapier which uses an ESC. That has its own set of issues. We find the lip seals don?t last more than 2-3 weeks in our system. Our chamber o-rings usually go for 2 months at best. I was thinking of changing to a kalrez o-ring and always wondered if they made a Kalrez lip seal. One suggestion on how to make them last longer is make sure they don?t get exposed to any solvents like Isopropyl when you are installing them. I want to say I am not happy with the longevity of the lip seals either and maybe we need to bring this to the attention of Orbotech/SPTS. Maybe they have a solution. Other than that they are good tools, very reliable, and heavily used here at Harvard. Because they are so heavily used with so many processes we find a biweekly chamber clean and lip seal replacement works well for everyone. This is why I have just lived with the lip seals as they are. Regards, David LaFleur Equipment Engineer CNS, Harvard University From: "labnetwork-bounces at mtl.mit.edu" > on behalf of Mark Weiler > Date: Tuesday, March 5, 2019 at 3:44 PM To: Fab Network > Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures Hello Everyone, We have gone through seven new lip seals purchased form Orbotech/SPTS. They are often failing before we even finish qualifying the system, or within a month thereafter. Our our process is stable with power and parameters not deviating over the past decade. However, I ordered the most recent batch of lip seals because the wafer seals we had been using were coming out with black residue after only a few runs? however, the current ones do the same. Not only have the lips seals disintegrated, but the chamber lid o-ring and bottom ceramic spool o-ring have also failed with black rubber material shedding off. It?s as if they are made of Buna and not meant for this application. Our process is typical Bosch with 100 sccm C4F8 and 20 sccm O2 for etching switching off with ~50 Sccm SF6 for passivation at a processing pressure of 15 mTorr, Coil power 600-800W, Platen power 100-150W, Bias voltage 50-100v (up to 200 peak-to-peak), Platen temp at 19 degrees, Lid temp 41 degrees. Qual wafers are new bare Silicon. Etch rates are normal and stable with 10+ years of data?. we just can?t complete the work due to failing seals. Our chamber base pressure is between 1E-8 and 5E-8 Torr each morning. When we put in a brand new seal and run only the LUR, it passes with 0.00 mTorr/minute leak rate. That jumps to 3.00 mTorr/m after only 30 minutes of the SPTS recommended O2 Clean? then rises as time and more runs progress. Wafers are coming out with black rings on their backsides. This should not be happening, and I believe it is due to incorrect material of the lip seals and o-rings. I am pinging the network, though, to see if there might be a parameter change we need to effect that may assist us. Have any of you seen this before? Best regards, Mark ________________________________________________________________ Mark Weiler Equipment & Facilites Manager Clair and John Bertucci Nanotechnology Laboratory Eden Hall Nanofabrication Cleanroom Carnegie Mellon University P: 412-268-2471 http://www.nanofab.ece.cmu.edu _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From michael.rooks at yale.edu Wed Mar 6 23:15:01 2019 From: michael.rooks at yale.edu (Michael Rooks) Date: Wed, 6 Mar 2019 21:15:01 -0700 Subject: [labnetwork] HSQ developer compatible with AlN for electron beam lithography (EBL) In-Reply-To: References: <69FD30F0-35D1-417C-8C07-5F70F5530F9F@andrew.cmu.edu> <26b2846d16984b939c5f8ade9e7336a9@dtu.dk> Message-ID: <04bd4466-372a-b7b7-df37-4406b2d900d1@yale.edu> TMAH and NaOH will both attack aluminum, but you can use a thin layer of PMMA under the HSQ, to protect the substrate. Then after development, use a brief oxygen plasma to clear away the PMMA. Oxygen will not etch HSQ at all. There is also some sort of buffered photoresist developer just for aluminum, but I've never tried that for HSQ. ------------------------------------ Michael Rooks Yale Institute for Nanoscience and Quantum Engineering nano.yale.edu On 3/6/2019 7:22 AM, Edmond Chow wrote: > Hello, > > We are trying to pattern HSQ with EBL on AlN film substrate,. We > typically use 2.2%TMAH (MF 319)as our HSQ developer. > However TMAH will attach AlN film and cause problem for our sample. > > Does anyone has some HSQ developer that is compatible with AlN? > > Thanks. > > Edmond > > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From odc1n08 at soton.ac.uk Thu Mar 7 03:40:47 2019 From: odc1n08 at soton.ac.uk (Clark O.D.) Date: Thu, 7 Mar 2019 08:40:47 +0000 Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures In-Reply-To: References: , <5BAB86D2-F5F3-42DB-B6EF-4B6DCF676555@andrew.cmu.edu> Message-ID: For what it is worth we used to run an SPTS Pegasus deep RIE etcher years ago, there is a Plasmatherm Versaline in its place now. I think we sold it ~6 years ago. We had many problems with it towards the end of its life but o-ring seals were with regards to chamber or He leak rate were not one. We used the same set for possibly years at a time. I recall being advised on an official training course to boil them for a couple of hours in water to remove the flatted edge before re-sealing the chamber which I never did, but always found to be quite interesting advice. I did have to rebuild the lower platen once due to a coolant leak and it did take me a about a day to get it to seal due to the complex arrangement of o-rings. If the black circle on the rear of the wafer is not the material breakdown of the o-ring itself, it could be micro-masking from rear wafer deposited polymer/spontaneous etching of Si radicals giving a rough Si surface? Do not ask me why this would be the case but we find it is often the cause of unexpectedly blackened Si wafers removed from etch chambers. O. From: labnetwork-bounces at mtl.mit.edu On Behalf Of Paolini, Steven Sent: 06 March 2019 22:32 To: Mark Weiler ; Noah Clay Cc: Fab Network Subject: Re: [labnetwork] STS DRIE Multiplex Lip Seal failures My $0.02, Black marks on the back of a wafer are not normal. I agree that there must have been a material change by the supplier perhaps to ?value engineer? there consumables. What IS normal is O-rings growing a black crud on their surfaces. This is simply O2 attacking organics regardless of the O-rings being out of the ? line of sight? of the plasma. A downstream etcher (two 90 degree gas shifts), will experience the same effect at a slower rate. We inspect them and if not cracked, we clean them up until the wipes show minimum crud and put them back in for more service. Oh yeah, I wholeheartedly agree with Julia that we should not forget that the LUR with backside He is the overall LUR of the chamber and you could be mislead by some other fine leak not associated with the He seal. Steve Paolini Principal Equipment Engineer Harvard University Center for Nanoscale Systems 11 Oxford St. Cambridge, MA 02138 617- 496- 9816 spaolini at cns.fas.harvard.edu www.cns.fas.harvard.edu From: labnetwork-bounces at mtl.mit.edu > On Behalf Of Mark Weiler Sent: Wednesday, March 06, 2019 10:18 AM To: Noah Clay > Cc: Fab Network > Subject: Re: [labnetwork] STS DRIE Multiplex Lip Seal failures Hi Noah, We have the first version of the 100mm STS Multiplex DRIE whereby the wafer is mechanically clamped with weighted ceramic fingers, and the wafer is lifted with a tripod. Our LUR is 0.00 mTorr/min when new, but rises to 15-20 mT/m within a week. We have an older HBC controller that indicates 6.5 for pressure at 2.33 flow rate... I apologize but don?t know the units for either. If these values are incorrect, it could be because they were adjusted to ensure a leak rate would pass. I will need to go back over a decade in the logs to see if any changes were made over time...but, our rates and results have been consistent. I believe the issue is material related, because we have our chamber lid o-ring and bottom ceramic o-ring failing with the same symptoms. Thanks, Mark Mark Weiler Equipment & Facilities Manager Claire and John Bertucci Nanotechnology Laboratory Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.2471 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu On Mar 6, 2019, at 09:19, Noah Clay > wrote: Mark, I have seen blackening on the back of the wafer when clamping is poor. Most recently, this was due the e-chuck having been etched excessively and/or polymer redep on the chuck from the endpoint clean step (cleans used to be run without a wafer; we now use SiC). What are your backside He leak rate set points and actual values? We run our etch process at -5C...(SPTS Rapier platform). Thanks, Noah Sent from my iPhone On Mar 5, 2019, at 15:44, Mark Weiler > wrote: Hello Everyone, We have gone through seven new lip seals purchased form Orbotech/SPTS. They are often failing before we even finish qualifying the system, or within a month thereafter. Our our process is stable with power and parameters not deviating over the past decade. However, I ordered the most recent batch of lip seals because the wafer seals we had been using were coming out with black residue after only a few runs? however, the current ones do the same. Not only have the lips seals disintegrated, but the chamber lid o-ring and bottom ceramic spool o-ring have also failed with black rubber material shedding off. It?s as if they are made of Buna and not meant for this application. Our process is typical Bosch with 100 sccm C4F8 and 20 sccm O2 for etching switching off with ~50 Sccm SF6 for passivation at a processing pressure of 15 mTorr, Coil power 600-800W, Platen power 100-150W, Bias voltage 50-100v (up to 200 peak-to-peak), Platen temp at 19 degrees, Lid temp 41 degrees. Qual wafers are new bare Silicon. Etch rates are normal and stable with 10+ years of data?. we just can?t complete the work due to failing seals. Our chamber base pressure is between 1E-8 and 5E-8 Torr each morning. When we put in a brand new seal and run only the LUR, it passes with 0.00 mTorr/minute leak rate. That jumps to 3.00 mTorr/m after only 30 minutes of the SPTS recommended O2 Clean? then rises as time and more runs progress. Wafers are coming out with black rings on their backsides. This should not be happening, and I believe it is due to incorrect material of the lip seals and o-rings. I am pinging the network, though, to see if there might be a parameter change we need to effect that may assist us. Have any of you seen this before? Best regards, Mark ________________________________________________________________ Mark Weiler Equipment & Facilites Manager Clair and John Bertucci Nanotechnology Laboratory Eden Hall Nanofabrication Cleanroom Carnegie Mellon University P: 412-268-2471 http://www.nanofab.ece.cmu.edu _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From kjvowen at lnf.umich.edu Thu Mar 7 13:44:33 2019 From: kjvowen at lnf.umich.edu (Kevin Owen) Date: Thu, 7 Mar 2019 13:44:33 -0500 Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures In-Reply-To: References: <5BAB86D2-F5F3-42DB-B6EF-4B6DCF676555@andrew.cmu.edu> Message-ID: We don't have lip seals on our SPTS systems, but I do agree that Kalrez is the way to go for o-rings. All of the source o-rings for the Pegasus were Kalrez to begin with. Well, except for a couple that were called out in the BOM as Kalrez but weren't... this was remedied. I also replaced our lid seals with Kalrez about a year ago and it was definitely a Good Decision. I wound up going with the 9300 series for the Bosch process equipment. Used to source them through Bay Seal, who was even able to make the custom size for the lid seal (it's not actually a 280, just seems like it should be), without the crazy tooling cost for most custom sizes. Recently, they suggested I find a distributor closer to my area, and I went with James Walker in Chicago, which seemed to work well for my last order. The one case I've found where this did not work as expected was the lid o-ring in our APS tool. I think it is because we tend to excessively over-clean the chamber to accommodate some "dirtier" processes, the Kalrez o-ring actually got substantially eaten away after only about 6 months. I wonder if this could also be related to some of the lip seal issues (not saying they didn't switch to a "cheaper" material also), but it might be that over-using O2 cleans could shorten the life further like it did to my o-ring. -Kevin On Wed, Mar 6, 2019 at 7:51 PM Paolini, Steven wrote: > My $0.02, > > Black marks on the back of a wafer are not normal. I agree that there must > have been a material change by the supplier perhaps to ?value engineer? > there consumables. What IS normal is O-rings growing a black crud on their > surfaces. This is simply O2 attacking organics regardless of the O-rings > being out of the ? line of sight? of the plasma. A downstream etcher (two > 90 degree gas shifts), will experience the same effect at a slower rate. We > inspect them and if not cracked, we clean them up until the wipes show > minimum crud and put them back in for more service. > > Oh yeah, I wholeheartedly agree with Julia that we should not forget that > the LUR with backside He is the *overall *LUR of the chamber and you > could be mislead by some other fine leak not associated with the He seal. > > > > Steve Paolini > > Principal Equipment Engineer > > Harvard University Center for Nanoscale Systems > > 11 Oxford St. > > Cambridge, MA 02138 > > 617- 496- 9816 > > spaolini at cns.fas.harvard.edu > > www.cns.fas.harvard.edu > > > > *From:* labnetwork-bounces at mtl.mit.edu *On > Behalf Of *Mark Weiler > *Sent:* Wednesday, March 06, 2019 10:18 AM > *To:* Noah Clay > *Cc:* Fab Network > *Subject:* Re: [labnetwork] STS DRIE Multiplex Lip Seal failures > > > > Hi Noah, > > > > We have the first version of the 100mm STS Multiplex DRIE whereby the > wafer is mechanically clamped with weighted ceramic fingers, and the wafer > is lifted with a tripod. Our LUR is 0.00 mTorr/min when new, but rises to > 15-20 mT/m within a week. We have an older HBC controller that indicates > 6.5 for pressure at 2.33 flow rate... I apologize but don?t know the units > for either. If these values are incorrect, it could be because they were > adjusted to ensure a leak rate would pass. I will need to go back over a > decade in the logs to see if any changes were made over time...but, our > rates and results have been consistent. > > > > I believe the issue is material related, because we have our chamber lid > o-ring and bottom ceramic o-ring failing with the same symptoms. > > > > Thanks, > > > > Mark > > > > > > *Mark Weiler* > Equipment & Facilities Manager > > Claire and John Bertucci Nanotechnology Laboratory > Electrical and Computer Engineering | Carnegie Mellon University > 5000 Forbes Ave., Pittsburgh, PA 15213-3890 > T: 412.268.2471 <412.268.5430> > F: 412.268.3497 > www.ece.cmu.edu > > nanofab.ece.cmu.edu > > > > On Mar 6, 2019, at 09:19, Noah Clay wrote: > > Mark, > > > > I have seen blackening on the back of the wafer when clamping is poor. > Most recently, this was due the e-chuck having been etched excessively > and/or polymer redep on the chuck from the endpoint clean step (cleans used > to be run without a wafer; we now use SiC). > > > > What are your backside He leak rate set points and actual values? We run > our etch process at -5C...(SPTS Rapier platform). > > > > Thanks, > > Noah > > Sent from my iPhone > > > On Mar 5, 2019, at 15:44, Mark Weiler wrote: > > Hello Everyone, > > > > We have gone through seven new lip seals purchased form Orbotech/SPTS. > They are often failing before we even finish qualifying the system, or > within a month thereafter. > > > > Our our process is stable with power and parameters not deviating over the > past decade. However, I ordered the most recent batch of lip seals because > the wafer seals we had been using were coming out with black residue after > only a few runs? however, the current ones do the same. Not only have the > lips seals disintegrated, but the chamber lid o-ring and bottom ceramic > spool o-ring have also failed with black rubber material shedding off. > It?s as if they are made of Buna and not meant for this application. > > > > Our process is typical Bosch with 100 sccm C4F8 and 20 sccm O2 for etching > switching off with ~50 Sccm SF6 for passivation at a processing pressure of > 15 mTorr, Coil power 600-800W, Platen power 100-150W, Bias voltage 50-100v > (up to 200 peak-to-peak), Platen temp at 19 degrees, Lid temp 41 degrees. > Qual wafers are new bare Silicon. Etch rates are normal and stable with > 10+ years of data?. we just can?t complete the work due to failing seals. > > > > Our chamber base pressure is between 1E-8 and 5E-8 Torr each morning. > When we put in a brand new seal and run only the LUR, it passes with 0.00 > mTorr/minute leak rate. That jumps to 3.00 mTorr/m after only 30 minutes > of the SPTS recommended O2 Clean? then rises as time and more runs > progress. Wafers are coming out with black rings on their backsides. > > > > This should not be happening, and I believe it is due to incorrect > material of the lip seals and o-rings. I am pinging the network, though, > to see if there might be a parameter change we need to effect that may > assist us. > > > > Have any of you seen this before? > > > > Best regards, > > > > Mark > > > > ________________________________________________________________ > > > > Mark Weiler > > Equipment & Facilites Manager > > Clair and John Bertucci Nanotechnology Laboratory > > Eden Hall Nanofabrication Cleanroom > > Carnegie Mellon University > > P: 412-268-2471 > > http://www.nanofab.ece.cmu.edu > > > > > > > > > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > -- Kevin Owen Senior Engineer in Research Operations Group, Lurie Nanofabrication Facility University of Michigan (734) 545-4014 -------------- next part -------------- An HTML attachment was scrubbed... URL: From christophe.clement at polymtl.ca Thu Mar 7 14:21:05 2019 From: christophe.clement at polymtl.ca (Christophe =?utf-8?Q?Cl=C3=A9ment?=) Date: Thu, 7 Mar 2019 14:21:05 -0500 (EST) Subject: [labnetwork] Gorilla glass Etching Message-ID: <307976345.2407675.1551986465550.JavaMail.zimbra@polymtl.ca> Hello Labnetwork community, I've been ask by a company to etch Gorilla Glass in our DRIE-ICP etcher (Oxford Plasmalab 100), where we already etch Si (regular Bosch process) and SiO2 etching (Fused silica only). As the supplier of the Gorilla glass does not share the composition of this kind of glass, I'm a little bit afraid of cross contamination (Potassium and other material that can be present in the glass) that can be found during Si etching for example. Is there anyone who has experienced etching this material? If yes, what is your cleaning procedure after etching Gorilla glass? Thank you in advance for your answer Best Christophe Christophe Cl?ment Technicien laboratoire Laboratoire de microfabrication (LMF) Groupe des Couches Minces (GCM) [ http://www.gcmlab.ca/ | www.gcmlab.ca ] Ecole Polytechnique de Montr?al [ http://www.polymtl.ca/ | www.polymtl.ca ] D?partement de g?nie physique * 2900 Boulevard Edouard Monpetit Pavillon JAB Campus de l'Universit? de Montr?al Montr?al (Qu?bec) H3T 1J4 8 [ mailto:christophe.clement at polymtl.ca | christophe.clement at polymtl.ca ] ( 514 340 4711 Fax : 514 340 4711 # 2417 -------------- next part -------------- An HTML attachment was scrubbed... URL: From kjvowen at lnf.umich.edu Thu Mar 7 17:05:34 2019 From: kjvowen at lnf.umich.edu (Kevin Owen) Date: Thu, 7 Mar 2019 17:05:34 -0500 Subject: [labnetwork] HSQ developer compatible with AlN for electron beam lithography (EBL) In-Reply-To: References: <69FD30F0-35D1-417C-8C07-5F70F5530F9F@andrew.cmu.edu> <26b2846d16984b939c5f8ade9e7336a9@dtu.dk> Message-ID: Edmond, For positive photoresists that develop in TMAH, we used to use CD-30 developer (an alkaline phosphate salt) when exposing AlN. It's no longer sold, I believe, but instead you can buy "Microposit Developer Concentrate" which is the same thing but needs dilution in DI to have the same concentration. I do not know if it would work for HSQ, I just know it worked for other TMAH-developed resists (e.g. SPR, S1800, etc). -Kevin On Wed, Mar 6, 2019 at 5:06 PM Edmond Chow wrote: > Hello, > > We are trying to pattern HSQ with EBL on AlN film substrate,. We typically > use 2.2%TMAH (MF 319)as our HSQ developer. > However TMAH will attach AlN film and cause problem for our sample. > > Does anyone has some HSQ developer that is compatible with AlN? > > Thanks. > > Edmond > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > -- Kevin Owen Senior Engineer in Research Operations Group, Lurie Nanofabrication Facility University of Michigan (734) 545-4014 -------------- next part -------------- An HTML attachment was scrubbed... URL: From adrian.cavazos at kaust.edu.sa Thu Mar 7 21:27:01 2019 From: adrian.cavazos at kaust.edu.sa (=?UTF-8?B?QWRyacOhbiBDw6lzYXIgQ2F2YXpvcyBTZXDDumx2ZWRh?=) Date: Thu, 7 Mar 2019 20:27:01 -0600 Subject: [labnetwork] Gorilla glass Etching In-Reply-To: <307976345.2407675.1551986465550.JavaMail.zimbra@polymtl.ca> References: <307976345.2407675.1551986465550.JavaMail.zimbra@polymtl.ca> Message-ID: Hi Christophe, To check for the composition, you can use an SEM with EDX/EDS. If sodium and potassium X-contamination is not a problem, and the glass is mainly Al2O3-SiO2, you could use preexisting etch recipes or a mixture of them (e.g. CHF3/Ar in 4:1) . Bests, Adri?n Cavazos Sep?lveda ------------------------------ This message and its contents, including attachments are intended solely for the original recipient. If you are not the intended recipient or have received this message in error, please notify me immediately and delete this message from your computer system. Any unauthorized use or distribution is prohibited. Please consider the environment before printing this email. Am Do., 7. M?rz 2019 um 18:49 Uhr schrieb Christophe Cl?ment < christophe.clement at polymtl.ca>: > Hello Labnetwork community, > I've been ask by a company to etch Gorilla Glass in our DRIE-ICP etcher > (Oxford Plasmalab 100), where we already etch Si (regular Bosch process) > and SiO2 etching (Fused silica only). As the supplier of the Gorilla glass > does not share the composition of this kind of glass, I'm a little bit > afraid of cross contamination (Potassium and other material that can be > present in the glass) that can be found during Si etching for example. > Is there anyone who has experienced etching this material? If yes, what is > your cleaning procedure after etching Gorilla glass? > > Thank you in advance for your answer > Best > Christophe > > *Christophe Cl?ment* > > *Technicien laboratoire* > > Laboratoire de microfabrication (LMF) > > Groupe des Couches Minces (GCM) *www.gcmlab.ca * > > Ecole Polytechnique de Montr?al www.polymtl.ca > > D?partement de g?nie physique > > * 2900 Boulevard Edouard Monpetit > > Pavillon JAB > Campus de l'Universit? de Montr?al > Montr?al (Qu?bec) H3T 1J4 > > > 8 christophe.clement at polymtl.ca > > ( 514 340 4711 > > Fax : 514 340 4711 # 2417 > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > -------------- next part -------------- An HTML attachment was scrubbed... URL: From bill_flounders at berkeley.edu Thu Mar 7 22:02:21 2019 From: bill_flounders at berkeley.edu (A. William (Bill) FLOUNDERS) Date: Thu, 7 Mar 2019 19:02:21 -0800 Subject: [labnetwork] Equipment Engineering Position Message-ID: Lab Network, The UC Berkeley NanoLab has been seeking an R&D3 engineer for several months. This engineer would join the NanoLab Equipment Engineering and Support team. As colleagues on this network know, these are unique and demanding positions. Lab Network academic laboratory engineering positions require a broad range of experience and a willingness to to learn as much as the expert who designed the tool with each new repair or rebuild challenge. This specific position is not a process engineering specialist nor an academic research appointment. This position is ideal for a hands on, mechanically inclined individual who likes to take equipment apart - and call upon an in-house custom machine shop to make improved parts - then put things back together. The selected candidate is likely more comfortable with a wrench than tweezers, uses an oscilloscope more than a spectrometer, and takes pride in tool performance and custom capabilities more than publications or conferences. Our job posting is here: https://nanolab.berkeley.edu/public/general/opportunities.shtml If you're considering relocation to the SF Bay Area, take a look. Sincerely, Bill Flounders, Ph.D. Executive Director Berkeley NanoLab -------------- next part -------------- An HTML attachment was scrubbed... URL: From sguo18 at yorku.ca Fri Mar 8 14:49:40 2019 From: sguo18 at yorku.ca (Xin (Shane) Guo) Date: Fri, 8 Mar 2019 19:49:40 +0000 Subject: [labnetwork] Universal standards of microfab enviornment In-Reply-To: References: Message-ID: Hi Steven, That's great information! I think a RH of 45% and temperature of 20+/-2oC will work for most of our applications. Cheers Shane On Wed, Mar 6, 2019 at 5:21 PM Paolini, Steven > wrote: Shane, The most often referenced material is from SEMI standards. Semistandards.org Whatever criteria you adopt, please note that it is of the utmost importance to ensure consistency. If temperature and RH vary, it will introduce unwanted variables in sensitive and complex processes. Another important point is to keep the RH relatively high (48%) to reduce ESD. If the RH and temperature fluctuate, you will encounter variation in your photo speed. Hope this helps. Steve Steve Paolini Principal Equipment Engineer Harvard University Center for Nanoscale Systems 11 Oxford St. Cambridge, MA 02138 617- 496- 9816 spaolini at cns.fas.harvard.edu www.cns.fas.harvard.edu From: labnetwork-bounces at mtl.mit.edu > On Behalf Of Xin (Shane) Guo Sent: Wednesday, March 06, 2019 1:30 PM To: labnetwork at mtl.mit.edu Subject: [labnetwork] Universal standards of microfab enviornment Hi Colleagues, Is there a universal standard for microfabrication cleanroom, outlining the requirement of humidity, temperature, noise, etc? Any documentation available? Cheers Shane -- Shane GUO, PhD Facility Manager SPaRC Microfabrication Laboratory York University | Bergeron Centre for Engineering Excellence | Office: BRG037 a: 4700 Keele St., 11 Arboretum Ln., Toronto, ON, Canada M3J 1P3 p: +1 416-736-2100x44160 e: sguo18 at yorku.ca -------------- next part -------------- An HTML attachment was scrubbed... URL: From lrehn at tamu.edu Fri Mar 8 15:29:59 2019 From: lrehn at tamu.edu (Rehn, Larry A) Date: Fri, 8 Mar 2019 20:29:59 +0000 Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures In-Reply-To: References: <5BAB86D2-F5F3-42DB-B6EF-4B6DCF676555@andrew.cmu.edu> Message-ID: <08e1ef8ef7104e35a82003d35e072474@tamu.edu> Let me tag on to the topic of STS Multiplex tools with another question. We are in the process to bring up a tool that has been running the Bosch etch process. We noticed some build-up of white coating inside the vacuum lines and valves from the chamber. Can someone recommend a best practice to remove and clean surfaces of this material? Are there any particular cautions or safety concerns? Thanks in advance. Larry A Rehn Technical Lab Manager AggieFab Nanofabrication Facility Texas A&M University 979 845-3199 lrehn at tamu.edu [cid:image001.jpg at 01CEC37D.FAF8C9E0] From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Kevin Owen Sent: Thursday, March 07, 2019 12:45 PM To: Paolini, Steven Cc: Fab Network Subject: Re: [labnetwork] STS DRIE Multiplex Lip Seal failures We don't have lip seals on our SPTS systems, but I do agree that Kalrez is the way to go for o-rings. All of the source o-rings for the Pegasus were Kalrez to begin with. Well, except for a couple that were called out in the BOM as Kalrez but weren't... this was remedied. I also replaced our lid seals with Kalrez about a year ago and it was definitely a Good Decision. I wound up going with the 9300 series for the Bosch process equipment. Used to source them through Bay Seal, who was even able to make the custom size for the lid seal (it's not actually a 280, just seems like it should be), without the crazy tooling cost for most custom sizes. Recently, they suggested I find a distributor closer to my area, and I went with James Walker in Chicago, which seemed to work well for my last order. The one case I've found where this did not work as expected was the lid o-ring in our APS tool. I think it is because we tend to excessively over-clean the chamber to accommodate some "dirtier" processes, the Kalrez o-ring actually got substantially eaten away after only about 6 months. I wonder if this could also be related to some of the lip seal issues (not saying they didn't switch to a "cheaper" material also), but it might be that over-using O2 cleans could shorten the life further like it did to my o-ring. -Kevin On Wed, Mar 6, 2019 at 7:51 PM Paolini, Steven > wrote: My $0.02, Black marks on the back of a wafer are not normal. I agree that there must have been a material change by the supplier perhaps to ?value engineer? there consumables. What IS normal is O-rings growing a black crud on their surfaces. This is simply O2 attacking organics regardless of the O-rings being out of the ? line of sight? of the plasma. A downstream etcher (two 90 degree gas shifts), will experience the same effect at a slower rate. We inspect them and if not cracked, we clean them up until the wipes show minimum crud and put them back in for more service. Oh yeah, I wholeheartedly agree with Julia that we should not forget that the LUR with backside He is the overall LUR of the chamber and you could be mislead by some other fine leak not associated with the He seal. Steve Paolini Principal Equipment Engineer Harvard University Center for Nanoscale Systems 11 Oxford St. Cambridge, MA 02138 617- 496- 9816 spaolini at cns.fas.harvard.edu www.cns.fas.harvard.edu From: labnetwork-bounces at mtl.mit.edu > On Behalf Of Mark Weiler Sent: Wednesday, March 06, 2019 10:18 AM To: Noah Clay > Cc: Fab Network > Subject: Re: [labnetwork] STS DRIE Multiplex Lip Seal failures Hi Noah, We have the first version of the 100mm STS Multiplex DRIE whereby the wafer is mechanically clamped with weighted ceramic fingers, and the wafer is lifted with a tripod. Our LUR is 0.00 mTorr/min when new, but rises to 15-20 mT/m within a week. We have an older HBC controller that indicates 6.5 for pressure at 2.33 flow rate... I apologize but don?t know the units for either. If these values are incorrect, it could be because they were adjusted to ensure a leak rate would pass. I will need to go back over a decade in the logs to see if any changes were made over time...but, our rates and results have been consistent. I believe the issue is material related, because we have our chamber lid o-ring and bottom ceramic o-ring failing with the same symptoms. Thanks, Mark Mark Weiler Equipment & Facilities Manager Claire and John Bertucci Nanotechnology Laboratory Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.2471 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu On Mar 6, 2019, at 09:19, Noah Clay > wrote: Mark, I have seen blackening on the back of the wafer when clamping is poor. Most recently, this was due the e-chuck having been etched excessively and/or polymer redep on the chuck from the endpoint clean step (cleans used to be run without a wafer; we now use SiC). What are your backside He leak rate set points and actual values? We run our etch process at -5C...(SPTS Rapier platform). Thanks, Noah Sent from my iPhone On Mar 5, 2019, at 15:44, Mark Weiler > wrote: Hello Everyone, We have gone through seven new lip seals purchased form Orbotech/SPTS. They are often failing before we even finish qualifying the system, or within a month thereafter. Our our process is stable with power and parameters not deviating over the past decade. However, I ordered the most recent batch of lip seals because the wafer seals we had been using were coming out with black residue after only a few runs? however, the current ones do the same. Not only have the lips seals disintegrated, but the chamber lid o-ring and bottom ceramic spool o-ring have also failed with black rubber material shedding off. It?s as if they are made of Buna and not meant for this application. Our process is typical Bosch with 100 sccm C4F8 and 20 sccm O2 for etching switching off with ~50 Sccm SF6 for passivation at a processing pressure of 15 mTorr, Coil power 600-800W, Platen power 100-150W, Bias voltage 50-100v (up to 200 peak-to-peak), Platen temp at 19 degrees, Lid temp 41 degrees. Qual wafers are new bare Silicon. Etch rates are normal and stable with 10+ years of data?. we just can?t complete the work due to failing seals. Our chamber base pressure is between 1E-8 and 5E-8 Torr each morning. When we put in a brand new seal and run only the LUR, it passes with 0.00 mTorr/minute leak rate. That jumps to 3.00 mTorr/m after only 30 minutes of the SPTS recommended O2 Clean? then rises as time and more runs progress. Wafers are coming out with black rings on their backsides. This should not be happening, and I believe it is due to incorrect material of the lip seals and o-rings. I am pinging the network, though, to see if there might be a parameter change we need to effect that may assist us. Have any of you seen this before? Best regards, Mark ________________________________________________________________ Mark Weiler Equipment & Facilites Manager Clair and John Bertucci Nanotechnology Laboratory Eden Hall Nanofabrication Cleanroom Carnegie Mellon University P: 412-268-2471 http://www.nanofab.ece.cmu.edu _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -- Kevin Owen Senior Engineer in Research Operations Group, Lurie Nanofabrication Facility University of Michigan (734) 545-4014 -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.jpg Type: image/jpeg Size: 13188 bytes Desc: image001.jpg URL: From spaolini at cns.fas.harvard.edu Fri Mar 8 16:02:46 2019 From: spaolini at cns.fas.harvard.edu (Paolini, Steven) Date: Fri, 8 Mar 2019 21:02:46 +0000 Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures In-Reply-To: <08e1ef8ef7104e35a82003d35e072474@tamu.edu> References: <5BAB86D2-F5F3-42DB-B6EF-4B6DCF676555@andrew.cmu.edu> <08e1ef8ef7104e35a82003d35e072474@tamu.edu> Message-ID: That?s an expected byproduct of the polymer during the dep step. We heat the foreline all the way to the pump to control the growth. Cleaning is via a HEPA vac followed with a water wipe. My partner Dave LaFleur has developed an interesting and effective technique in that he places a clean wafer on the chuck before closing the chamber and pumping it down. The wafer prevents any stray particles disturbed during the turbulent rough out from landing on the ESC and giving us backside helium problems. Respiratory protection is recommended when working with any fine powder. I am unaware if there are any toxins in the powder but the HEPA vac and wet wipe prevents us from exposure. Best of luck, Steve Steve Paolini Principal Equipment Engineer Harvard University Center for Nanoscale Systems 11 Oxford St. Cambridge, MA 02138 617- 496- 9816 spaolini at cns.fas.harvard.edu www.cns.fas.harvard.edu From: Rehn, Larry A Sent: Friday, March 08, 2019 3:30 PM To: Kevin Owen ; Paolini, Steven Cc: Fab Network Subject: RE: [labnetwork] STS DRIE Multiplex Lip Seal failures Let me tag on to the topic of STS Multiplex tools with another question. We are in the process to bring up a tool that has been running the Bosch etch process. We noticed some build-up of white coating inside the vacuum lines and valves from the chamber. Can someone recommend a best practice to remove and clean surfaces of this material? Are there any particular cautions or safety concerns? Thanks in advance. Larry A Rehn Technical Lab Manager AggieFab Nanofabrication Facility Texas A&M University 979 845-3199 lrehn at tamu.edu [cid:image001.jpg at 01CEC37D.FAF8C9E0] From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Kevin Owen Sent: Thursday, March 07, 2019 12:45 PM To: Paolini, Steven > Cc: Fab Network > Subject: Re: [labnetwork] STS DRIE Multiplex Lip Seal failures We don't have lip seals on our SPTS systems, but I do agree that Kalrez is the way to go for o-rings. All of the source o-rings for the Pegasus were Kalrez to begin with. Well, except for a couple that were called out in the BOM as Kalrez but weren't... this was remedied. I also replaced our lid seals with Kalrez about a year ago and it was definitely a Good Decision. I wound up going with the 9300 series for the Bosch process equipment. Used to source them through Bay Seal, who was even able to make the custom size for the lid seal (it's not actually a 280, just seems like it should be), without the crazy tooling cost for most custom sizes. Recently, they suggested I find a distributor closer to my area, and I went with James Walker in Chicago, which seemed to work well for my last order. The one case I've found where this did not work as expected was the lid o-ring in our APS tool. I think it is because we tend to excessively over-clean the chamber to accommodate some "dirtier" processes, the Kalrez o-ring actually got substantially eaten away after only about 6 months. I wonder if this could also be related to some of the lip seal issues (not saying they didn't switch to a "cheaper" material also), but it might be that over-using O2 cleans could shorten the life further like it did to my o-ring. -Kevin On Wed, Mar 6, 2019 at 7:51 PM Paolini, Steven > wrote: My $0.02, Black marks on the back of a wafer are not normal. I agree that there must have been a material change by the supplier perhaps to ?value engineer? there consumables. What IS normal is O-rings growing a black crud on their surfaces. This is simply O2 attacking organics regardless of the O-rings being out of the ? line of sight? of the plasma. A downstream etcher (two 90 degree gas shifts), will experience the same effect at a slower rate. We inspect them and if not cracked, we clean them up until the wipes show minimum crud and put them back in for more service. Oh yeah, I wholeheartedly agree with Julia that we should not forget that the LUR with backside He is the overall LUR of the chamber and you could be mislead by some other fine leak not associated with the He seal. Steve Paolini Principal Equipment Engineer Harvard University Center for Nanoscale Systems 11 Oxford St. Cambridge, MA 02138 617- 496- 9816 spaolini at cns.fas.harvard.edu www.cns.fas.harvard.edu From: labnetwork-bounces at mtl.mit.edu > On Behalf Of Mark Weiler Sent: Wednesday, March 06, 2019 10:18 AM To: Noah Clay > Cc: Fab Network > Subject: Re: [labnetwork] STS DRIE Multiplex Lip Seal failures Hi Noah, We have the first version of the 100mm STS Multiplex DRIE whereby the wafer is mechanically clamped with weighted ceramic fingers, and the wafer is lifted with a tripod. Our LUR is 0.00 mTorr/min when new, but rises to 15-20 mT/m within a week. We have an older HBC controller that indicates 6.5 for pressure at 2.33 flow rate... I apologize but don?t know the units for either. If these values are incorrect, it could be because they were adjusted to ensure a leak rate would pass. I will need to go back over a decade in the logs to see if any changes were made over time...but, our rates and results have been consistent. I believe the issue is material related, because we have our chamber lid o-ring and bottom ceramic o-ring failing with the same symptoms. Thanks, Mark Mark Weiler Equipment & Facilities Manager Claire and John Bertucci Nanotechnology Laboratory Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.2471 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu On Mar 6, 2019, at 09:19, Noah Clay > wrote: Mark, I have seen blackening on the back of the wafer when clamping is poor. Most recently, this was due the e-chuck having been etched excessively and/or polymer redep on the chuck from the endpoint clean step (cleans used to be run without a wafer; we now use SiC). What are your backside He leak rate set points and actual values? We run our etch process at -5C...(SPTS Rapier platform). Thanks, Noah Sent from my iPhone On Mar 5, 2019, at 15:44, Mark Weiler > wrote: Hello Everyone, We have gone through seven new lip seals purchased form Orbotech/SPTS. They are often failing before we even finish qualifying the system, or within a month thereafter. Our our process is stable with power and parameters not deviating over the past decade. However, I ordered the most recent batch of lip seals because the wafer seals we had been using were coming out with black residue after only a few runs? however, the current ones do the same. Not only have the lips seals disintegrated, but the chamber lid o-ring and bottom ceramic spool o-ring have also failed with black rubber material shedding off. It?s as if they are made of Buna and not meant for this application. Our process is typical Bosch with 100 sccm C4F8 and 20 sccm O2 for etching switching off with ~50 Sccm SF6 for passivation at a processing pressure of 15 mTorr, Coil power 600-800W, Platen power 100-150W, Bias voltage 50-100v (up to 200 peak-to-peak), Platen temp at 19 degrees, Lid temp 41 degrees. Qual wafers are new bare Silicon. Etch rates are normal and stable with 10+ years of data?. we just can?t complete the work due to failing seals. Our chamber base pressure is between 1E-8 and 5E-8 Torr each morning. When we put in a brand new seal and run only the LUR, it passes with 0.00 mTorr/minute leak rate. That jumps to 3.00 mTorr/m after only 30 minutes of the SPTS recommended O2 Clean? then rises as time and more runs progress. Wafers are coming out with black rings on their backsides. This should not be happening, and I believe it is due to incorrect material of the lip seals and o-rings. I am pinging the network, though, to see if there might be a parameter change we need to effect that may assist us. Have any of you seen this before? Best regards, Mark ________________________________________________________________ Mark Weiler Equipment & Facilites Manager Clair and John Bertucci Nanotechnology Laboratory Eden Hall Nanofabrication Cleanroom Carnegie Mellon University P: 412-268-2471 http://www.nanofab.ece.cmu.edu _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -- Kevin Owen Senior Engineer in Research Operations Group, Lurie Nanofabrication Facility University of Michigan (734) 545-4014 -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.jpg Type: image/jpeg Size: 13188 bytes Desc: image001.jpg URL: From mengdiz2 at illinois.edu Sat Mar 9 00:02:44 2019 From: mengdiz2 at illinois.edu (Zhao, Mengdi) Date: Sat, 9 Mar 2019 05:02:44 +0000 Subject: [labnetwork] Has anyone using thicker than 200nm HSQ for EBL patterning? Message-ID: Hello everyone, I am trying to spin 350nm HSQ by double coating XR1541 6% at 2000rpm and bake at 80C between coating. However, HSQ thickness measured by reflectance spectrum actually get thinner after the second spin and bake. I wonder if the HSQ still get dissolved again during the 2nd dispense even with 80C bake for 4min after the first coating. Any suggestion on getting over 200nm HSQ spin coated on Si? Best regards, Mengdi -------------- next part -------------- An HTML attachment was scrubbed... URL: From michael.rooks at yale.edu Sat Mar 9 08:50:58 2019 From: michael.rooks at yale.edu (Michael Rooks) Date: Sat, 9 Mar 2019 06:50:58 -0700 Subject: [labnetwork] Has anyone using thicker than 200nm HSQ for EBL patterning? In-Reply-To: References: Message-ID: <4270623f-ea5c-a49f-e737-543acb5e07c3@yale.edu> Multiple-spins seldom produce good results. It's easier to use a thicker solution of HSQ. Of course you can buy thicker HSQ, such as Fox-16, but if you are in a hurry you can thicken the 6% HSQ (well, any resist really) by bubbling nitrogen through it. Just put a tube in the bottle and blow in some dry nitrogen. The solvent will evaporate, and the bubbles will keep the solution agitated, so a skin does not form on the surface. No need to be precise about the solution. Just keep bubbling until you get the thickness you want. ------------------------------------ Michael Rooks Yale Institute for Nanoscience and Quantum Engineering nano.yale.edu On 3/8/2019 10:02 PM, Zhao, Mengdi wrote: > > Hello everyone, > > > I am trying to spin 350nm HSQ by double coating XR1541 6% at 2000rpm > and bake at 80C between coating. However, HSQ thickness measured by > reflectance spectrum actually get thinner after the second spin and > bake. I wonder if the HSQ still get dissolved again during the 2nd > dispense even with 80C bake for 4min after the first coating. Any > suggestion on getting over 200nm HSQ spin coated on Si? > > > Best regards, > > > Mengdi > > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From sangeethk9 at gmail.com Sat Mar 9 12:01:53 2019 From: sangeethk9 at gmail.com (sangeeth kallatt) Date: Sat, 9 Mar 2019 22:31:53 +0530 Subject: [labnetwork] Has anyone using thicker than 200nm HSQ for EBL patterning? In-Reply-To: References: Message-ID: Hello Mengdi, You can avoid the heating step. For this Silicon polymer, film quality degrades even with low-temperature baking. Also, the solvent (MIBK) evaporates quite easily. Nevertheless, I have seen that the thickness of the film gets added up, with multiple coating. Hope this helps!!! Regards, Sangeeth On Sat, Mar 9, 2019 at 7:11 PM Zhao, Mengdi wrote: > Hello everyone, > > > I am trying to spin 350nm HSQ by double coating XR1541 6% at 2000rpm and > bake at 80C between coating. However, HSQ thickness measured by reflectance > spectrum actually get thinner after the second spin and bake. I wonder if > the HSQ still get dissolved again during the 2nd dispense even with 80C > bake for 4min after the first coating. Any suggestion on getting over 200nm > HSQ spin coated on Si? > > > Best regards, > > > Mengdi > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > -- Sangeeth Kallatt Department of Electrical Communication Engineering Indian Institute of Science Bangalore-12 -------------- next part -------------- An HTML attachment was scrubbed... URL: From mondol at mit.edu Sat Mar 9 17:05:56 2019 From: mondol at mit.edu (Mark K Mondol) Date: Sat, 9 Mar 2019 22:05:56 +0000 Subject: [labnetwork] Has anyone using thicker than 200nm HSQ for EBL patterning? In-Reply-To: <4270623f-ea5c-a49f-e737-543acb5e07c3@yale.edu> References: , <4270623f-ea5c-a49f-e737-543acb5e07c3@yale.edu> Message-ID: <1DE742C03F382B44848ED7C52E4C3E41C13F3170@OC11EXPO30.exchange.mit.edu> As usual I agree with Mike, but have to chime in anyway. Applied Quantum Materials in Canada offers dry HSQ, which you mix with MIBK to make a solution. I just got some and haven't used it yet, but others have. As it is dry you can make whatever dilution you want to achieve thicker films. ________________________________ From: labnetwork-bounces at mtl.mit.edu [labnetwork-bounces at mtl.mit.edu] on behalf of Michael Rooks [michael.rooks at yale.edu] Sent: Saturday, March 09, 2019 8:50 AM To: labnetwork at mtl.mit.edu Subject: Re: [labnetwork] Has anyone using thicker than 200nm HSQ for EBL patterning? Multiple-spins seldom produce good results. It's easier to use a thicker solution of HSQ. Of course you can buy thicker HSQ, such as Fox-16, but if you are in a hurry you can thicken the 6% HSQ (well, any resist really) by bubbling nitrogen through it. Just put a tube in the bottle and blow in some dry nitrogen. The solvent will evaporate, and the bubbles will keep the solution agitated, so a skin does not form on the surface. No need to be precise about the solution. Just keep bubbling until you get the thickness you want. ------------------------------------ Michael Rooks Yale Institute for Nanoscience and Quantum Engineering nano.yale.edu On 3/8/2019 10:02 PM, Zhao, Mengdi wrote: Hello everyone, I am trying to spin 350nm HSQ by double coating XR1541 6% at 2000rpm and bake at 80C between coating. However, HSQ thickness measured by reflectance spectrum actually get thinner after the second spin and bake. I wonder if the HSQ still get dissolved again during the 2nd dispense even with 80C bake for 4min after the first coating. Any suggestion on getting over 200nm HSQ spin coated on Si? Best regards, Mengdi _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From mengdiz2 at illinois.edu Sat Mar 9 23:26:35 2019 From: mengdiz2 at illinois.edu (Zhao, Mengdi) Date: Sun, 10 Mar 2019 04:26:35 +0000 Subject: [labnetwork] Has anyone using thicker than 200nm HSQ for EBL patterning? In-Reply-To: <4270623f-ea5c-a49f-e737-543acb5e07c3@yale.edu> References: , <4270623f-ea5c-a49f-e737-543acb5e07c3@yale.edu> Message-ID: Hi Michael, That sounds like an easy way to get a thicker HSQ solution. We will definitely give it a try. Thank you! Best regards, Mengdi ________________________________ From: labnetwork-bounces at mtl.mit.edu on behalf of Michael Rooks Sent: Saturday, March 9, 2019 7:50 AM To: labnetwork at mtl.mit.edu Subject: Re: [labnetwork] Has anyone using thicker than 200nm HSQ for EBL patterning? Multiple-spins seldom produce good results. It's easier to use a thicker solution of HSQ. Of course you can buy thicker HSQ, such as Fox-16, but if you are in a hurry you can thicken the 6% HSQ (well, any resist really) by bubbling nitrogen through it. Just put a tube in the bottle and blow in some dry nitrogen. The solvent will evaporate, and the bubbles will keep the solution agitated, so a skin does not form on the surface. No need to be precise about the solution. Just keep bubbling until you get the thickness you want. ------------------------------------ Michael Rooks Yale Institute for Nanoscience and Quantum Engineering nano.yale.edu On 3/8/2019 10:02 PM, Zhao, Mengdi wrote: Hello everyone, I am trying to spin 350nm HSQ by double coating XR1541 6% at 2000rpm and bake at 80C between coating. However, HSQ thickness measured by reflectance spectrum actually get thinner after the second spin and bake. I wonder if the HSQ still get dissolved again during the 2nd dispense even with 80C bake for 4min after the first coating. Any suggestion on getting over 200nm HSQ spin coated on Si? Best regards, Mengdi _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From price.798 at osu.edu Mon Mar 11 10:03:21 2019 From: price.798 at osu.edu (Price, Aimee) Date: Mon, 11 Mar 2019 14:03:21 +0000 Subject: [labnetwork] VMS and/or Compaq/DEC experts Message-ID: All, Is anyone out there, or do you know anyone/have a source who is, a VMS and/or Compaq(HP or DEC) expert? I'm looking for a consultant, either on the phone or preferably in person. I have an Compaq/DEC Alpha XP900 running open VMS for my Raith (Leica/Vistec) EBPG5000 ebeam lithography tool. One of the two hard disks failed and 3 tape drives have failed. We have another tape drive on order ... I have a replacement hard disk and backup tapes (though fewer now after the failed tape drives destroyed two) and a backup file on our network, which can be moved to the system drive. However, I'm running up against my lack of VMS knowledge. For completeness, there is also a CD-ROM drive and a floppy. We are running Open VMS 7.2. If anyone has a contact or would be interested on working on something like this, please let me know. Alternatively, if anyone has a contact that can repair or recover hard disks of this type, I would be more than appreciative. Thanks much, Aimee Bross Price Sr. Research Associate The Ohio State University Nanotech West Lab Institute for Materials Research 1381 Kinnear Road Suite 100 Columbus, OH 43212 614-292-2753 -------------- next part -------------- An HTML attachment was scrubbed... URL: From james.beall at nist.gov Mon Mar 11 13:50:00 2019 From: james.beall at nist.gov (Beall, James A. (Fed)) Date: Mon, 11 Mar 2019 17:50:00 +0000 Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures In-Reply-To: References: <5BAB86D2-F5F3-42DB-B6EF-4B6DCF676555@andrew.cmu.edu> <08e1ef8ef7104e35a82003d35e072474@tamu.edu> Message-ID: I?m not a chemist but recall that this was been discussed a while back. See email copied from Steve Pritchett below. Gloves and a fume hood sound like a good idea. Jim From: Steve Pritchett > Subject: Re: [labnetwork] Cleaning of cold trap from DRIE system Date: June 21, 2016 at 9:19:15 AM MDT To: "Lino Eugene, Dr" >, "labnetwork at mtl.mit.edu" > Hi Lino, I have used the LN2 method to clean out a bellows on a DRIE system. It did cause the deposits to flake off with ends capped and shaking. Per safety instruction we did this in a fume hood and disposed of deposits as hazardous waste due to toxic S2F10 etch byproducts. In hind sight if my time is worth anything it was not very cost effective. I just didn't have a spare bellows on-hand and time was a consideration. Good luck, Steve Pritchett Sr Process Eng. Utah nanofab Ph: 801-587-0684 Jim Beall National Institute of Standards and Technology Quantum Sensors Group Mailcode 687.08 325 Broadway 1C-110 Boulder, CO 80305-3328 303-497-5989 303-497-3042 (fax) On Mar 8, 2019, at 2:02 PM, Paolini, Steven > wrote: That?s an expected byproduct of the polymer during the dep step. We heat the foreline all the way to the pump to control the growth. Cleaning is via a HEPA vac followed with a water wipe. My partner Dave LaFleur has developed an interesting and effective technique in that he places a clean wafer on the chuck before closing the chamber and pumping it down. The wafer prevents any stray particles disturbed during the turbulent rough out from landing on the ESC and giving us backside helium problems. Respiratory protection is recommended when working with any fine powder. I am unaware if there are any toxins in the powder but the HEPA vac and wet wipe prevents us from exposure. Best of luck, Steve Steve Paolini Principal Equipment Engineer Harvard University Center for Nanoscale Systems 11 Oxford St. Cambridge, MA 02138 617- 496- 9816 spaolini at cns.fas.harvard.edu www.cns.fas.harvard.edu From: Rehn, Larry A > Sent: Friday, March 08, 2019 3:30 PM To: Kevin Owen >; Paolini, Steven > Cc: Fab Network > Subject: RE: [labnetwork] STS DRIE Multiplex Lip Seal failures Let me tag on to the topic of STS Multiplex tools with another question. We are in the process to bring up a tool that has been running the Bosch etch process. We noticed some build-up of white coating inside the vacuum lines and valves from the chamber. Can someone recommend a best practice to remove and clean surfaces of this material? Are there any particular cautions or safety concerns? Thanks in advance. Larry A Rehn Technical Lab Manager AggieFab Nanofabrication Facility Texas A&M University 979 845-3199 lrehn at tamu.edu From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Kevin Owen Sent: Thursday, March 07, 2019 12:45 PM To: Paolini, Steven > Cc: Fab Network > Subject: Re: [labnetwork] STS DRIE Multiplex Lip Seal failures We don't have lip seals on our SPTS systems, but I do agree that Kalrez is the way to go for o-rings. All of the source o-rings for the Pegasus were Kalrez to begin with. Well, except for a couple that were called out in the BOM as Kalrez but weren't... this was remedied. I also replaced our lid seals with Kalrez about a year ago and it was definitely a Good Decision. I wound up going with the 9300 series for the Bosch process equipment. Used to source them through Bay Seal, who was even able to make the custom size for the lid seal (it's not actually a 280, just seems like it should be), without the crazy tooling cost for most custom sizes. Recently, they suggested I find a distributor closer to my area, and I went with James Walker in Chicago, which seemed to work well for my last order. The one case I've found where this did not work as expected was the lid o-ring in our APS tool. I think it is because we tend to excessively over-clean the chamber to accommodate some "dirtier" processes, the Kalrez o-ring actually got substantially eaten away after only about 6 months. I wonder if this could also be related to some of the lip seal issues (not saying they didn't switch to a "cheaper" material also), but it might be that over-using O2 cleans could shorten the life further like it did to my o-ring. -Kevin On Wed, Mar 6, 2019 at 7:51 PM Paolini, Steven > wrote: My $0.02, Black marks on the back of a wafer are not normal. I agree that there must have been a material change by the supplier perhaps to ?value engineer? there consumables. What IS normal is O-rings growing a black crud on their surfaces. This is simply O2 attacking organics regardless of the O-rings being out of the ? line of sight? of the plasma. A downstream etcher (two 90 degree gas shifts), will experience the same effect at a slower rate. We inspect them and if not cracked, we clean them up until the wipes show minimum crud and put them back in for more service. Oh yeah, I wholeheartedly agree with Julia that we should not forget that the LUR with backside He is the overall LUR of the chamber and you could be mislead by some other fine leak not associated with the He seal. Steve Paolini Principal Equipment Engineer Harvard University Center for Nanoscale Systems 11 Oxford St. Cambridge, MA 02138 617- 496- 9816 spaolini at cns.fas.harvard.edu www.cns.fas.harvard.edu From: labnetwork-bounces at mtl.mit.edu > On Behalf Of Mark Weiler Sent: Wednesday, March 06, 2019 10:18 AM To: Noah Clay > Cc: Fab Network > Subject: Re: [labnetwork] STS DRIE Multiplex Lip Seal failures Hi Noah, We have the first version of the 100mm STS Multiplex DRIE whereby the wafer is mechanically clamped with weighted ceramic fingers, and the wafer is lifted with a tripod. Our LUR is 0.00 mTorr/min when new, but rises to 15-20 mT/m within a week. We have an older HBC controller that indicates 6.5 for pressure at 2.33 flow rate... I apologize but don?t know the units for either. If these values are incorrect, it could be because they were adjusted to ensure a leak rate would pass. I will need to go back over a decade in the logs to see if any changes were made over time...but, our rates and results have been consistent. I believe the issue is material related, because we have our chamber lid o-ring and bottom ceramic o-ring failing with the same symptoms. Thanks, Mark Mark Weiler Equipment & Facilities Manager Claire and John Bertucci Nanotechnology Laboratory Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.2471 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu On Mar 6, 2019, at 09:19, Noah Clay > wrote: Mark, I have seen blackening on the back of the wafer when clamping is poor. Most recently, this was due the e-chuck having been etched excessively and/or polymer redep on the chuck from the endpoint clean step (cleans used to be run without a wafer; we now use SiC). What are your backside He leak rate set points and actual values? We run our etch process at -5C...(SPTS Rapier platform). Thanks, Noah Sent from my iPhone On Mar 5, 2019, at 15:44, Mark Weiler > wrote: Hello Everyone, We have gone through seven new lip seals purchased form Orbotech/SPTS. They are often failing before we even finish qualifying the system, or within a month thereafter. Our our process is stable with power and parameters not deviating over the past decade. However, I ordered the most recent batch of lip seals because the wafer seals we had been using were coming out with black residue after only a few runs? however, the current ones do the same. Not only have the lips seals disintegrated, but the chamber lid o-ring and bottom ceramic spool o-ring have also failed with black rubber material shedding off. It?s as if they are made of Buna and not meant for this application. Our process is typical Bosch with 100 sccm C4F8 and 20 sccm O2 for etching switching off with ~50 Sccm SF6 for passivation at a processing pressure of 15 mTorr, Coil power 600-800W, Platen power 100-150W, Bias voltage 50-100v (up to 200 peak-to-peak), Platen temp at 19 degrees, Lid temp 41 degrees. Qual wafers are new bare Silicon. Etch rates are normal and stable with 10+ years of data?. we just can?t complete the work due to failing seals. Our chamber base pressure is between 1E-8 and 5E-8 Torr each morning. When we put in a brand new seal and run only the LUR, it passes with 0.00 mTorr/minute leak rate. That jumps to 3.00 mTorr/m after only 30 minutes of the SPTS recommended O2 Clean? then rises as time and more runs progress. Wafers are coming out with black rings on their backsides. This should not be happening, and I believe it is due to incorrect material of the lip seals and o-rings. I am pinging the network, though, to see if there might be a parameter change we need to effect that may assist us. Have any of you seen this before? Best regards, Mark ________________________________________________________________ Mark Weiler Equipment & Facilites Manager Clair and John Bertucci Nanotechnology Laboratory Eden Hall Nanofabrication Cleanroom Carnegie Mellon University P: 412-268-2471 http://www.nanofab.ece.cmu.edu _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -- Kevin Owen Senior Engineer in Research Operations Group, Lurie Nanofabrication Facility University of Michigan (734) 545-4014 _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://gcc01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fmtl.mit.edu%2Fmailman%2Flistinfo.cgi%2Flabnetwork&data=02%7C01%7Cjames.beall%40nist.gov%7C431d04cdf62d476ddfe608d6a432655b%7C2ab5d82fd8fa4797a93e054655c61dec%7C1%7C0%7C636876933694355318&sdata=rq022tcbL9M6nCnRBNRP8x6Fqz%2Bdu85Y%2Bt92MO6LMzM%3D&reserved=0 -------------- next part -------------- An HTML attachment was scrubbed... URL: From kurt.kupcho at wisc.edu Mon Mar 11 15:55:07 2019 From: kurt.kupcho at wisc.edu (Kurt Kupcho) Date: Mon, 11 Mar 2019 19:55:07 +0000 Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures In-Reply-To: <6181704F-4A5F-4A52-B386-7B6C505A5B1F@andrew.cmu.edu> References: <8395D872-145D-42D7-8D7D-558BAE91C048@cns.fas.harvard.edu> <6181704F-4A5F-4A52-B386-7B6C505A5B1F@andrew.cmu.edu> Message-ID: Hi Mark & David ? I was on vacation so I apologize for my late thoughts on this STS DRIE lipseal issue. I am the engineer in charge of the STS DRIE at UW-Madison. When I first started the lipseals were great ? throw one in the system and it would last about 6 months with no issues. Then about a few years ago we noticed that wafers would stick to new lipseals and pop-off causing the transfer system to miss. To fix this new issue at the time STS told us to do a lipseal burn, or what equates to a 10s O2 plasma of the exposed lipseal. The wafers stopped sticking then, but never had to do that before and still do to this day. First, piece of evidence that something was different. Then we also saw a greatly reduced lifetime of these lipseals from 6 months to weeks. Second, piece of evidence that something was different. So, I have been fighting with SPTS for several years now that something changed with their lipseals and they refuse to admit anything. What it comes down to is these tools are obsolete to them but they are happy to sell you a $250 lipseal if you still want it. However, we do not see black residue on the back of the wafer where it contacted the lipseal. Because the lipseals are so expensive and lasting a few weeks is not sustainable we reduced our O2 plasma clean times, which seems to increase the lipseal lifetime significantly. Mark, with that said we are very interested here at the UW in your effort to make your own lipseals. Please let me know how we can help and get involved in this endeavor with you. Best, Kurt --------------------------------------------------- Kurt Kupcho Process Engineer/Safety Officer NFC 1550 Engineering Drive ECB Room 3110 Madison, WI 53706 E: kurt.kupcho at wisc.edu T: 608-262-2982 [Nano-Fab_color-flush] From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Mark Weiler Sent: Wednesday, March 06, 2019 8:04 AM To: LaFleur, David W Cc: Fab Network Subject: Re: [labnetwork] STS DRIE Multiplex Lip Seal failures Hi David, I am currently working with an elastomer manufacturer to produce O-Rings and seals for the systems of a material that can withstand better temperature ranges and chemical attacks. If you would like, I can share the information with you and maybe you can join us in this endeavor. The cost for the tooling and mold is now at ~1900 dollars, but I have negotiated the seal price to around 130.00 ea. I have not yet tested this material but we are having a seal made specifically for the Bosch process and 02 cleans. It is my believe that Orbotech has changed suppliers, or has allowed their supplier to switch their material source without testing, all in an effort to shave costs. My new efforts have also yielded a lower cost (50%) for the ceramic components in the chamber. I will test these and get back with the lab network sharing the source and part number. Thank you for sharing your info; now I know we are not the only ones ?feeling the pain? so to speak and can officially commiserate... LOL Best, Mark Mark Weiler Equipment & Facilities Manager Claire and John Bertucci Nanotechnology Laboratory Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.2471 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu On Mar 6, 2019, at 08:46, LaFleur, David W > wrote: Hi Mark, We have an STS MP0579 ICP which uses the lip seals. It is used mostly for silicon and SiO2 etches with O2 cleans between uses. Most of our Bosch processes are run on SPTS Rapier which uses an ESC. That has its own set of issues. We find the lip seals don?t last more than 2-3 weeks in our system. Our chamber o-rings usually go for 2 months at best. I was thinking of changing to a kalrez o-ring and always wondered if they made a Kalrez lip seal. One suggestion on how to make them last longer is make sure they don?t get exposed to any solvents like Isopropyl when you are installing them. I want to say I am not happy with the longevity of the lip seals either and maybe we need to bring this to the attention of Orbotech/SPTS. Maybe they have a solution. Other than that they are good tools, very reliable, and heavily used here at Harvard. Because they are so heavily used with so many processes we find a biweekly chamber clean and lip seal replacement works well for everyone. This is why I have just lived with the lip seals as they are. Regards, David LaFleur Equipment Engineer CNS, Harvard University From: "labnetwork-bounces at mtl.mit.edu" > on behalf of Mark Weiler > Date: Tuesday, March 5, 2019 at 3:44 PM To: Fab Network > Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures Hello Everyone, We have gone through seven new lip seals purchased form Orbotech/SPTS. They are often failing before we even finish qualifying the system, or within a month thereafter. Our our process is stable with power and parameters not deviating over the past decade. However, I ordered the most recent batch of lip seals because the wafer seals we had been using were coming out with black residue after only a few runs? however, the current ones do the same. Not only have the lips seals disintegrated, but the chamber lid o-ring and bottom ceramic spool o-ring have also failed with black rubber material shedding off. It?s as if they are made of Buna and not meant for this application. Our process is typical Bosch with 100 sccm C4F8 and 20 sccm O2 for etching switching off with ~50 Sccm SF6 for passivation at a processing pressure of 15 mTorr, Coil power 600-800W, Platen power 100-150W, Bias voltage 50-100v (up to 200 peak-to-peak), Platen temp at 19 degrees, Lid temp 41 degrees. Qual wafers are new bare Silicon. Etch rates are normal and stable with 10+ years of data?. we just can?t complete the work due to failing seals. Our chamber base pressure is between 1E-8 and 5E-8 Torr each morning. When we put in a brand new seal and run only the LUR, it passes with 0.00 mTorr/minute leak rate. That jumps to 3.00 mTorr/m after only 30 minutes of the SPTS recommended O2 Clean? then rises as time and more runs progress. Wafers are coming out with black rings on their backsides. This should not be happening, and I believe it is due to incorrect material of the lip seals and o-rings. I am pinging the network, though, to see if there might be a parameter change we need to effect that may assist us. Have any of you seen this before? Best regards, Mark ________________________________________________________________ Mark Weiler Equipment & Facilites Manager Clair and John Bertucci Nanotechnology Laboratory Eden Hall Nanofabrication Cleanroom Carnegie Mellon University P: 412-268-2471 http://www.nanofab.ece.cmu.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.png Type: image/png Size: 39543 bytes Desc: image001.png URL: From matt at 3ctechnical.com Mon Mar 11 15:56:16 2019 From: matt at 3ctechnical.com (Matt Pace) Date: Mon, 11 Mar 2019 12:56:16 -0700 Subject: [labnetwork] VMS and/or Compaq/DEC experts In-Reply-To: References: Message-ID: <5c86bcca5691d0396e000001@polymail.io> Hi Aimee, Maybe try Mitch at Keyways - he did a lot of work for us as we transitioned from the old DEC PDP 11 computers to the PC upgrades on the GCA Steppers some time ago.? All the best, Matt --- Matt Pace 3c Technical matt at 3ctechnical.com ( matt at 3ctechnical.com ) www.3ctechnical.com ( http://www.3ctechnical.com/ ) 480-963-4559?voice On Mon, Mar 11th, 2019 at 7:3 AM, "Price, Aimee" wrote: > > > > All, > > > > > > > > > > > > Is anyone out there, or do you know anyone/have a source who is, a VMS > and/or Compaq(HP or DEC) expert?? I?m looking for a consultant, either on > the phone or preferably in person. > > > > > > > > > > > > > > > > ? > > > > > > > > I have an Compaq/DEC Alpha XP900 running open VMS for my Raith > (Leica/Vistec) EBPG5000 ebeam lithography tool.? One of the two hard disks > failed and 3 tape drives have failed. ??We have another tape drive on > order ? > > > > > > > > > > > > > > > > ? > > > > > > > > I have a replacement hard disk and backup tapes (though fewer now after > the failed tape drives destroyed two) and a backup file on our network, > which can be moved to the system drive.? However, I?m running up against > my lack of VMS knowledge.? > > > > > > > > > > > > > > > > ? > > > > > > > > For completeness, there is also a CD-ROM drive and a floppy.? We are > running Open VMS 7.2. > > > > > > > > > > > > > > > > ? > > > > > > > > If anyone has a contact or would be interested on working on something > like this, please let me know.? Alternatively, if anyone has a contact > that can repair or recover hard disks of this type, I would be more than > appreciative.? > > > > > > > > > > > > > > > > ? > > > > > > > > Thanks much, > > > > > > > > > > > > Aimee Bross Price > > > > > > > > > > > > > > > > ? > > > > > > > > > > > > ? > > > > > > > > > > > > ? > > > > > > > > Sr. Research Associate > > > > > > > > > > > > The Ohio State University > > > > > > > > > > > > Nanotech West Lab > > > > > > > > > > > > Institute for Materials Research > > > > > > > > > > > > 1381 Kinnear Road > > > > > > > > > > > > Suite 100 > > > > > > > > > > > > Columbus, OH 43212 > > > > > > > > > > > > 614-292-2753 > > > > > > > > > > > > > > > > ? > > > > > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From matt at 3ctechnical.com Mon Mar 11 16:01:41 2019 From: matt at 3ctechnical.com (Matt Pace) Date: Mon, 11 Mar 2019 13:01:41 -0700 Subject: [labnetwork] VMS and/or Compaq/DEC experts In-Reply-To: <5c86bcca5691d0396e000001@polymail.io> References: <5c86bcca5691d0396e000001@polymail.io> Message-ID: <5c86bdba5691d0396e000002@polymail.io> Oops - forgot to attache his contact info: Mitch Miller? Keyways, Inc. (formerly Computer Keyways) SINCE 1987 204 S. Third St.? Miamisburg, OH 45342 USA? --- Matt Pace 3c Technical matt at 3ctechnical.com ( matt at 3ctechnical.com ) www.3ctechnical.com ( http://www.3ctechnical.com/ ) 480-963-4559?voice On Mon, Mar 11th, 2019 at 12:56 PM, Matt Pace wrote: > > Hi Aimee, > > > Maybe try Mitch at Keyways - he did a lot of work for us as we > transitioned from the old DEC PDP 11 computers to the PC upgrades on the > GCA Steppers some time ago.? > > > All the best, > Matt > > > > > --- > > > > Matt Pace > > > > 3c Technical > > > > matt at 3ctechnical.com ( matt at 3ctechnical.com ) > > > > www.3ctechnical.com ( http://www.3ctechnical.com/ ) > > > > 480-963-4559?voice > > > > > On Mon, Mar 11th, 2019 at 7:3 AM, "Price, Aimee" < price.798 at osu.edu > > wrote: > > >> >> >> All, >> >> >> >> >> >> >> >> >> >> >> >> Is anyone out there, or do you know anyone/have a source who is, a VMS >> and/or Compaq(HP or DEC) expert?? I?m looking for a consultant, either on >> the phone or preferably in person. >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> ? >> >> >> >> >> >> >> >> I have an Compaq/DEC Alpha XP900 running open VMS for my Raith >> (Leica/Vistec) EBPG5000 ebeam lithography tool.? One of the two hard disks >> failed and 3 tape drives have failed. ??We have another tape drive on >> order ? >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> ? >> >> >> >> >> >> >> >> I have a replacement hard disk and backup tapes (though fewer now after >> the failed tape drives destroyed two) and a backup file on our network, >> which can be moved to the system drive.? However, I?m running up against >> my lack of VMS knowledge.? >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> ? >> >> >> >> >> >> >> >> For completeness, there is also a CD-ROM drive and a floppy.? We are >> running Open VMS 7.2. >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> ? >> >> >> >> >> >> >> >> If anyone has a contact or would be interested on working on something >> like this, please let me know.? Alternatively, if anyone has a contact >> that can repair or recover hard disks of this type, I would be more than >> appreciative.? >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> ? >> >> >> >> >> >> >> >> Thanks much, >> >> >> >> >> >> >> >> >> >> >> >> Aimee Bross Price >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> ? >> >> >> >> >> >> >> >> >> >> >> >> ? >> >> >> >> >> >> >> >> >> >> >> >> ? >> >> >> >> >> >> >> >> Sr. Research Associate >> >> >> >> >> >> >> >> >> >> >> >> The Ohio State University >> >> >> >> >> >> >> >> >> >> >> >> Nanotech West Lab >> >> >> >> >> >> >> >> >> >> >> >> Institute for Materials Research >> >> >> >> >> >> >> >> >> >> >> >> 1381 Kinnear Road >> >> >> >> >> >> >> >> >> >> >> >> Suite 100 >> >> >> >> >> >> >> >> >> >> >> >> Columbus, OH 43212 >> >> >> >> >> >> >> >> >> >> >> >> 614-292-2753 >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> ? >> >> >> >> >> >> >> > > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From mweiler at andrew.cmu.edu Mon Mar 11 16:32:56 2019 From: mweiler at andrew.cmu.edu (Mark Weiler) Date: Mon, 11 Mar 2019 20:32:56 +0000 Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures In-Reply-To: References: <8395D872-145D-42D7-8D7D-558BAE91C048@cns.fas.harvard.edu> <6181704F-4A5F-4A52-B386-7B6C505A5B1F@andrew.cmu.edu> Message-ID: <0E780989-ED17-46BA-B3FC-92932EDB936C@andrew.cmu.edu> Hi Kurt, I will let you know the results of the new seals? In the meantime, I am also creating an Argon lip seal conditioning recipe to see if it will be a kinder-gentler approach to seal conditioning. Mark ________________________________________________________________ Mark Weiler Equipment & Facilites Manager Clair and John Bertucci Nanotechnology Laboratory Eden Hall Nanofabrication Cleanroom Carnegie Mellon University P: 412-268-2471 http://www.nanofab.ece.cmu.edu [cid:2D2E01E3-CEC1-4F48-A845-224D8D7CED12 at wv.cc.cmu.edu] On Mar 11, 2019, at 3:55 PM, Kurt Kupcho > wrote: Hi Mark & David ? I was on vacation so I apologize for my late thoughts on this STS DRIE lipseal issue. I am the engineer in charge of the STS DRIE at UW-Madison. When I first started the lipseals were great ? throw one in the system and it would last about 6 months with no issues. Then about a few years ago we noticed that wafers would stick to new lipseals and pop-off causing the transfer system to miss. To fix this new issue at the time STS told us to do a lipseal burn, or what equates to a 10s O2 plasma of the exposed lipseal. The wafers stopped sticking then, but never had to do that before and still do to this day. First, piece of evidence that something was different. Then we also saw a greatly reduced lifetime of these lipseals from 6 months to weeks. Second, piece of evidence that something was different. So, I have been fighting with SPTS for several years now that something changed with their lipseals and they refuse to admit anything. What it comes down to is these tools are obsolete to them but they are happy to sell you a $250 lipseal if you still want it. However, we do not see black residue on the back of the wafer where it contacted the lipseal. Because the lipseals are so expensive and lasting a few weeks is not sustainable we reduced our O2 plasma clean times, which seems to increase the lipseal lifetime significantly. Mark, with that said we are very interested here at the UW in your effort to make your own lipseals. Please let me know how we can help and get involved in this endeavor with you. Best, Kurt --------------------------------------------------- Kurt Kupcho Process Engineer/Safety Officer NFC 1550 Engineering Drive ECB Room 3110 Madison, WI 53706 E: kurt.kupcho at wisc.edu T: 608-262-2982 From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Mark Weiler Sent: Wednesday, March 06, 2019 8:04 AM To: LaFleur, David W Cc: Fab Network Subject: Re: [labnetwork] STS DRIE Multiplex Lip Seal failures Hi David, I am currently working with an elastomer manufacturer to produce O-Rings and seals for the systems of a material that can withstand better temperature ranges and chemical attacks. If you would like, I can share the information with you and maybe you can join us in this endeavor. The cost for the tooling and mold is now at ~1900 dollars, but I have negotiated the seal price to around 130.00 ea. I have not yet tested this material but we are having a seal made specifically for the Bosch process and 02 cleans. It is my believe that Orbotech has changed suppliers, or has allowed their supplier to switch their material source without testing, all in an effort to shave costs. My new efforts have also yielded a lower cost (50%) for the ceramic components in the chamber. I will test these and get back with the lab network sharing the source and part number. Thank you for sharing your info; now I know we are not the only ones ?feeling the pain? so to speak and can officially commiserate... LOL Best, Mark Mark Weiler Equipment & Facilities Manager Claire and John Bertucci Nanotechnology Laboratory Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.2471 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu On Mar 6, 2019, at 08:46, LaFleur, David W > wrote: Hi Mark, We have an STS MP0579 ICP which uses the lip seals. It is used mostly for silicon and SiO2 etches with O2 cleans between uses. Most of our Bosch processes are run on SPTS Rapier which uses an ESC. That has its own set of issues. We find the lip seals don?t last more than 2-3 weeks in our system. Our chamber o-rings usually go for 2 months at best. I was thinking of changing to a kalrez o-ring and always wondered if they made a Kalrez lip seal. One suggestion on how to make them last longer is make sure they don?t get exposed to any solvents like Isopropyl when you are installing them. I want to say I am not happy with the longevity of the lip seals either and maybe we need to bring this to the attention of Orbotech/SPTS. Maybe they have a solution. Other than that they are good tools, very reliable, and heavily used here at Harvard. Because they are so heavily used with so many processes we find a biweekly chamber clean and lip seal replacement works well for everyone. This is why I have just lived with the lip seals as they are. Regards, David LaFleur Equipment Engineer CNS, Harvard University From: "labnetwork-bounces at mtl.mit.edu" > on behalf of Mark Weiler > Date: Tuesday, March 5, 2019 at 3:44 PM To: Fab Network > Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures Hello Everyone, We have gone through seven new lip seals purchased form Orbotech/SPTS. They are often failing before we even finish qualifying the system, or within a month thereafter. Our our process is stable with power and parameters not deviating over the past decade. However, I ordered the most recent batch of lip seals because the wafer seals we had been using were coming out with black residue after only a few runs? however, the current ones do the same. Not only have the lips seals disintegrated, but the chamber lid o-ring and bottom ceramic spool o-ring have also failed with black rubber material shedding off. It?s as if they are made of Buna and not meant for this application. Our process is typical Bosch with 100 sccm C4F8 and 20 sccm O2 for etching switching off with ~50 Sccm SF6 for passivation at a processing pressure of 15 mTorr, Coil power 600-800W, Platen power 100-150W, Bias voltage 50-100v (up to 200 peak-to-peak), Platen temp at 19 degrees, Lid temp 41 degrees. Qual wafers are new bare Silicon. Etch rates are normal and stable with 10+ years of data?. we just can?t complete the work due to failing seals. Our chamber base pressure is between 1E-8 and 5E-8 Torr each morning. When we put in a brand new seal and run only the LUR, it passes with 0.00 mTorr/minute leak rate. That jumps to 3.00 mTorr/m after only 30 minutes of the SPTS recommended O2 Clean? then rises as time and more runs progress. Wafers are coming out with black rings on their backsides. This should not be happening, and I believe it is due to incorrect material of the lip seals and o-rings. I am pinging the network, though, to see if there might be a parameter change we need to effect that may assist us. Have any of you seen this before? Best regards, Mark ________________________________________________________________ Mark Weiler Equipment & Facilites Manager Clair and John Bertucci Nanotechnology Laboratory Eden Hall Nanofabrication Cleanroom Carnegie Mellon University P: 412-268-2471 http://www.nanofab.ece.cmu.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: images.png Type: image/png Size: 720 bytes Desc: images.png URL: From kurt.kupcho at wisc.edu Mon Mar 11 16:40:31 2019 From: kurt.kupcho at wisc.edu (Kurt Kupcho) Date: Mon, 11 Mar 2019 20:40:31 +0000 Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures In-Reply-To: <0E780989-ED17-46BA-B3FC-92932EDB936C@andrew.cmu.edu> References: <8395D872-145D-42D7-8D7D-558BAE91C048@cns.fas.harvard.edu> <6181704F-4A5F-4A52-B386-7B6C505A5B1F@andrew.cmu.edu> <0E780989-ED17-46BA-B3FC-92932EDB936C@andrew.cmu.edu> Message-ID: Thanks Mark. I would be interested in hearing your Ar lipseal burn results as well. Kurt --------------------------------------------------- Kurt Kupcho Process Engineer/Safety Officer NFC 1550 Engineering Drive ECB Room 3110 Madison, WI 53706 E: kurt.kupcho at wisc.edu T: 608-262-2982 [Nano-Fab_color-flush] From: Mark Weiler [mailto:mweiler at andrew.cmu.edu] Sent: Monday, March 11, 2019 3:33 PM To: Kurt Kupcho Cc: LaFleur, David W; Fab Network Subject: Re: [labnetwork] STS DRIE Multiplex Lip Seal failures Hi Kurt, I will let you know the results of the new seals? In the meantime, I am also creating an Argon lip seal conditioning recipe to see if it will be a kinder-gentler approach to seal conditioning. Mark ________________________________________________________________ Mark Weiler Equipment & Facilites Manager Clair and John Bertucci Nanotechnology Laboratory Eden Hall Nanofabrication Cleanroom Carnegie Mellon University P: 412-268-2471 http://www.nanofab.ece.cmu.edu [cid:image002.png at 01D4D820.C1D01660] On Mar 11, 2019, at 3:55 PM, Kurt Kupcho > wrote: Hi Mark & David ? I was on vacation so I apologize for my late thoughts on this STS DRIE lipseal issue. I am the engineer in charge of the STS DRIE at UW-Madison. When I first started the lipseals were great ? throw one in the system and it would last about 6 months with no issues. Then about a few years ago we noticed that wafers would stick to new lipseals and pop-off causing the transfer system to miss. To fix this new issue at the time STS told us to do a lipseal burn, or what equates to a 10s O2 plasma of the exposed lipseal. The wafers stopped sticking then, but never had to do that before and still do to this day. First, piece of evidence that something was different. Then we also saw a greatly reduced lifetime of these lipseals from 6 months to weeks. Second, piece of evidence that something was different. So, I have been fighting with SPTS for several years now that something changed with their lipseals and they refuse to admit anything. What it comes down to is these tools are obsolete to them but they are happy to sell you a $250 lipseal if you still want it. However, we do not see black residue on the back of the wafer where it contacted the lipseal. Because the lipseals are so expensive and lasting a few weeks is not sustainable we reduced our O2 plasma clean times, which seems to increase the lipseal lifetime significantly. Mark, with that said we are very interested here at the UW in your effort to make your own lipseals. Please let me know how we can help and get involved in this endeavor with you. Best, Kurt --------------------------------------------------- Kurt Kupcho Process Engineer/Safety Officer NFC 1550 Engineering Drive ECB Room 3110 Madison, WI 53706 E: kurt.kupcho at wisc.edu T: 608-262-2982 From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Mark Weiler Sent: Wednesday, March 06, 2019 8:04 AM To: LaFleur, David W Cc: Fab Network Subject: Re: [labnetwork] STS DRIE Multiplex Lip Seal failures Hi David, I am currently working with an elastomer manufacturer to produce O-Rings and seals for the systems of a material that can withstand better temperature ranges and chemical attacks. If you would like, I can share the information with you and maybe you can join us in this endeavor. The cost for the tooling and mold is now at ~1900 dollars, but I have negotiated the seal price to around 130.00 ea. I have not yet tested this material but we are having a seal made specifically for the Bosch process and 02 cleans. It is my believe that Orbotech has changed suppliers, or has allowed their supplier to switch their material source without testing, all in an effort to shave costs. My new efforts have also yielded a lower cost (50%) for the ceramic components in the chamber. I will test these and get back with the lab network sharing the source and part number. Thank you for sharing your info; now I know we are not the only ones ?feeling the pain? so to speak and can officially commiserate... LOL Best, Mark Mark Weiler Equipment & Facilities Manager Claire and John Bertucci Nanotechnology Laboratory Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.2471 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu On Mar 6, 2019, at 08:46, LaFleur, David W > wrote: Hi Mark, We have an STS MP0579 ICP which uses the lip seals. It is used mostly for silicon and SiO2 etches with O2 cleans between uses. Most of our Bosch processes are run on SPTS Rapier which uses an ESC. That has its own set of issues. We find the lip seals don?t last more than 2-3 weeks in our system. Our chamber o-rings usually go for 2 months at best. I was thinking of changing to a kalrez o-ring and always wondered if they made a Kalrez lip seal. One suggestion on how to make them last longer is make sure they don?t get exposed to any solvents like Isopropyl when you are installing them. I want to say I am not happy with the longevity of the lip seals either and maybe we need to bring this to the attention of Orbotech/SPTS. Maybe they have a solution. Other than that they are good tools, very reliable, and heavily used here at Harvard. Because they are so heavily used with so many processes we find a biweekly chamber clean and lip seal replacement works well for everyone. This is why I have just lived with the lip seals as they are. Regards, David LaFleur Equipment Engineer CNS, Harvard University From: "labnetwork-bounces at mtl.mit.edu" > on behalf of Mark Weiler > Date: Tuesday, March 5, 2019 at 3:44 PM To: Fab Network > Subject: [labnetwork] STS DRIE Multiplex Lip Seal failures Hello Everyone, We have gone through seven new lip seals purchased form Orbotech/SPTS. They are often failing before we even finish qualifying the system, or within a month thereafter. Our our process is stable with power and parameters not deviating over the past decade. However, I ordered the most recent batch of lip seals because the wafer seals we had been using were coming out with black residue after only a few runs? however, the current ones do the same. Not only have the lips seals disintegrated, but the chamber lid o-ring and bottom ceramic spool o-ring have also failed with black rubber material shedding off. It?s as if they are made of Buna and not meant for this application. Our process is typical Bosch with 100 sccm C4F8 and 20 sccm O2 for etching switching off with ~50 Sccm SF6 for passivation at a processing pressure of 15 mTorr, Coil power 600-800W, Platen power 100-150W, Bias voltage 50-100v (up to 200 peak-to-peak), Platen temp at 19 degrees, Lid temp 41 degrees. Qual wafers are new bare Silicon. Etch rates are normal and stable with 10+ years of data?. we just can?t complete the work due to failing seals. Our chamber base pressure is between 1E-8 and 5E-8 Torr each morning. When we put in a brand new seal and run only the LUR, it passes with 0.00 mTorr/minute leak rate. That jumps to 3.00 mTorr/m after only 30 minutes of the SPTS recommended O2 Clean? then rises as time and more runs progress. Wafers are coming out with black rings on their backsides. This should not be happening, and I believe it is due to incorrect material of the lip seals and o-rings. I am pinging the network, though, to see if there might be a parameter change we need to effect that may assist us. Have any of you seen this before? Best regards, Mark ________________________________________________________________ Mark Weiler Equipment & Facilites Manager Clair and John Bertucci Nanotechnology Laboratory Eden Hall Nanofabrication Cleanroom Carnegie Mellon University P: 412-268-2471 http://www.nanofab.ece.cmu.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.png Type: image/png Size: 39543 bytes Desc: image001.png URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image002.png Type: image/png Size: 720 bytes Desc: image002.png URL: From psharris at trilicium.ca Mon Mar 11 22:14:54 2019 From: psharris at trilicium.ca (P. Scott Harris) Date: Mon, 11 Mar 2019 22:14:54 -0400 Subject: [labnetwork] VMS and/or Compaq/DEC experts In-Reply-To: <5c86bcca5691d0396e000001@polymail.io> References: <5c86bcca5691d0396e000001@polymail.io> Message-ID: <0cb067f3-d882-b9c7-5ac3-fad9e93b0905@trilicium.ca> Hi Aimee, We actually have done the PC upgrades that Matt references that replace DEC PDP-11s running RSX-11 with PCs.? We haven't actually done the equivalent for Alpha machines running OpenVMS but a few of the simple things to try first might be : - replace SCSI drives, assuming SCSI is being used, with some sort of SCSI-to-SATA or SCSI-to-SD adapter and new drive hardware (Google will find these pretty quickly although you will have to pay attention the the SCSI connectors and the generation of SCSI interface being used) - replace the actual DEC Alpha processor hardware with an emulation such as EmuVM and AlphaVM-Pro which uses emulated disks and tape drives. I have never tried it so I can't make a recommendation one way or the other but it would likely be a good place to start The actual connection to the E-beam hardware might be tricky. We have done upgrades for XLS steppers that replace the Sparcstation and SunOS with an emulation but the hardware interface in that case is a fairly basic ethernet network connection. If it's a custom hardware interface you may have to stick with the existing Alpha computer hardware. If you can actually run an emulation, the network backup file that you mention might serve as a suitable disk image.? We should be able to read your SCSI drive (assuming that's what is being used) and generate a binary file image for use in an emulation if your network backup is unsuitable. If you wanted to pursue this further, or have further questions, then please let me know. Best regards P. Scott Harris, P.Eng. H&L Associates On 2019-03-11 3:56 p.m., Matt Pace wrote: > Web Bug from > https://share.polymail.io/v2/z/a/NWM4NmJjY2E1Njkx/haT1u4yBZCGDphdnoBXbKYR_lP5OZeV9ve3et6sU9tAsJmQRYwCQcIp6E018H7EsJdw_BXU-RoX-pg5rh4QTQS4IZuUC0s4m9EZJAVY8ei7Wl_djvYgoyL25HqWHOwX56nRvoj7YeuA9f6V2UA6w1EQ=.png > > Hi Aimee, > > Maybe try Mitch at Keyways - he did a lot of work for us as we transitioned > from the old DEC PDP 11 computers to the PC upgrades on the GCA Steppers some > time ago. > > All the best, > Matt > > --- > > Matt Pace > > 3c Technical > > matt at 3ctechnical.com > > www.3ctechnical.com > > 480-963-4559?voice > > > On Mon, Mar 11th, 2019 at 7:3 AM, "Price, Aimee" wrote: > > All, > > Is anyone out there, or do you know anyone/have a source who is, a VMS > and/or Compaq(HP or DEC) expert?? I?m looking for a consultant, either on > the phone or preferably in person. > > I have an Compaq/DEC Alpha XP900 running open VMS for my Raith > (Leica/Vistec) EBPG5000 ebeam lithography tool.? One of the two hard disks > failed and 3 tape drives have failed. ??We have another tape drive on order ? > > I have a replacement hard disk and backup tapes (though fewer now after > the failed tape drives destroyed two) and a backup file on our network, > which can be moved to the system drive.? However, I?m running up against > my lack of VMS knowledge. > > For completeness, there is also a CD-ROM drive and a floppy.? We are > running Open VMS 7.2. > > If anyone has a contact or would be interested on working on something > like this, please let me know.? Alternatively, if anyone has a contact > that can repair or recover hard disks of this type, I would be more than > appreciative. > > Thanks much, > > Aimee Bross Price > > Sr. Research Associate > > The Ohio State University > > Nanotech West Lab > > Institute for Materials Research > > 1381 Kinnear Road > > Suite 100 > > Columbus, OH 43212 > > 614-292-2753 > > --- This email has been checked for viruses by Avast antivirus software. https://www.avast.com/antivirus -------------- next part -------------- An HTML attachment was scrubbed... URL: From Milan.Begliarbekov at asrc.cuny.edu Tue Mar 12 15:24:33 2019 From: Milan.Begliarbekov at asrc.cuny.edu (Milan Begliarbekov) Date: Tue, 12 Mar 2019 19:24:33 +0000 Subject: [labnetwork] Electroplating Ni Message-ID: <10de53f532bf4df5bc586ec7d65f9938@EXCPMNJ02.enterpriseapps.cuny.adlan> Hi All, I need to electroplate Nickel into a photoresist mask. The features should be 25 microns wide and 25 microns tall. Does anyone have a suggestion about external vendors that would be good for this? Also any other guidance about this process is highly appreciated. Thank you for the help, Milan Begliarbekov Research Assistant Professor NanoFabrication Facility CUNY Advanced Science Research Center Office: 212-413-3311 85 St. Nicholas Terrace Manhattan NY 10031 -------------- next part -------------- An HTML attachment was scrubbed... URL: From qleonard at wisc.edu Wed Mar 13 10:01:35 2019 From: qleonard at wisc.edu (Quinn Leonard) Date: Wed, 13 Mar 2019 14:01:35 +0000 Subject: [labnetwork] Electroplating Ni In-Reply-To: <10de53f532bf4df5bc586ec7d65f9938@EXCPMNJ02.enterpriseapps.cuny.adlan> References: <10de53f532bf4df5bc586ec7d65f9938@EXCPMNJ02.enterpriseapps.cuny.adlan> Message-ID: <5a28e821-5e29-b3bc-399c-69ed08347e4b@wisc.edu> We had good results using the premixed Ni electroplating bath available from Sigma-Aldrich. Our application required plating Ni films on the order of a few microns thick, with low stress, to form features with sizes down to one micron width or so. We saw Ni crystal grain sizes around 25 nm in the plated film. This may, or may not, scale up to the 25 micron thickness you ask for. Some work was done at the same time with another commercial product that was sold as separate components - wetting agent, stabilizer, brightener, a couple of chemicals to manage pH, something to reduce stress in the final film, and finally the solution of goofy sulfated nickel compound that provides the actual metal. Probably this could have given us more control over the process, but tinkering with all those components by a lone graduate student, who did Ni plating only occasionally never yielded a stable process. And it cost a lot. We also found it necessary to build a recirculation/filtration/temperature control system for the plating bath to live in; otherwise the results were nonuniform across our 4" samples, could have different plating rates for different sized features, and were otherwise nonreproducible. A good place to start reading might be the ASM Metals Handbook Volume 5: Surface Engineering. Best of luck! Quinn Leonard Technical Staff Nanoscale Fabrication Center University of Wisconsin Room 3112 Engineering Centers Building 1550 Engineering Drive Madison, WI 53706 (608) 890-3030 qleonard at wisc.edu https://wcnt.wisc.edu/ On 3/12/2019 2:24 PM, Milan Begliarbekov wrote: Hi All, I need to electroplate Nickel into a photoresist mask. The features should be 25 microns wide and 25 microns tall. Does anyone have a suggestion about external vendors that would be good for this? Also any other guidance about this process is highly appreciated. Thank you for the help, Milan Begliarbekov Research Assistant Professor NanoFabrication Facility CUNY Advanced Science Research Center Office: 212-413-3311 85 St. Nicholas Terrace Manhattan NY 10031 _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -- Quinn Leonard Technical Staff Nanoscale Fabrication Center University of Wisconsin Room 3112 Engineering Centers Building 1550 Engineering Drive Madison, WI 53706 (608) 890-3030 qleonard at wisc.edu https://wcnt.wisc.edu/ -------------- next part -------------- An HTML attachment was scrubbed... URL: From nsieb at sfu.ca Wed Mar 13 12:01:23 2019 From: nsieb at sfu.ca (Nathanael Sieb) Date: Wed, 13 Mar 2019 16:01:23 +0000 Subject: [labnetwork] Electroplating Ni Message-ID: <0fe17304-df79-46a6-8f3c-1989baa21aa7@email.android.com> Similarly we use a premixed solution from Technic in a heated, recirculating, filtered bath. We've had good success with wafers up to 4" and sometimes 6". We have to monitor the pH and replace the bath every year or two, but it is a pretty consistent process and the chemicals are not that expensive. We also used to have a gold plating bath but it wasn't used enough and the bath degraded. It cost of $thousands of dollars in chemicals unfortunately and we won't be setting that one up again. Nathanael On Mar 13, 2019 08:40, Quinn Leonard wrote: We had good results using the premixed Ni electroplating bath available from Sigma-Aldrich. Our application required plating Ni films on the order of a few microns thick, with low stress, to form features with sizes down to one micron width or so. We saw Ni crystal grain sizes around 25 nm in the plated film. This may, or may not, scale up to the 25 micron thickness you ask for. Some work was done at the same time with another commercial product that was sold as separate components - wetting agent, stabilizer, brightener, a couple of chemicals to manage pH, something to reduce stress in the final film, and finally the solution of goofy sulfated nickel compound that provides the actual metal. Probably this could have given us more control over the process, but tinkering with all those components by a lone graduate student, who did Ni plating only occasionally never yielded a stable process. And it cost a lot. We also found it necessary to build a recirculation/filtration/temperature control system for the plating bath to live in; otherwise the results were nonuniform across our 4" samples, could have different plating rates for different sized features, and were otherwise nonreproducible. A good place to start reading might be the ASM Metals Handbook Volume 5: Surface Engineering. Best of luck! Quinn Leonard Technical Staff Nanoscale Fabrication Center University of Wisconsin Room 3112 Engineering Centers Building 1550 Engineering Drive Madison, WI 53706 (608) 890-3030 qleonard at wisc.edu https://wcnt.wisc.edu/ On 3/12/2019 2:24 PM, Milan Begliarbekov wrote: Hi All, I need to electroplate Nickel into a photoresist mask. The features should be 25 microns wide and 25 microns tall. Does anyone have a suggestion about external vendors that would be good for this? Also any other guidance about this process is highly appreciated. Thank you for the help, Milan Begliarbekov Research Assistant Professor NanoFabrication Facility CUNY Advanced Science Research Center Office: 212-413-3311 85 St. Nicholas Terrace Manhattan NY 10031 _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -- Quinn Leonard Technical Staff Nanoscale Fabrication Center University of Wisconsin Room 3112 Engineering Centers Building 1550 Engineering Drive Madison, WI 53706 (608) 890-3030 qleonard at wisc.edu https://wcnt.wisc.edu/ -------------- next part -------------- An HTML attachment was scrubbed... URL: From hadi_esmaeilsabzali at sfu.ca Thu Mar 14 03:26:40 2019 From: hadi_esmaeilsabzali at sfu.ca (Hadi Esmaeilsabzali) Date: Thu, 14 Mar 2019 07:26:40 +0000 Subject: [labnetwork] Electroplating Ni In-Reply-To: <10de53f532bf4df5bc586ec7d65f9938@EXCPMNJ02.enterpriseapps.cuny.adlan> References: <10de53f532bf4df5bc586ec7d65f9938@EXCPMNJ02.enterpriseapps.cuny.adlan> Message-ID: <975c5f98cc86457ba942b244d4e6e46d@sfu.ca> I did quite a bit of permalloy (80%Ni-20%Fe) e-plating when I was in the grad school. I had to build my own setup, as at the time I couldn't find any lab that would allow me to use their setup for Ni/Fe plating (risk of contamination). I had heated 4L bath with constant mixing using magnetic stirrer and later recirculating using a small aquarium pump. The bath composition was according to a couple of established papers, and I ordered all the chemicals from Sigma. Aside from getting the correct 20-80 composition (came down to experimentally tweaking the current for the most part to account for different reduction potentials - this shouldn't be a big issue in your application), another issue that you particularly might want to be aware of was the difference in the thickness of structures across the wafer as well as across the same structure (my structures were typically 30-100 um wide and up to 15 um thick). This happens because of the so-called ?edge effect? resulting from increased electrodeposition rate due to current crowding happening on edges of individual features on the plating mold as well as across the wafer. I was initially using a wafer holder that I had made and had 4 contact point on 4 corners of the wafer. This gave really bad edge effect (the thickness difference was >25% at edges sometimes). I had to convince my boss to order a nice custom-made wafer holder (from OAI/Idonus) with a continuous electrode touching the periphery of the wafer, and it helped a lot by creating a more uniform field. Good luck! Hadi Hadi Esmaeilsabzali, PhD 4D LABS, Simon Fraser University Phone: 778-782-3790 Email: hesmaeil at sfu.ca http://www.4dlabs.ca/ [1525200877645_1480963378154.png] Acknowledging that we live, work, and play on the unceded territory of the Musqueam, Tsleil-Waututh, and Squamish nations. ________________________________ From: labnetwork-bounces at mtl.mit.edu on behalf of Milan Begliarbekov Sent: March 12, 2019 12:24 PM To: labnetwork at mtl.mit.edu Subject: [labnetwork] Electroplating Ni Hi All, I need to electroplate Nickel into a photoresist mask. The features should be 25 microns wide and 25 microns tall. Does anyone have a suggestion about external vendors that would be good for this? Also any other guidance about this process is highly appreciated. Thank you for the help, Milan Begliarbekov Research Assistant Professor NanoFabrication Facility CUNY Advanced Science Research Center Office: 212-413-3311 85 St. Nicholas Terrace Manhattan NY 10031 -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: OutlookEmoji-1525200877645_1480963378154.png7982bd7d-ea3a-488d-8b52-dd4757227ec8.png Type: image/png Size: 2860 bytes Desc: OutlookEmoji-1525200877645_1480963378154.png7982bd7d-ea3a-488d-8b52-dd4757227ec8.png URL: From travisgabel at boisestate.edu Thu Mar 14 11:53:54 2019 From: travisgabel at boisestate.edu (Travis Gabel) Date: Thu, 14 Mar 2019 09:53:54 -0600 Subject: [labnetwork] Wyko Nt1100 alignment procedure Message-ID: Hi I am looking for a light alignment procedure for a WYKO NT1100 optical profiler. The manuals we have for this machine only mention the centering screw but this is for the objective lenses and not the light itself. If anyone has one that they can pass along I would greatly appreciate it. Thanks Travis -------------- next part -------------- An HTML attachment was scrubbed... URL: From Daniel.Pulver at ll.mit.edu Fri Mar 15 12:11:23 2019 From: Daniel.Pulver at ll.mit.edu (Pulver, Daniel - 0835 - MITLL) Date: Fri, 15 Mar 2019 16:11:23 +0000 Subject: [labnetwork] Fab engineer opening Message-ID: <6481de5fd8a34b21ab994ebfc2ca45ce@ll.mit.edu> Labnetwork, We have a Microfabrication Process Engineer opening to work in our Microelectronics Laboratory. Our lab is US Government's most advanced captive silicon fab, based on 200mm wafers with a commercial class tool set serving development and prototyping needs utilizing technologies including 90nm FDSOI CMOS, superconducting digital and quantum computing, photonics, and 2.5 and 3D integration. Kindly forward to those who may be interested. Dan Pulver Microelectronics Laboratory Manager MIT Lincoln Laboratory 244 Wood Street Lexington, MA 02421 781-540-3906 mobile 781-981-1716 office daniel.pulver at ll.mit.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: smime.p7s Type: application/pkcs7-signature Size: 5537 bytes Desc: not available URL: From ahryciw at ualberta.ca Fri Mar 15 12:12:46 2019 From: ahryciw at ualberta.ca (Aaron Hryciw) Date: Fri, 15 Mar 2019 10:12:46 -0600 Subject: [labnetwork] Use of forming gas in cryo-pumped sputtering system Message-ID: Dear colleagues, Our open-access facility has a cryo-pumped, manual sputtering system plumbed with argon, oxygen, and nitrogen, which is often used for reactive sputtering (mostly oxides). One of our users has requested the addition of forming gas (5% H? + balance Ar) to enable sputtering of *a*-Si:H / SiO? multilayers, as described in this paper . A concern was raised, however, about the possibility of explosions in the cryo during regeneration, as the frozen mixture of argon, oxygen, ozone, and hydrogen is released as the pump is warmed up. Does anyone have experience with using forming gas in a cryo-pumped system, and/or know of any measures that could be taken to ensure these sputtering processes could be performed safely? Doing this on a system equipped with a turbo pump would be better, but we are leery of putting a turbo on a manual system, where users fairly routinely crash the cryo. As always, any advice would be greatly appreciated. Many thanks. Cheers, ? Aaron Aaron Hryciw, PhD, PEng Fabrication Group Manager University of Alberta - nanoFAB W1-060 ECERF Building 9107 - 116 Street Edmonton, Alberta Canada T6G 2V4 Ph: 780-940-7938 www.nanofab.ualberta.ca -------------- next part -------------- An HTML attachment was scrubbed... URL: From bgila at ufl.edu Fri Mar 15 17:54:04 2019 From: bgila at ufl.edu (Brent Gila) Date: Fri, 15 Mar 2019 17:54:04 -0400 Subject: [labnetwork] Use of forming gas in cryo-pumped sputtering system In-Reply-To: References: Message-ID: <439d506d-7737-9956-50cb-90df5a6b0483@ufl.edu> Hello Aaron, I my previous research, I did a lot of oxide MBE growth and we used a H2 plasma to clean the substrate surface (GaAs, GaN,...).? The cryopump on the MBE system worked well for these gases.? The regen was not a big concern for us, H2 comes off of the cold head at 20K while O2 comes off at 90K.? We regened the cryo with a dry backing pump (not the standard flowing N2 method), so the cryopump was always under vacuum and thus we never had a critical build up of H2.? But I think you will be fine even if you use the flowing N2 regen method for the cryo (like most sputter tools), the dilution of the H2 will occur pretty quickly and the pump body will have a LOT of N2 inside. Best Regards, Brent -- Brent P. Gila, PhD. Director, Nanoscale Research Facility 1041 Center Drive University of Florida Gainesville, Florida 32611 Tel:352-273-2245 Fax:352-846-2877 email:bgila at ufl.edu On 3/15/2019 12:12 PM, Aaron Hryciw wrote: > Dear colleagues, > > Our open-access facility has a cryo-pumped, manual sputtering system > plumbed with argon, oxygen, and nitrogen, which is often used for > reactive sputtering (mostly oxides). One of our users has requested > the addition of forming gas (5% H??+ balance Ar) to enable sputtering > of /a/-Si:H / SiO? multilayers, as described in this paper > .? > A concern was raised, however, about the possibility of explosions in > the cryo during regeneration, as the frozen mixture of argon, oxygen, > ozone, and hydrogen is released as the pump is warmed up. > > Does anyone have experience with using forming gas in a cryo-pumped > system, and/or know of any measures that could be taken to ensure > these sputtering processes could be performed safely?? Doing this on a > system equipped with a turbo pump would be better, but we are leery of > putting a turbo on a manual system, where users fairly routinely crash > the cryo. As always, any advice would be greatly appreciated. > > Many thanks. > > Cheers, > > ?? Aaron > > __ > > Aaron Hryciw, PhD, PEng > > Fabrication Group Manager > > University of Alberta - nanoFAB > > W1-060 ECERF Building > > 9107 - 116 Street > > Edmonton, Alberta > > Canada T6G 2V4 Ph: 780-940-7938 > > www.nanofab.ualberta.ca > > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://urldefense.proofpoint.com/v2/url?u=https-3A__mtl.mit.edu_mailman_listinfo.cgi_labnetwork&d=DwICAg&c=sJ6xIWYx-zLMB3EPkvcnVg&r=gl_2fLZA_-_JfH_dOmx7ug&m=RQnKj8jWOJDys3S59ErGq_i0RC9WpIgTRWwy5pLQGlw&s=VMscYXW1vfKJ2lHCb2UcCanpdUQks5AWKhquXQyNT-o&e= -------------- next part -------------- An HTML attachment was scrubbed... URL: From michael.martin at louisville.edu Mon Mar 18 14:06:48 2019 From: michael.martin at louisville.edu (Martin,Michael David) Date: Mon, 18 Mar 2019 18:06:48 +0000 Subject: [labnetwork] CMOS Clean in a MEMS Fab Facility Message-ID: Hi, I'm trying to track down potential sources of contamination for a CMOS process we are trying to run through our predominantly MEMS fab here at U of Louisville. Really the only pieces of equipment that are dedicated for CMOS type processes is our RCA bench, an older Technics sputterer, and our oxidation furnace (sort of, see below). So I have a few questions for those of you who have experience with this: 1) For HF etch/dips is there a particular polymer type or brand we should use for our containers that are known to be free of trace metals? Can I avoid PTFE as this is super expensive? 2) When you do litho do you have separate labware for developing? We currently use a Pyrex pan develop which I know is a No-No due to Na and other ions. What sort of container does your lab use (assuming pan develop)? 2 a) Do you have a dedicated spinner for CMOS? 2 b) Is there any danger that we are picking up contamination from the amber bottles we are temporarily storing our resists in? What about the polypropylene droppers we are dispensing resists with? 2 c) What about resist stripping after etching? We typically use a big warm vat of NMP that is shared by all users. We can also do a plasma etch but I worry about carry over from other folks as none of our plasma etchers are dedicated CMOS. 3) I presume quartz glassware works for my metal (usually aluminum) etching? Do you do regular aqua regia cleans on quartz-ware to scavenge other metals and potential contaminants? 4) We gravitate to peek tipped metal tweezers. Are they okay? Do you regularly run the tips through a RCA clean? 5) Oxidation furnace: Before trying to transition to CMOS like devices the tube was used with non-RCA cleaned wafers and a pyrex bubbler. After moving to a quartz bubbler with DI water we cleaned the 4" tube with HF. This is the one I'm really concerned about because I'm guessing that ionic contamination that might have been removed from the surface will readily diffuse back at 1000C. So should we just bite the bullet and buy a new tube? Any vendor suggestions for a 4" Blue-M? 6) Any other suggestions other than buying a dedicated CMOS tool set? I did find a very nice document from Stanford that has a lot of practical suggestions found here https://web.stanford.edu/class/ee410/cleaning.pdf ) Krishna Saraswa - Stanford University 6 tanford University araswat 11! Cleaning - Surface Issues Contaminant ? Organics ? Skin oils ? Resist ? Polymers ? Metals web.stanford.edu Thank you in advance, Michael -------------- next part -------------- An HTML attachment was scrubbed... URL: From paj1 at email.gwu.edu Mon Mar 18 15:08:17 2019 From: paj1 at email.gwu.edu (Johnson, Patrick) Date: Mon, 18 Mar 2019 15:08:17 -0400 Subject: [labnetwork] Clean room / Nanofab temp/ Message-ID: Hello Colleagues, what do the other NanoFabs basically have there cleanrooms temp and humidity specs set at? I have been in Semiconductor since 1995 and 67F +/- 1 degree and humidity 45-47% is what I have encountered. I appreciate any input from the LabNetwork partners. Thanks Patrick *Patrick Johnson* *George Washington University* *Nano Fabrication Lab Manager * *Science and Engineering Hall* *800 NW 22nd Street Rm-B2815* *Washington D.C. 20052* *Cell 703 258 2465* *Desk 202 994 2346* -------------- next part -------------- An HTML attachment was scrubbed... URL: From mmoneck at andrew.cmu.edu Mon Mar 18 20:03:24 2019 From: mmoneck at andrew.cmu.edu (Matthew Moneck) Date: Tue, 19 Mar 2019 00:03:24 +0000 Subject: [labnetwork] Clean room / Nanofab temp/ In-Reply-To: References: Message-ID: <2cacbfb7721f4284b82c4bc5e968adf2@andrew.cmu.edu> Hi Patrick, Our systems are set to target 68 deg +/- 0.5 deg and 40% +/- 1%. Best Regards, Matt -- Matthew T. Moneck, Ph.D. Executive Manager, Claire & John Bertucci Nanotechnology Laboratory Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.5430 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Johnson, Patrick Sent: Monday, March 18, 2019 3:08 PM To: labnetwork at mtl.mit.edu Subject: [labnetwork] Clean room / Nanofab temp/ Hello Colleagues, what do the other NanoFabs basically have there cleanrooms temp and humidity specs set at? I have been in Semiconductor since 1995 and 67F +/- 1 degree and humidity 45-47% is what I have encountered. I appreciate any input from the LabNetwork partners. Thanks Patrick Patrick Johnson George Washington University Nano Fabrication Lab Manager Science and Engineering Hall 800 NW 22nd Street Rm-B2815 Washington D.C. 20052 Cell 703 258 2465 Desk 202 994 2346 -------------- next part -------------- An HTML attachment was scrubbed... URL: From codreanu at udel.edu Tue Mar 19 08:30:19 2019 From: codreanu at udel.edu (Iulian Codreanu) Date: Tue, 19 Mar 2019 08:30:19 -0400 Subject: [labnetwork] Clean room / Nanofab temp/ In-Reply-To: References: Message-ID: Hi Patrick, My systems meet 68 +/- 0.5 degF year round. When it comes to humidity they achieve the equivalent of 45 +/-2 %RH during the humidification and dehumidification seasons. I am working on achieving that during the "shoulder seasons" as well. I control to dewpoint (rather than relative humidity) because it has more physical meaning. Good luck, Iulian iulian Codreanu, Ph.D. Director of Operations, Nanofabrication Facility University of Delaware Harker ISE Lab, Room 163 221 Academy Street Newark, DE 19716 302-831-2784 http://udnf.udel.edu On 3/18/2019 3:08 PM, Johnson, Patrick wrote: > ?Hello Colleagues,? what do the other NanoFabs basically have there > cleanrooms temp and humidity specs set at? I have been in > Semiconductor since 1995 and 67F +/- 1 degree and humidity 45-47%? is > what I have encountered.? I appreciate any input from? the LabNetwork > partners.? Thanks Patrick > */Patrick Johnson/* > /George Washington University/ > /Nano Fabrication Lab Manager / > /Science and Engineering Hall/ > /800 NW 22nd Street Rm-B2815/ > /Washington D.C. 20052/ > /Cell 703 258 2465/ > /Desk 202 994 2346/ > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From kjvowen at lnf.umich.edu Tue Mar 19 10:05:13 2019 From: kjvowen at lnf.umich.edu (Kevin Owen) Date: Tue, 19 Mar 2019 10:05:13 -0400 Subject: [labnetwork] Gorilla glass Etching In-Reply-To: <307976345.2407675.1551986465550.JavaMail.zimbra@polymtl.ca> References: <307976345.2407675.1551986465550.JavaMail.zimbra@polymtl.ca> Message-ID: Christophe, For a more accurate analysis of the contamination in the glass, if you are willing to spend the money, you could do VPD ICP-MS. This is what we use to check contamination from processing in our tools. We use Balazs to analyze the samples ( https://www.electronics-airliquide.com/our-brands/balazstm-nanoanalysis). They can check for up to ~35 elements on a sample, and we often do a second wafer for noble metals (Au, Ag, Pt). We etch various kinds of glass (fused silica, borosilicate, etc) in our STS APS system, although I haven't specifically had anyone request gorilla glass. I use the same cleaning procedure as I would for fused silica, although our tool isn't all that "clean" to begin with. You could check cross contamination by running a gorilla glass wafer followed by a clean Si wafer and sending the latter out for analysis. -Kevin On Thu, Mar 7, 2019 at 7:46 PM Christophe Cl?ment < christophe.clement at polymtl.ca> wrote: > Hello Labnetwork community, > I've been ask by a company to etch Gorilla Glass in our DRIE-ICP etcher > (Oxford Plasmalab 100), where we already etch Si (regular Bosch process) > and SiO2 etching (Fused silica only). As the supplier of the Gorilla glass > does not share the composition of this kind of glass, I'm a little bit > afraid of cross contamination (Potassium and other material that can be > present in the glass) that can be found during Si etching for example. > Is there anyone who has experienced etching this material? If yes, what is > your cleaning procedure after etching Gorilla glass? > > Thank you in advance for your answer > Best > Christophe > > *Christophe Cl?ment* > > *Technicien laboratoire* > > Laboratoire de microfabrication (LMF) > > Groupe des Couches Minces (GCM) *www.gcmlab.ca * > > Ecole Polytechnique de Montr?al www.polymtl.ca > > D?partement de g?nie physique > > * 2900 Boulevard Edouard Monpetit > > Pavillon JAB > Campus de l'Universit? de Montr?al > Montr?al (Qu?bec) H3T 1J4 > > > 8 christophe.clement at polymtl.ca > > ( 514 340 4711 > > Fax : 514 340 4711 # 2417 > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > -- Kevin Owen Senior Engineer in Research Operations Group, Lurie Nanofabrication Facility University of Michigan (734) 545-4014 -------------- next part -------------- An HTML attachment was scrubbed... URL: From john.nibarger at nist.gov Tue Mar 19 10:27:06 2019 From: john.nibarger at nist.gov (Nibarger, John (Fed)) Date: Tue, 19 Mar 2019 14:27:06 +0000 Subject: [labnetwork] Clean room / Nanofab temp/ In-Reply-To: <2cacbfb7721f4284b82c4bc5e968adf2@andrew.cmu.edu> References: <2cacbfb7721f4284b82c4bc5e968adf2@andrew.cmu.edu> Message-ID: <27B6147C-A428-4FB9-B624-BA8D8B13D210@nist.gov> We?re at 68.5 deg +/- 0.5 deg and 40% +/- 5%. - John John P. Nibarger, Ph.D. Manager, Boulder Micro-fabrication Facility Microfabrication Group Leader (687.10) National Institute of Standards and Technology 325 Broadway, MS 687.10 Boulder, CO 80305 303-497-4575 (phone) 303-497-3042 (fax) john.nibarger at nist.gov From: on behalf of Matthew Moneck Date: Tuesday, March 19, 2019 at 5:42 AM To: "Johnson, Patrick" , "labnetwork at mtl.mit.edu" Subject: Re: [labnetwork] Clean room / Nanofab temp/ Hi Patrick, Our systems are set to target 68 deg +/- 0.5 deg and 40% +/- 1%. Best Regards, Matt -- Matthew T. Moneck, Ph.D. Executive Manager, Claire & John Bertucci Nanotechnology Laboratory Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.5430 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Johnson, Patrick Sent: Monday, March 18, 2019 3:08 PM To: labnetwork at mtl.mit.edu Subject: [labnetwork] Clean room / Nanofab temp/ Hello Colleagues, what do the other NanoFabs basically have there cleanrooms temp and humidity specs set at? I have been in Semiconductor since 1995 and 67F +/- 1 degree and humidity 45-47% is what I have encountered. I appreciate any input from the LabNetwork partners. Thanks Patrick Patrick Johnson George Washington University Nano Fabrication Lab Manager Science and Engineering Hall 800 NW 22nd Street Rm-B2815 Washington D.C. 20052 Cell 703 258 2465 Desk 202 994 2346 -------------- next part -------------- An HTML attachment was scrubbed... URL: From mmoneck at andrew.cmu.edu Tue Mar 19 12:59:20 2019 From: mmoneck at andrew.cmu.edu (Matthew Moneck) Date: Tue, 19 Mar 2019 16:59:20 +0000 Subject: [labnetwork] CMOS Clean in a MEMS Fab Facility In-Reply-To: References: Message-ID: Hi Michael, Our fab does not do a lot of traditional CMOS work, so I am by no means an expert in this area. A lot of our work is concentrated in MEMS (including back-end processing on CMOS tapeout chips), magnetics, spintronics, photonics, 2D materials, functional oxides, bio interfaces, other emerging technologies. However, I can hopefully offer a few comments from lessons learned or experiences we've had in the past, especially when working on devices where trapped charge or ion contamination were an issue. Referencing your original question numbers: 1. We typically use PTFE petri dishes for this application. We routinely process 100mm wafers in low profile evaporating dishes. While not cheap, a couple dishes won't typically set you back too much. 2. We separate glassware for metal ion free (MIF) and metal ion containing (MIC) containers (I'm assuming you are using MIF developers for CMOS). Beakers are labeled MIF or MIC by etching the letters into the glass exterior of the beaker. If I recall correctly most of the beakers are Type 1, Class A, 33 expansion Borosilicate glass (note that I'm not endorsing this one way or the other for CMOS). 2A. We do not have a dedicated spinner for CMOS, but we do limit which resists can go in which spinners (in the case where non-standard resists are used). 2B. I would verify the type of glass used in the amber bottles. Also, we buy droppers in clean, sterile packaging, as we have seen that droppers packaged and stored incorrectly can introduce contaminates. In extreme cases, we have had some users request and move to glass pipettes. 2C. The shared bath of NMP would be one of my biggest concerns in this whole process. Manufacturers will list that NMP is safe on a lot of metals, including copper. However, there is a caveat. If the NMP bath collects or becomes contaminated with moisture, it makes the bath corrosive. I have seen first-hand how NMP can corrode, or even etch through metals, such as copper. If people are using the bath with such materials, it could have trace metals and other contaminants. We do not do a lot in the way of furnace work, so I will default to others in the network that are much more of an expert in this area than me, but for what it's worth, the latter questions on quartz tube contaminants would be a concern in my opinion. Even in simple annealing furnaces and our RTA, we keep "clean" and "dirty" tubes/chambers that we exchange depending on the materials being used. In regards to potential vendors, we have purchased quartz products from Technical Glass Products in the past (https://technicalglass.com/), although, again, others who do a lot more work with furnaces will likely have more input than me. Hope this helps in some capacity. Best Regards, Matt -- Matthew T. Moneck, Ph.D. Executive Manager, Claire & John Bertucci Nanotechnology Laboratory Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.5430 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Martin,Michael David Sent: Monday, March 18, 2019 2:07 PM To: labnetwork at mtl.mit.edu Subject: [labnetwork] CMOS Clean in a MEMS Fab Facility Hi, I'm trying to track down potential sources of contamination for a CMOS process we are trying to run through our predominantly MEMS fab here at U of Louisville. Really the only pieces of equipment that are dedicated for CMOS type processes is our RCA bench, an older Technics sputterer, and our oxidation furnace (sort of, see below). So I have a few questions for those of you who have experience with this: 1) For HF etch/dips is there a particular polymer type or brand we should use for our containers that are known to be free of trace metals? Can I avoid PTFE as this is super expensive? 2) When you do litho do you have separate labware for developing? We currently use a Pyrex pan develop which I know is a No-No due to Na and other ions. What sort of container does your lab use (assuming pan develop)? 2 a) Do you have a dedicated spinner for CMOS? 2 b) Is there any danger that we are picking up contamination from the amber bottles we are temporarily storing our resists in? What about the polypropylene droppers we are dispensing resists with? 2 c) What about resist stripping after etching? We typically use a big warm vat of NMP that is shared by all users. We can also do a plasma etch but I worry about carry over from other folks as none of our plasma etchers are dedicated CMOS. 3) I presume quartz glassware works for my metal (usually aluminum) etching? Do you do regular aqua regia cleans on quartz-ware to scavenge other metals and potential contaminants? 4) We gravitate to peek tipped metal tweezers. Are they okay? Do you regularly run the tips through a RCA clean? 5) Oxidation furnace: Before trying to transition to CMOS like devices the tube was used with non-RCA cleaned wafers and a pyrex bubbler. After moving to a quartz bubbler with DI water we cleaned the 4" tube with HF. This is the one I'm really concerned about because I'm guessing that ionic contamination that might have been removed from the surface will readily diffuse back at 1000C. So should we just bite the bullet and buy a new tube? Any vendor suggestions for a 4" Blue-M? 6) Any other suggestions other than buying a dedicated CMOS tool set? I did find a very nice document from Stanford that has a lot of practical suggestions found here https://web.stanford.edu/class/ee410/cleaning.pdf ) Krishna Saraswa - Stanford University 6 tanford University araswat 11! Cleaning - Surface Issues Contaminant * Organics - Skin oils - Resist - Polymers * Metals web.stanford.edu Thank you in advance, Michael -------------- next part -------------- An HTML attachment was scrubbed... URL: From lrehn at tamu.edu Wed Mar 20 10:09:29 2019 From: lrehn at tamu.edu (Rehn, Larry A) Date: Wed, 20 Mar 2019 14:09:29 +0000 Subject: [labnetwork] CMOS Clean in a MEMS Fab Facility In-Reply-To: References: Message-ID: <98970e3513f04e51806c9b4028476c83@tamu.edu> Hello Michael, I general, I would say that you need to be most careful to control any processes the involve elevated temperature, or cleanups that occur before steps with high temperature. I would suggest dedicated quartz containers for piranha cleans. Besides suggestions from Matt below, I would concentrate first on your oxidation and furnace operations. It is best to have dedicated oxidation tubes that never see any other materials except silicon and oxides, particularly metal for annealing , sintering etc. In fact most would have a dedicated field ox tube and a separate tube just for the gate oxidation step, which is the most critical. If you only have one furnace, then you will need to change out quartz tubes (and push rods, wafer boats, profile thermocouples, etc) for each operation. When you fabricate the CMOS device it is also important to control any other sources for Na+ contamination. Will you be using polysilicon gates, or metal? If metal, than there are other process tricks to make sure the gate integrity is preserved. There are also some ongoing things that are done to maintain cleanliness of the system. Cleaning of tubes with dilute HF, monitoring the gate/oxide device performance with CV tests will ensure that you do not have too much mobile ion concentration to affect the device. Good luck! Larry A Rehn Technical Lab Manager AggieFab Nanofabrication Facility Texas A&M University 979 845-3199 lrehn at tamu.edu [cid:image001.jpg at 01CEC37D.FAF8C9E0] From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Matthew Moneck Sent: Tuesday, March 19, 2019 11:59 AM To: Martin,Michael David ; labnetwork at mtl.mit.edu Subject: Re: [labnetwork] CMOS Clean in a MEMS Fab Facility Hi Michael, Our fab does not do a lot of traditional CMOS work, so I am by no means an expert in this area. A lot of our work is concentrated in MEMS (including back-end processing on CMOS tapeout chips), magnetics, spintronics, photonics, 2D materials, functional oxides, bio interfaces, other emerging technologies. However, I can hopefully offer a few comments from lessons learned or experiences we've had in the past, especially when working on devices where trapped charge or ion contamination were an issue. Referencing your original question numbers: 1. We typically use PTFE petri dishes for this application. We routinely process 100mm wafers in low profile evaporating dishes. While not cheap, a couple dishes won't typically set you back too much. 2. We separate glassware for metal ion free (MIF) and metal ion containing (MIC) containers (I'm assuming you are using MIF developers for CMOS). Beakers are labeled MIF or MIC by etching the letters into the glass exterior of the beaker. If I recall correctly most of the beakers are Type 1, Class A, 33 expansion Borosilicate glass (note that I'm not endorsing this one way or the other for CMOS). 2A. We do not have a dedicated spinner for CMOS, but we do limit which resists can go in which spinners (in the case where non-standard resists are used). 2B. I would verify the type of glass used in the amber bottles. Also, we buy droppers in clean, sterile packaging, as we have seen that droppers packaged and stored incorrectly can introduce contaminates. In extreme cases, we have had some users request and move to glass pipettes. 2C. The shared bath of NMP would be one of my biggest concerns in this whole process. Manufacturers will list that NMP is safe on a lot of metals, including copper. However, there is a caveat. If the NMP bath collects or becomes contaminated with moisture, it makes the bath corrosive. I have seen first-hand how NMP can corrode, or even etch through metals, such as copper. If people are using the bath with such materials, it could have trace metals and other contaminants. We do not do a lot in the way of furnace work, so I will default to others in the network that are much more of an expert in this area than me, but for what it's worth, the latter questions on quartz tube contaminants would be a concern in my opinion. Even in simple annealing furnaces and our RTA, we keep "clean" and "dirty" tubes/chambers that we exchange depending on the materials being used. In regards to potential vendors, we have purchased quartz products from Technical Glass Products in the past (https://technicalglass.com/), although, again, others who do a lot more work with furnaces will likely have more input than me. Hope this helps in some capacity. Best Regards, Matt -- Matthew T. Moneck, Ph.D. Executive Manager, Claire & John Bertucci Nanotechnology Laboratory Electrical and Computer Engineering | Carnegie Mellon University 5000 Forbes Ave., Pittsburgh, PA 15213-3890 T: 412.268.5430 F: 412.268.3497 www.ece.cmu.edu nanofab.ece.cmu.edu From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Martin,Michael David Sent: Monday, March 18, 2019 2:07 PM To: labnetwork at mtl.mit.edu Subject: [labnetwork] CMOS Clean in a MEMS Fab Facility Hi, I'm trying to track down potential sources of contamination for a CMOS process we are trying to run through our predominantly MEMS fab here at U of Louisville. Really the only pieces of equipment that are dedicated for CMOS type processes is our RCA bench, an older Technics sputterer, and our oxidation furnace (sort of, see below). So I have a few questions for those of you who have experience with this: 1) For HF etch/dips is there a particular polymer type or brand we should use for our containers that are known to be free of trace metals? Can I avoid PTFE as this is super expensive? 2) When you do litho do you have separate labware for developing? We currently use a Pyrex pan develop which I know is a No-No due to Na and other ions. What sort of container does your lab use (assuming pan develop)? 2 a) Do you have a dedicated spinner for CMOS? 2 b) Is there any danger that we are picking up contamination from the amber bottles we are temporarily storing our resists in? What about the polypropylene droppers we are dispensing resists with? 2 c) What about resist stripping after etching? We typically use a big warm vat of NMP that is shared by all users. We can also do a plasma etch but I worry about carry over from other folks as none of our plasma etchers are dedicated CMOS. 3) I presume quartz glassware works for my metal (usually aluminum) etching? Do you do regular aqua regia cleans on quartz-ware to scavenge other metals and potential contaminants? 4) We gravitate to peek tipped metal tweezers. Are they okay? Do you regularly run the tips through a RCA clean? 5) Oxidation furnace: Before trying to transition to CMOS like devices the tube was used with non-RCA cleaned wafers and a pyrex bubbler. After moving to a quartz bubbler with DI water we cleaned the 4" tube with HF. This is the one I'm really concerned about because I'm guessing that ionic contamination that might have been removed from the surface will readily diffuse back at 1000C. So should we just bite the bullet and buy a new tube? Any vendor suggestions for a 4" Blue-M? 6) Any other suggestions other than buying a dedicated CMOS tool set? I did find a very nice document from Stanford that has a lot of practical suggestions found here https://web.stanford.edu/class/ee410/cleaning.pdf ) Krishna Saraswa - Stanford University 6 tanford University araswat 11! Cleaning - Surface Issues Contaminant * Organics - Skin oils - Resist - Polymers * Metals web.stanford.edu Thank you in advance, Michael -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.jpg Type: image/jpeg Size: 13188 bytes Desc: image001.jpg URL: From carsen at stanford.edu Wed Mar 20 12:00:57 2019 From: carsen at stanford.edu (Carsen Kline) Date: Wed, 20 Mar 2019 16:00:57 +0000 Subject: [labnetwork] Cycle purge on long lines Message-ID: It was my understanding that there would be no math... But going with gut feelings sometimes leads to a building evacuation, so here I am humbling myself before you. Has anyone out there in labnetwork land modeled the cycle purging of gas lines, really taking a hard look at concentration at the end of the line? How can we answer the question, "Is it safe to open up this silane line?" Our scenario involved an LPCVD furnace, replacing a dead silane MFC, failed closed, with no bypass to pump out the inlet side of the MFC. Beyond this is about 250 feet of mixed diameter tubing, with countless elbows, leading to the gas cabinet. Unable to evacuate from the chamber end, we had to rely on the gas cabinet's venturi. We cycle purged from the cabinet end, pumping and backfilling with nitrogen... until it felt good enough. I'll spare you the embarrassing details, but we learned that it definitely wasn't good enough. What's done is done (and dusted), but I'm hoping to have a quantitative measure of goodness inside the lines for future similar scenarios. Variables include tubing length/diameter/constrictions/surface roughness, venturi vacuum, nitrogen pressure, gas concentration, time, temperature gradients, and more that I'm sure to have missed. It's a complex problem, and before I talk to the fluid dynamics folks here, I wanted to ask you all how you would approach this. Thanks as always for your input. Carsen Carsen Kline Lab Operations Manager Stanford Nanofabrication Facility (650)724-8214 http://snf.stanford.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: From mtang at stanford.edu Wed Mar 20 17:17:34 2019 From: mtang at stanford.edu (Mary Tang) Date: Wed, 20 Mar 2019 14:17:34 -0700 Subject: [labnetwork] CMOS Clean in a MEMS Fab Facility In-Reply-To: <98970e3513f04e51806c9b4028476c83@tamu.edu> References: <98970e3513f04e51806c9b4028476c83@tamu.edu> Message-ID: <5fa3958d-d2db-8974-9078-8b0134784ee9@stanford.edu> Hi Michael, et al ? Good points, all.For the last few years, we have been asking ourselves the same questions, as we evolve from being predominately a CMOS-compatible lab to one where most of our labmembers don?t require this level of contamination control.It?s been a slower transition than we?d like, because the process requires unraveling the why?s of 60 years of best-known-practices, so we can figure out which rules we can break with minimal risk. The main question is what level of technology needs to be protected and to what degree.Our most demanding customers are the detector researchers.The next most demanding are the Ge/SiGe device researchers.So, we try to make sure to work with them to safeguard the high-risk process steps. The next step is to identify the process steps where there is possible transfer of contaminants.Basically, RCA cleans done before any high temperature step can rectify all sorts of assaults to the system.So at SNF, we don?t dedicate litho equipment for reasons of contamination and pretend that a CMOS substrate remains as CMOS clean when it leaves litho.There is basis for this pretense - resist developers in the 80?s were NaOH-based, but the post-etch resist cleans and pre-furnace RCA cleans were sufficient for that generation of technology.However, it?s also important to remember that temperatures don?t need to be very high for mobile ions to start migrating ? a high density plasma asher can get hot enough, so it?s advisable to carefully review the process runsheet. Depending on the stringency of your device requirements, it?s possible to share CMOS and non-CMOS processes on a single tool.You might be able to do a chamber clean or have dedicated cassettes, handlers, of inserts.You might be able to lay down a barrier or getter layer in a deposition system.You might be able to run a Cl-based clean cycle in an oxidation furnace. Lastly, every time a device run fails, the very first suspect is contamination.More often, it?s not, but rather because researchers often unknowingly violate 60 years of process integration best-practices with seemingly innocuous process changes (evaporating vs sputtering metal, damaging gates; changing barrier metal, resulting in spiking) or misprocessing (wrong implant dose).This is where careful review of the process runsheet with an experienced integration person can really save a lot of time and frustration. If you are building a process from scratch, it's best to build up from modules. I am far from expert, but will gladly share our experiences - and can refer you to the real experts. Best, Mary -- Mary X. Tang, Ph.D. Managing Director Stanford Nanofabrication Facility Paul G. Allen Building, Rm 141 420 Via Palou Mall Stanford, CA? 94305 (650)723-9980 mtang at stanford.edu https://snf.stanford.edu On 3/20/2019 7:09 AM, Rehn, Larry A wrote: > > Hello Michael, > > I general, I would say that you need to be most careful to control any > processes the involve elevated temperature, or cleanups that occur > before steps with high temperature.? I would suggest dedicated quartz > containers for piranha cleans.? Besides suggestions from Matt below, I > would concentrate first on your oxidation and furnace operations. It > is best to have dedicated oxidation tubes that never see any other > materials except silicon and oxides, particularly metal for annealing > , sintering etc.? In fact most would have a dedicated field ox tube > and a separate tube just for the gate oxidation step, which is the > most critical.? If you only have one furnace, then you will need to > change out quartz tubes (and push rods, wafer boats, profile > thermocouples, etc) for each operation.? When you fabricate the CMOS > device it is also important to control any other sources for Na+ > contamination.? Will you be using polysilicon gates, or metal?? If > metal, than there are other process tricks to make sure the gate > integrity is preserved. > > There are also some ongoing things that are done to maintain > cleanliness of the system.? Cleaning of tubes with dilute HF, > monitoring the gate/oxide device performance with CV tests will ensure > that you do not have too much mobile ion concentration to affect the > device. > > Good luck! > > Larry A Rehn > > Technical Lab Manager > > AggieFab Nanofabrication Facility > > Texas A&M University > > 979 845-3199 > > lrehn at tamu.edu > > cid:image001.jpg at 01CEC37D.FAF8C9E0 > > *From:*labnetwork-bounces at mtl.mit.edu > [mailto:labnetwork-bounces at mtl.mit.edu] *On Behalf Of *Matthew Moneck > *Sent:* Tuesday, March 19, 2019 11:59 AM > *To:* Martin,Michael David ; > labnetwork at mtl.mit.edu > *Subject:* Re: [labnetwork] CMOS Clean in a MEMS Fab Facility > > Hi Michael, > > Our fab does not do a lot of traditional CMOS work, so I am by no > means an expert in this area.? A lot of our work is concentrated in > MEMS (including back-end processing on CMOS tapeout chips), magnetics, > spintronics, photonics, 2D materials, functional oxides, bio > interfaces, other emerging technologies.? However, I can hopefully > offer a few comments from lessons learned or experiences we?ve had in > the past, especially when working on devices where trapped charge or > ion contamination were an issue. > > Referencing your original question numbers: > > 1. We typically use PTFE petri dishes for this application.? We > routinely process 100mm wafers in low profile? evaporating dishes.? > While not cheap, a couple dishes won?t typically set you back too much. > > 2. We separate glassware for metal ion free (MIF) and metal ion > containing (MIC) containers (I?m assuming you are using MIF developers > for CMOS).? Beakers are labeled MIF or MIC by etching the letters into > the glass exterior of the beaker. If I recall correctly most of the > beakers are Type 1, Class A, 33 expansion Borosilicate glass (note > that I?m not endorsing this one way or the other for CMOS). > > 2A. We do not have a dedicated spinner for CMOS, but we do limit which > resists can go in which spinners (in the case where non-standard > resists are used). > > 2B. I would verify the type of glass used in the amber bottles. Also, > we buy droppers in clean, sterile packaging, as we have seen that > droppers packaged and stored incorrectly can introduce contaminates.? > In extreme cases, we have had some users request and move to glass > pipettes. > > 2C. The shared bath of NMP would be one of my biggest concerns in this > whole process.? Manufacturers will list that NMP is safe on a lot of > metals, including copper.? However, there is a caveat.? If the NMP > bath collects or becomes contaminated with moisture, it makes the bath > corrosive.? I have seen first-hand how NMP can corrode, or even etch > through metals, such as copper.? If people are using the bath with > such materials, it could have trace metals and other contaminants. > > We do not do a lot in the way of furnace work, so I will default to > others in the network that are much more of an expert in this area > than me, but for what it?s worth, the latter questions on quartz tube > contaminants would be a concern in my opinion.? Even in simple > annealing furnaces and our RTA, we keep ?clean? and ?dirty? > tubes/chambers that we exchange depending on the materials being > used.? In regards to potential vendors, we have purchased quartz > products from Technical Glass Products in the past > (https://technicalglass.com/ > ), > although, again, others who do a lot more work with furnaces will > likely have more input than me. > > Hope this helps in some capacity. > > Best Regards, > > > Matt > > -- > *Matthew T. Moneck, Ph.D.* > Executive Manager, Claire & John Bertucci Nanotechnology Laboratory > Electrical and Computer Engineering | Carnegie Mellon University > 5000 Forbes Ave., Pittsburgh, PA 15213-3890 > T: 412.268.5430 > F: 412.268.3497 > www.ece.cmu.edu > > nanofab.ece.cmu.edu > > *From:*labnetwork-bounces at mtl.mit.edu > > [mailto:labnetwork-bounces at mtl.mit.edu] *On Behalf Of *Martin,Michael > David > *Sent:* Monday, March 18, 2019 2:07 PM > *To:* labnetwork at mtl.mit.edu > *Subject:* [labnetwork] CMOS Clean in a MEMS Fab Facility > > Hi, > > I'm trying to track down potential sources of contamination for a CMOS > process we are trying to run through our predominantly MEMS fab here > at U of Louisville.? Really the only pieces of equipment that are > dedicated for CMOS type processes is our RCA bench, an older Technics > sputterer, and our oxidation furnace (sort of, see below). So I have a > few questions for those of you who have experience with this: > > 1) For HF etch/dips is there a particular polymer type or brand we > should use for our containers that are known to be free of trace > metals? Can I avoid PTFE as this is super expensive? > > 2) When you do litho do you have separate labware for developing? We > currently use a Pyrex pan develop which I know is a No-No due to Na > and other ions. What sort of container does your lab use (assuming pan > develop)? > > 2 a) Do you have a dedicated spinner for CMOS? > > 2 b) Is there any danger that we are picking up contamination from the > amber bottles we are temporarily storing our resists in? What about > the polypropylene droppers we are dispensing resists with? > > 2 c) What about resist stripping after etching? We typically use a big > warm vat of NMP that is shared by all users.? We can also do a plasma > etch but I worry about carry over from other folks as none of our > plasma etchers are dedicated CMOS. > > 3) I presume quartz glassware works for my metal (usually aluminum) > etching? Do you do regular aqua regia cleans on quartz-ware to > scavenge other metals and potential contaminants? > > 4) We gravitate to peek tipped metal tweezers.? Are they okay? Do you > regularly run the tips through a RCA clean? > > 5) Oxidation furnace: Before trying to transition to CMOS like devices > the tube was used with non-RCA cleaned wafers and a pyrex bubbler. > After moving to a quartz bubbler with DI water we cleaned the 4" tube > with HF.? This is the one I'm really concerned about because I'm > guessing that ionic contamination that might have been removed from > the surface will readily diffuse back at 1000C.? So should we just > bite the bullet and buy a new tube? Any vendor suggestions for a 4" > Blue-M? > > 6) Any other suggestions other than buying a dedicated CMOS tool set? > > I did find a very nice document from Stanford that has a lot of > practical suggestions found here > https://web.stanford.edu/class/ee410/cleaning.pdf > > ) > > Krishna Saraswa - Stanford University > > > 6 tanford University araswat 11! Cleaning - Surface Issues Contaminant > ? Organics ? Skin oils ? Resist ? Polymers ? Metals > > web.stanford.edu > > Thank you in advance, > > ?? Michael > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.jpg Type: image/jpeg Size: 13188 bytes Desc: not available URL: From kevin.walsh at louisville.edu Tue Mar 26 14:30:37 2019 From: kevin.walsh at louisville.edu (Walsh,Kevin M.) Date: Tue, 26 Mar 2019 18:30:37 +0000 Subject: [labnetwork] contact angle goniometer Message-ID: Does anyone have advice for a nice automated reasonably-priced contact angle goniometer? Thanks in advance, Kevin Dr. Kevin M. Walsh Associate Dean of Research and Facilities, Speed School of Engineering Samuel T. Fife Professor of Electrical and Computer Engineering Director of the NSF NNCI KY Multiscale Manufacturing and Nano Integration Node (MMNIN) and the NSF KY nanoNET Fellow of the National Academy of Inventors JB Speed Bldg. Deans Office Louisville, KY 40292 Office # (502) 852-0826 Fax # (502) 852-8128 www.kymultiscale.net [small logo] [NNCI_Longhand] -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.jpg Type: image/jpeg Size: 6431 bytes Desc: image001.jpg URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image002.png Type: image/png Size: 53226 bytes Desc: image002.png URL: From david.gottfried at ien.gatech.edu Tue Mar 26 16:53:29 2019 From: david.gottfried at ien.gatech.edu (Gottfried, David S) Date: Tue, 26 Mar 2019 20:53:29 +0000 Subject: [labnetwork] contact angle goniometer In-Reply-To: References: Message-ID: Kevin: We have a rame-hart Model 250 here at Georgia Tech. rame-hart has a variety of models, depending on desired features, and are pretty easy to use. They also have excellent user support. David David S. Gottfried, Ph.D. Institute for Electronics and Nanotechnology Georgia Institute of Technology From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Walsh,Kevin M. Sent: Tuesday, March 26, 2019 2:31 PM To: labnetwork at mtl.mit.edu Cc: Walsh,Kevin M. Subject: [labnetwork] contact angle goniometer Does anyone have advice for a nice automated reasonably-priced contact angle goniometer? Thanks in advance, Kevin Dr. Kevin M. Walsh Associate Dean of Research and Facilities, Speed School of Engineering Samuel T. Fife Professor of Electrical and Computer Engineering Director of the NSF NNCI KY Multiscale Manufacturing and Nano Integration Node (MMNIN) and the NSF KY nanoNET Fellow of the National Academy of Inventors JB Speed Bldg. Deans Office Louisville, KY 40292 Office # (502) 852-0826 Fax # (502) 852-8128 www.kymultiscale.net [small logo] [NNCI_Longhand] -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.jpg Type: image/jpeg Size: 6431 bytes Desc: image001.jpg URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image002.png Type: image/png Size: 53226 bytes Desc: image002.png URL: From bill_flounders at berkeley.edu Tue Mar 26 20:48:48 2019 From: bill_flounders at berkeley.edu (A. William (Bill) FLOUNDERS) Date: Tue, 26 Mar 2019 17:48:48 -0700 Subject: [labnetwork] contact angle goniometer In-Reply-To: References: Message-ID: Kevin, We have a manual Kruss. Simple, reliable. They offer many models - not familiar with automated models. See Kruss Scientific Drop Shap Analysis (DSA) Bill Flounders UC Berkeley On Tue, Mar 26, 2019 at 12:54 PM Walsh,Kevin M. wrote: > Does anyone have advice for a nice automated reasonably-priced contact > angle goniometer? > > > > Thanks in advance, > > Kevin > > > > *Dr. Kevin M. Walsh* > > Associate Dean of Research and Facilities, Speed School of Engineering > > Samuel T. Fife Professor of Electrical and Computer Engineering > Director of the NSF NNCI KY Multiscale Manufacturing and Nano Integration > Node (MMNIN) and the NSF KY nanoNET > > Fellow of the National Academy of Inventors > > JB Speed Bldg. Deans Office > > Louisville, KY 40292 > > Office # (502) 852-0826 > > Fax # (502) 852-8128 > > > > *www.kymultiscale.net * > > > > > > *[image: small logo]* > > > > [image: NNCI_Longhand] > > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.jpg Type: image/jpeg Size: 6431 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image002.png Type: image/png Size: 53226 bytes Desc: not available URL: From c.ober at cornell.edu Tue Mar 26 20:56:58 2019 From: c.ober at cornell.edu (Christopher Kemper Ober) Date: Wed, 27 Mar 2019 00:56:58 +0000 Subject: [labnetwork] Search for Director of Operations for the Cornell Nanoscale Facility - pdf attached Message-ID: <4E03D4FF-4958-4E29-A559-3EA16EFBF8DB@cornell.edu> Director of Operations Cornell NanoScale Science and Technology Facility (CNF) Cornell University Ithaca, New York Cornell University is seeking candidates for the position of Director of Operations for the Cornell NanoScale Science and Technology Facility. The Cornell NanoScale Science & Technology Facility (CNF) is a pre-eminent national user facility that supports a broad range of nanoscale science and technology projects by providing state-of-the- art resources coupled with expert staff support. Research at CNF encompasses the physical sciences, engineering, and life sciences with a strong inter-disciplinary emphasis. Serving the science and engineering community since 1977, CNF has over 500 users per year many external to Cornell who use the fabrication, synthesis, computation, characterization, and integration resources of CNF to build structures, devices, and systems from nanometer to micrometer length-scales. With a multi-million dollar operation, CNF is part of the National Nanoscale Coordinated Infrastructure (NNCI), the NSF-funded nanofabrication network. Reporting to the Director of CNF, the Director of Operations is the chief operating officer of CNF whose responsibilities include oversight of facility management and operations, user research programs, facility financials, external and internal relations, industrial relations, and program development, including outreach, education, and sponsored research funding, that are necessary for successful fulfillment of the mission of CNF and the NNCI. Working with CNF?s Director and its Executive Board, the Director of Operations plays a key role in strategic planning, development of and implementation of new and innovative programs, as well as the acquisition of facility tools and capabilities to meet current and emerging research needs with a goal to grow the CNF user base. The preferred candidate will have a M.S. and/or Ph.D. in a related physical science, life science or engineering discipline and at least 10 years of academic or industrial experience or equivalent combination. Additional valued qualifications include one or more of the following: * Technical knowledge of the equipment and the diverse research that occurs in this type of facility; * Ability to work with both industrial and academic users, working entrepreneurially to build a broad base of users * Demonstrated effective organizational and communication skills * Ability to effectively manage and develop a team of technical and professional staff. * Proficiency in sponsored funding and experience with financial management CNF staff enjoy working in a collaborative and innovative organization within Cornell University, an award-winning employer recognized for supporting employee health, workplace diversity, and environmental sustainability. CNF is located on the main Ithaca campus, in the heart of the Finger Lakes of central New York State. Ithaca and the surrounding area is noted for a high quality of life surrounded by natural beauty and a vibrant community. To apply, please submit a resume/CV, letter of application, and a list of 3 references. Materials may be submitted online at Building a Career at Cornell. Diversity and Inclusion are a part of Cornell University?s heritage. We?re an employer and educator recognized for valuing AA/EEO, Protected Veterans and Individuals with Disabilities. [cid:5e52cd0e-cbd4-4fd9-88bc-6ded4ba77f2f at namprd04.prod.outlook.com] [cid:50e0d026-fe75-41cb-b995-ebb47a394586 at namprd04.prod.outlook.com] Chris Ober cko3 at cornell.edu -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: page1image39104320.png Type: image/png Size: 118 bytes Desc: page1image39104320.png URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: page1image39107584.png Type: image/png Size: 113 bytes Desc: page1image39107584.png URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: CNF Director Ad_final2019.pdf Type: application/pdf Size: 29930 bytes Desc: CNF Director Ad_final2019.pdf URL: From sguo18 at yorku.ca Wed Mar 27 10:54:01 2019 From: sguo18 at yorku.ca (Xin (Shane) Guo) Date: Wed, 27 Mar 2019 14:54:01 +0000 Subject: [labnetwork] Commercial power interlocks compatible with NEMO Message-ID: Hi Colleagues, I saw that NEMO had been discussed here before. We are interested in NEMO as well. What's challenging for us to figure out is identifying IP-based power interlocks. I think that a lot of you bought FPGA boards and progammed them yourselves. Are there any commercial products compatible with NEMO and are ready to use with no or minimum customisation. Cheers Shane -------------- next part -------------- An HTML attachment was scrubbed... URL: From betemc at rit.edu Wed Mar 27 12:26:46 2019 From: betemc at rit.edu (Bruce Tolleson) Date: Wed, 27 Mar 2019 16:26:46 +0000 Subject: [labnetwork] Semitest SCA 2500 Support Message-ID: Dear Labnetwork, Does anyone have a contact that still offers support for the SemiTest SCA 2500 Surface Charge Analyzer? We have tried to reach the original manufacturer in Bellerica, Mass. At 978-667-8783 and the number is disconnected. Web searching doesn't come up with a contact that is still valid. If you have a place that still supports the system I would greatly appreciate that contact. Thank you, Bruce E. Tolleson Rochester Institute of Technology 82 Lomb Memorial Drive, Bldg 17-2627 Rochester, NY 14623-5604 (585) 478-3836 [http://www.rit.edu/~962www/logos/tiger_walking_rit_color.jpg] -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.jpg Type: image/jpeg Size: 2550 bytes Desc: image001.jpg URL: From iharvey at Princeton.EDU Thu Mar 28 10:07:21 2019 From: iharvey at Princeton.EDU (Ian Harvey) Date: Thu, 28 Mar 2019 14:07:21 +0000 Subject: [labnetwork] Fwd: [UCE] Commercial power interlocks compatible with NEMO References: <38B79243-A751-4B64-81B7-D52029ED8825@eng.utah.edu> Message-ID: Dear Shane and Labnetwork colleagues, We implemented the NEMO LMS here at Princeton last August without incident and have not looked back. Many thanks to the visionary folks at NIST who made this available to our community as the first truly open source (no-charge) cleanroom soft management solution. There are many options for lockout boxes. Jerry Bowser (NIST) and I are planning to host an afternoon information session, Thursday, April 25, here at Princeton. We will make this available by WebEx or other online method. Our respective (NIST/Princeton) technical experts will be leading the discussion. In that session we will briefly talk about our in-house solution to Shane?s question, below, as well as feature customization we have implemented at Princeton, documentation under development at NIST, and a Princeton/NIST roadmap for further feature development. We are definitely interested in a crowd-sourcing model for Python-based feature development and look to other campuses to share in both the vision and the execution of a continuously improving and expanding whole-lab management capability. We have just sent out an invite recently and you can RSVP here if you would like to attend live or by WebEx. Happy Spring! ?Ian Ian R. Harvey Cleanroom Director Princeton University, Institute of Materials 70 Prospect Avenue, Princeton, NJ 08540 609-258-5922 (office) iharvey at princeton.edu PRISM-Cleanroom.princeton.edu Begin forwarded message: From: "Xin (Shane) Guo" > Subject: [UCE] [labnetwork] Commercial power interlocks compatible with NEMO Date: March 27, 2019 10:54:01 AM EDT To: "labnetwork at mtl.mit.edu" > Hi Colleagues, I saw that NEMO had been discussed here before. We are interested in NEMO as well. What's challenging for us to figure out is identifying IP-based power interlocks. I think that a lot of you bought FPGA boards and progammed them yourselves. Are there any commercial products compatible with NEMO and are ready to use with no or minimum customisation. Cheers Shane _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork -------------- next part -------------- An HTML attachment was scrubbed... URL: From kmcpeak at lsu.edu Thu Mar 28 11:56:41 2019 From: kmcpeak at lsu.edu (Kevin M McPeak) Date: Thu, 28 Mar 2019 15:56:41 +0000 Subject: [labnetwork] Commercial power interlocks compatible with NEMO In-Reply-To: References: Message-ID: Dear Shane, Here at the LSU cleanroom we use NEMO and implemented an IP interlock system with a Raspberry PI an Arduino UNO and a 24V relay driver shield plus some Python code written by a CS student. We are happy with the results. If you are interested in learning more I am happy to discuss. Regards, Kevin On Wed, Mar 27, 2019 at 11:09 AM Xin (Shane) Guo wrote: > > Hi Colleagues, > > I saw that NEMO had been discussed here before. We are interested in NEMO as well. > > What's challenging for us to figure out is identifying IP-based power interlocks. I think that a lot of you bought FPGA boards and progammed them yourselves. Are there any commercial products compatible with NEMO and are ready to use with no or minimum customisation. > > Cheers > > Shane > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://nam04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fmtl.mit.edu%2Fmailman%2Flistinfo.cgi%2Flabnetwork&data=02%7C01%7Ckmcpeak%40lsu.edu%7Ce812531673624639c57b08d6b2ce921b%7C2d4dad3f50ae47d983a09ae2b1f466f8%7C0%7C0%7C636892997616270407&sdata=K8xOHFgu6JqQ4V8P9LBrjb67GqCCmCMvAxgNqu8Uul0%3D&reserved=0 -- Kevin M. McPeak Assistant Professor | LSU Dept. of Chemical Engineering 225-578-0058 | mcpeaklab.com | lsu.edu/nanofabrication From lesjo at dtu.dk Thu Mar 28 12:10:40 2019 From: lesjo at dtu.dk (Leif Johansen) Date: Thu, 28 Mar 2019 16:10:40 +0000 Subject: [labnetwork] contact angle goniometer In-Reply-To: References: Message-ID: Hello Kevin, We have an automated DSA-100 Drop Shape Analyzer from Kr?ss in Germany. It is a very nice tool, but it can hardly be classified as reasonably-priced. Kruss also has less expensive products, like the DSA-25. https://www.kruss-scientific.com/products/drop-shape/dsa25/drop-shape-analyzer-dsa25/ I have previously worked with a manual Tantec contact angle meter. As far as I know, they are not that expensive. https://cheminstruments.com/contact-angle-meter.html Hustech also sell contact angle goniometers, but I know very little of these: http://www.hustech.co.kr/?portfolio=rame-hart-model-400-goniometer-with-wafer-support Depending on the precision and reproducibility you need, you can also try building your own system with a light source, a stage, a droplet dispenser and a digital camera. The tricky part is the precise deposition of a droplet and the precise measurement of the contact angle . You could buy a micrometer dispenser: https://www.coleparmer.co.uk/i/gilmont-gs-1200-a-micrometer-burette-style-dispenser-1-ea/0784600 . EPFL offers free drop shape analysis software on their homepage: http://bigwww.epfl.ch/demo/dropanalysis/ Best regards, Leif From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Walsh,Kevin M. Sent: 26. marts 2019 19:31 To: labnetwork at mtl.mit.edu Cc: Walsh,Kevin M. Subject: [labnetwork] contact angle goniometer Does anyone have advice for a nice automated reasonably-priced contact angle goniometer? Thanks in advance, Kevin Dr. Kevin M. Walsh Associate Dean of Research and Facilities, Speed School of Engineering Samuel T. Fife Professor of Electrical and Computer Engineering Director of the NSF NNCI KY Multiscale Manufacturing and Nano Integration Node (MMNIN) and the NSF KY nanoNET Fellow of the National Academy of Inventors JB Speed Bldg. Deans Office Louisville, KY 40292 Office # (502) 852-0826 Fax # (502) 852-8128 www.kymultiscale.net [small logo] [NNCI_Longhand] -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image001.jpg Type: image/jpeg Size: 6431 bytes Desc: image001.jpg URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: image002.png Type: image/png Size: 53226 bytes Desc: image002.png URL: From hathaway at cns.fas.harvard.edu Thu Mar 28 16:24:14 2019 From: hathaway at cns.fas.harvard.edu (Hathaway, Malcolm R) Date: Thu, 28 Mar 2019 20:24:14 +0000 Subject: [labnetwork] Commercial power interlocks compatible with NEMO In-Reply-To: References: Message-ID: <5C9D2D81.1020203@cns.fas.harvard.edu> Hi Shane, I don't know if the ones we use are NEMO-compatible right out of the box, but the CLEAN system at Harvard CNS uses ADAM-6060 6-channel relays from Advantech. They are the only such ones I've run across, so perhaps everybody uses them, if they don't make their own. Just needs a static IP address, and compatible control software (which I suspect is quite generic)... Only drawback is they only have 6 channels, so you need many of them scattered around the labs to serve everything that is interlocked. We have them in these little boxes, which can serve up 6 sets of "dry contacts" (to work in series with tool internal interlock circuits), or 12V outputs, which we use to trigger power relays for equipment control PC monitors. Mac Mac Hathaway Senior Process and Systems Engineer Harvard Center for Nanoscale Systems 11 Oxford St. Cambridge, MA 02138 617-495-9012 On 3/28/2019 11:56 AM, Kevin M McPeak wrote: Dear Shane, Here at the LSU cleanroom we use NEMO and implemented an IP interlock system with a Raspberry PI an Arduino UNO and a 24V relay driver shield plus some Python code written by a CS student. We are happy with the results. If you are interested in learning more I am happy to discuss. Regards, Kevin On Wed, Mar 27, 2019 at 11:09 AM Xin (Shane) Guo wrote: Hi Colleagues, I saw that NEMO had been discussed here before. We are interested in NEMO as well. What's challenging for us to figure out is identifying IP-based power interlocks. I think that a lot of you bought FPGA boards and progammed them yourselves. Are there any commercial products compatible with NEMO and are ready to use with no or minimum customisation. Cheers Shane _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://nam04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fmtl.mit.edu%2Fmailman%2Flistinfo.cgi%2Flabnetwork&data=02%7C01%7Ckmcpeak%40lsu.edu%7Ce812531673624639c57b08d6b2ce921b%7C2d4dad3f50ae47d983a09ae2b1f466f8%7C0%7C0%7C636892997616270407&sdata=K8xOHFgu6JqQ4V8P9LBrjb67GqCCmCMvAxgNqu8Uul0%3D&reserved=0 -------------- next part -------------- An HTML attachment was scrubbed... URL: From odc1n08 at soton.ac.uk Thu Mar 28 18:43:54 2019 From: odc1n08 at soton.ac.uk (Clark O.D.) Date: Thu, 28 Mar 2019 22:43:54 +0000 Subject: [labnetwork] Vanadium Oxide Deposition Message-ID: Hi all, recently we have been receiving several requests for Vanadium Oxide deposition via sputtering and ALD. Users are primarily interested in the +4 oxidation state VO2 compound which going on the Sigma Aldrich powder SDS can be handled with typical minor precautions and controls. However V2O5 (which I believe is the more energetically stable and preferred oxidation state upon exposure to atmosphere?) is highly hazardous in dust form regarding it's toxicity, Cat1 for eye damage, and Cat 2 for mutagenicity and reproductive toxicity. So far work with the compound has been declined on the basis of these assessments and because we have no way to measure the amount of material (or its oxidation state) that may or may not be emitted from chambers when they are opened for cleaning. I would be interested to know if you have allowed vanadium oxide deposition or etching in your facilities (or not), and if you did what controls were enacted to enable safe cleaning of the chambers involved? One idea that has been floated is that Vanadium Pentaflouride is a volatile etch product and perhaps F based plasma cleaning following deposition could help to reduce risk. Although again I am reluctant because the problem of never knowing what particulates lurk in the chamber upon opening is still an issue. Best regards, Owain -------------- next part -------------- An HTML attachment was scrubbed... URL: From shux at ucsd.edu Thu Mar 28 21:17:00 2019 From: shux at ucsd.edu (Shu Xiang) Date: Thu, 28 Mar 2019 18:17:00 -0700 Subject: [labnetwork] Alternative to HMDS Based Spin-on Primer Message-ID: Dear Colleagues, I'm wondering if you have any suggestions for spin-on primer / adhesion promoter as a substitute for HMDS vapor prime process. We used to work with Microchem's MCC Primer 80/20, which is a dilute solution of HMDS in PGMEA, but the company recently discontinued it. We tried several alternatives including making our own version of the solution, but none worked as well. The majority of resists we work with that require priming are Microchem's AZ1500 and AZ12XT-20PL series. If you have experience with or know of any similar alternatives that are easily accessible from an U.S. distributor, please let me know. Thank you, -- Shu Xiang Process Development Engineer / Area Safety Coordinator Nano3 Cleanroom Facility University of California, San Diego shux at ucsd.edu | (858) 534-6678 | Mailing Address -------------- next part -------------- An HTML attachment was scrubbed... URL: From shimonel at savion.huji.ac.il Fri Mar 29 03:49:14 2019 From: shimonel at savion.huji.ac.il (Shimon Eliav) Date: Fri, 29 Mar 2019 07:49:14 +0000 Subject: [labnetwork] Commercial power interlocks compatible with NEMO In-Reply-To: <5C9D2D81.1020203@cns.fas.harvard.edu> References: <5C9D2D81.1020203@cns.fas.harvard.edu> Message-ID: Hi Shane, Here at Hebrew University we use a 8 channels Digital I/O box from National Instruments (NI-9472): http://www.ni.com/en-il/shop/select/c-series-digital-module?modelId=122223 Simple to use, not expensive and very robust: in use for more than 10 years. Regards, Shimon From: labnetwork-bounces at mtl.mit.edu [mailto:labnetwork-bounces at mtl.mit.edu] On Behalf Of Hathaway, Malcolm R Sent: Thursday, 28 March 2019 22:24 To: labnetwork at mtl.mit.edu Subject: Re: [labnetwork] Commercial power interlocks compatible with NEMO Hi Shane, I don't know if the ones we use are NEMO-compatible right out of the box, but the CLEAN system at Harvard CNS uses ADAM-6060 6-channel relays from Advantech. They are the only such ones I've run across, so perhaps everybody uses them, if they don't make their own. Just needs a static IP address, and compatible control software (which I suspect is quite generic)... Only drawback is they only have 6 channels, so you need many of them scattered around the labs to serve everything that is interlocked. We have them in these little boxes, which can serve up 6 sets of "dry contacts" (to work in series with tool internal interlock circuits), or 12V outputs, which we use to trigger power relays for equipment control PC monitors. Mac Mac Hathaway Senior Process and Systems Engineer Harvard Center for Nanoscale Systems 11 Oxford St. Cambridge, MA 02138 617-495-9012 On 3/28/2019 11:56 AM, Kevin M McPeak wrote: Dear Shane, Here at the LSU cleanroom we use NEMO and implemented an IP interlock system with a Raspberry PI an Arduino UNO and a 24V relay driver shield plus some Python code written by a CS student. We are happy with the results. If you are interested in learning more I am happy to discuss. Regards, Kevin On Wed, Mar 27, 2019 at 11:09 AM Xin (Shane) Guo wrote: Hi Colleagues, I saw that NEMO had been discussed here before. We are interested in NEMO as well. What's challenging for us to figure out is identifying IP-based power interlocks. I think that a lot of you bought FPGA boards and progammed them yourselves. Are there any commercial products compatible with NEMO and are ready to use with no or minimum customisation. Cheers Shane _______________________________________________ labnetwork mailing list labnetwork at mtl.mit.edu https://nam04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fmtl.mit.edu%2Fmailman%2Flistinfo.cgi%2Flabnetwork&data=02%7C01%7Ckmcpeak%40lsu.edu%7Ce812531673624639c57b08d6b2ce921b%7C2d4dad3f50ae47d983a09ae2b1f466f8%7C0%7C0%7C636892997616270407&sdata=K8xOHFgu6JqQ4V8P9LBrjb67GqCCmCMvAxgNqu8Uul0%3D&reserved=0 -------------- next part -------------- An HTML attachment was scrubbed... URL: From kamal.yadav at gmail.com Fri Mar 29 08:04:45 2019 From: kamal.yadav at gmail.com (Kamal Yadav) Date: Fri, 29 Mar 2019 08:04:45 -0400 Subject: [labnetwork] Alternative to HMDS Based Spin-on Primer In-Reply-To: References: Message-ID: Dear Shu, You can buy pure HMDS. You can do vapor prime works better than spin. Have a HMDS compatible container Stainless steel or Teflon or similar with a lid or use Al foil as lid. Pour few ml in the container anywhere so that its just visible you just need little to create vapors. Load your wafer in a wafer cassette and load the cassette into the container for few mins with lid closed. HMDS should not be inhaled so need a fume hood space for this. You should have your monolayer of HMDS. There is Surpass 3000 as well, where wafer needs to immersed and rinsed in DI water later. I think vapor HMDS should work fine. You can buy SS containers big enough online that can take your wafer cassette. Thanks, Kamal On Fri, Mar 29, 2019, 7:51 AM Shu Xiang Dear Colleagues, > > I'm wondering if you have any suggestions for spin-on primer / adhesion > promoter as a substitute for HMDS vapor prime process. > > We used to work with Microchem's MCC Primer 80/20, which is a dilute > solution of HMDS in PGMEA, but the company recently discontinued it. We > tried several alternatives including making our own version of the > solution, but none worked as well. The majority of resists we work with > that require priming are Microchem's AZ1500 and AZ12XT-20PL series. > > If you have experience with or know of any similar alternatives that are > easily accessible from an U.S. distributor, please let me know. > > Thank you, > -- > Shu Xiang > > Process Development Engineer / Area Safety Coordinator > Nano3 Cleanroom Facility > University of California, San Diego > shux at ucsd.edu | (858) 534-6678 | Mailing Address > > _______________________________________________ > labnetwork mailing list > labnetwork at mtl.mit.edu > https://mtl.mit.edu/mailman/listinfo.cgi/labnetwork > -------------- next part -------------- An HTML attachment was scrubbed... URL: From na2661 at columbia.edu Fri Mar 29 16:10:12 2019 From: na2661 at columbia.edu (Nava Ariel-Sternberg) Date: Fri, 29 Mar 2019 16:10:12 -0400 Subject: [labnetwork] KCl deposition? Message-ID: <01a501d4e66b$6b1403f0$413c0bd0$@columbia.edu> Dear all, We got a request to deposit KCl which we're not experienced with. Has anyone done this before? How? Can you share some tips? Concerns? Thanks, Nava Nava Ariel-Sternberg, Ph.D. Director of CNI Shared Labs CEPSR/MC 8903 530 west 120th st. NY NY 10027 Office: 212-8549927 Cell: 201-5627600 -------------- next part -------------- An HTML attachment was scrubbed... URL: