[labnetwork] CMOS Clean in a MEMS Fab Facility
Mary Tang
mtang at stanford.edu
Wed Mar 20 17:17:34 EDT 2019
Hi Michael, et al –
Good points, all.For the last few years, we have been asking ourselves
the same questions, as we evolve from being predominately a
CMOS-compatible lab to one where most of our labmembers don’t require
this level of contamination control.It’s been a slower transition than
we’d like, because the process requires unraveling the why’s of 60 years
of best-known-practices, so we can figure out which rules we can break
with minimal risk.
The main question is what level of technology needs to be protected and
to what degree.Our most demanding customers are the detector
researchers.The next most demanding are the Ge/SiGe device
researchers.So, we try to make sure to work with them to safeguard the
high-risk process steps.
The next step is to identify the process steps where there is possible
transfer of contaminants.Basically, RCA cleans done before any high
temperature step can rectify all sorts of assaults to the system.So at
SNF, we don’t dedicate litho equipment for reasons of contamination and
pretend that a CMOS substrate remains as CMOS clean when it leaves
litho.There is basis for this pretense - resist developers in the 80’s
were NaOH-based, but the post-etch resist cleans and pre-furnace RCA
cleans were sufficient for that generation of technology.However, it’s
also important to remember that temperatures don’t need to be very high
for mobile ions to start migrating – a high density plasma asher can get
hot enough, so it’s advisable to carefully review the process runsheet.
Depending on the stringency of your device requirements, it’s possible
to share CMOS and non-CMOS processes on a single tool.You might be able
to do a chamber clean or have dedicated cassettes, handlers, of
inserts.You might be able to lay down a barrier or getter layer in a
deposition system.You might be able to run a Cl-based clean cycle in an
oxidation furnace.
Lastly, every time a device run fails, the very first suspect is
contamination.More often, it’s not, but rather because researchers often
unknowingly violate 60 years of process integration best-practices with
seemingly innocuous process changes (evaporating vs sputtering metal,
damaging gates; changing barrier metal, resulting in spiking) or
misprocessing (wrong implant dose).This is where careful review of the
process runsheet with an experienced integration person can really save
a lot of time and frustration. If you are building a process from
scratch, it's best to build up from modules.
I am far from expert, but will gladly share our experiences - and can
refer you to the real experts.
Best,
Mary
--
Mary X. Tang, Ph.D.
Managing Director
Stanford Nanofabrication Facility
Paul G. Allen Building, Rm 141
420 Via Palou Mall
Stanford, CA 94305
(650)723-9980
mtang at stanford.edu
https://snf.stanford.edu
On 3/20/2019 7:09 AM, Rehn, Larry A wrote:
>
> Hello Michael,
>
> I general, I would say that you need to be most careful to control any
> processes the involve elevated temperature, or cleanups that occur
> before steps with high temperature. I would suggest dedicated quartz
> containers for piranha cleans. Besides suggestions from Matt below, I
> would concentrate first on your oxidation and furnace operations. It
> is best to have dedicated oxidation tubes that never see any other
> materials except silicon and oxides, particularly metal for annealing
> , sintering etc. In fact most would have a dedicated field ox tube
> and a separate tube just for the gate oxidation step, which is the
> most critical. If you only have one furnace, then you will need to
> change out quartz tubes (and push rods, wafer boats, profile
> thermocouples, etc) for each operation. When you fabricate the CMOS
> device it is also important to control any other sources for Na+
> contamination. Will you be using polysilicon gates, or metal? If
> metal, than there are other process tricks to make sure the gate
> integrity is preserved.
>
> There are also some ongoing things that are done to maintain
> cleanliness of the system. Cleaning of tubes with dilute HF,
> monitoring the gate/oxide device performance with CV tests will ensure
> that you do not have too much mobile ion concentration to affect the
> device.
>
> Good luck!
>
> Larry A Rehn
>
> Technical Lab Manager
>
> AggieFab Nanofabrication Facility
>
> Texas A&M University
>
> 979 845-3199
>
> lrehn at tamu.edu <mailto:lrehn at tamu.edu>
>
> cid:image001.jpg at 01CEC37D.FAF8C9E0
>
> *From:*labnetwork-bounces at mtl.mit.edu
> [mailto:labnetwork-bounces at mtl.mit.edu] *On Behalf Of *Matthew Moneck
> *Sent:* Tuesday, March 19, 2019 11:59 AM
> *To:* Martin,Michael David <michael.martin at louisville.edu>;
> labnetwork at mtl.mit.edu
> *Subject:* Re: [labnetwork] CMOS Clean in a MEMS Fab Facility
>
> Hi Michael,
>
> Our fab does not do a lot of traditional CMOS work, so I am by no
> means an expert in this area. A lot of our work is concentrated in
> MEMS (including back-end processing on CMOS tapeout chips), magnetics,
> spintronics, photonics, 2D materials, functional oxides, bio
> interfaces, other emerging technologies. However, I can hopefully
> offer a few comments from lessons learned or experiences we’ve had in
> the past, especially when working on devices where trapped charge or
> ion contamination were an issue.
>
> Referencing your original question numbers:
>
> 1. We typically use PTFE petri dishes for this application. We
> routinely process 100mm wafers in low profile evaporating dishes.
> While not cheap, a couple dishes won’t typically set you back too much.
>
> 2. We separate glassware for metal ion free (MIF) and metal ion
> containing (MIC) containers (I’m assuming you are using MIF developers
> for CMOS). Beakers are labeled MIF or MIC by etching the letters into
> the glass exterior of the beaker. If I recall correctly most of the
> beakers are Type 1, Class A, 33 expansion Borosilicate glass (note
> that I’m not endorsing this one way or the other for CMOS).
>
> 2A. We do not have a dedicated spinner for CMOS, but we do limit which
> resists can go in which spinners (in the case where non-standard
> resists are used).
>
> 2B. I would verify the type of glass used in the amber bottles. Also,
> we buy droppers in clean, sterile packaging, as we have seen that
> droppers packaged and stored incorrectly can introduce contaminates.
> In extreme cases, we have had some users request and move to glass
> pipettes.
>
> 2C. The shared bath of NMP would be one of my biggest concerns in this
> whole process. Manufacturers will list that NMP is safe on a lot of
> metals, including copper. However, there is a caveat. If the NMP
> bath collects or becomes contaminated with moisture, it makes the bath
> corrosive. I have seen first-hand how NMP can corrode, or even etch
> through metals, such as copper. If people are using the bath with
> such materials, it could have trace metals and other contaminants.
>
> We do not do a lot in the way of furnace work, so I will default to
> others in the network that are much more of an expert in this area
> than me, but for what it’s worth, the latter questions on quartz tube
> contaminants would be a concern in my opinion. Even in simple
> annealing furnaces and our RTA, we keep “clean” and “dirty”
> tubes/chambers that we exchange depending on the materials being
> used. In regards to potential vendors, we have purchased quartz
> products from Technical Glass Products in the past
> (https://technicalglass.com/
> <https://urldefense.proofpoint.com/v2/url?u=https-3A__technicalglass.com_&d=DwMFAg&c=ODFT-G5SujMiGrKuoJJjVg&r=viXbs6wGaGZ-o2y0LFbqZrWN_jy4Cw47zl8d3Wrr2M4&m=xcsoSqLZ1td4AHsfpW_fG71YxxRin21Y89KQILp8A30&s=EaQ94Wv0hwJQ6Bky1QAe9J_xVZTqpH7I525wec8_bPg&e=>),
> although, again, others who do a lot more work with furnaces will
> likely have more input than me.
>
> Hope this helps in some capacity.
>
> Best Regards,
>
>
> Matt
>
> --
> *Matthew T. Moneck, Ph.D.*
> Executive Manager, Claire & John Bertucci Nanotechnology Laboratory
> Electrical and Computer Engineering | Carnegie Mellon University
> 5000 Forbes Ave., Pittsburgh, PA 15213-3890
> T: 412.268.5430
> F: 412.268.3497
> www.ece.cmu.edu
> <https://urldefense.proofpoint.com/v2/url?u=http-3A__www.ece.cmu.edu_&d=DwMFAg&c=ODFT-G5SujMiGrKuoJJjVg&r=viXbs6wGaGZ-o2y0LFbqZrWN_jy4Cw47zl8d3Wrr2M4&m=xcsoSqLZ1td4AHsfpW_fG71YxxRin21Y89KQILp8A30&s=yTWyjWfxzDFxrSZSFCC3jDg83rT8xIXzXQtGhcpAREQ&e=>
> nanofab.ece.cmu.edu
>
> *From:*labnetwork-bounces at mtl.mit.edu
> <mailto:labnetwork-bounces at mtl.mit.edu>
> [mailto:labnetwork-bounces at mtl.mit.edu] *On Behalf Of *Martin,Michael
> David
> *Sent:* Monday, March 18, 2019 2:07 PM
> *To:* labnetwork at mtl.mit.edu <mailto:labnetwork at mtl.mit.edu>
> *Subject:* [labnetwork] CMOS Clean in a MEMS Fab Facility
>
> Hi,
>
> I'm trying to track down potential sources of contamination for a CMOS
> process we are trying to run through our predominantly MEMS fab here
> at U of Louisville. Really the only pieces of equipment that are
> dedicated for CMOS type processes is our RCA bench, an older Technics
> sputterer, and our oxidation furnace (sort of, see below). So I have a
> few questions for those of you who have experience with this:
>
> 1) For HF etch/dips is there a particular polymer type or brand we
> should use for our containers that are known to be free of trace
> metals? Can I avoid PTFE as this is super expensive?
>
> 2) When you do litho do you have separate labware for developing? We
> currently use a Pyrex pan develop which I know is a No-No due to Na
> and other ions. What sort of container does your lab use (assuming pan
> develop)?
>
> 2 a) Do you have a dedicated spinner for CMOS?
>
> 2 b) Is there any danger that we are picking up contamination from the
> amber bottles we are temporarily storing our resists in? What about
> the polypropylene droppers we are dispensing resists with?
>
> 2 c) What about resist stripping after etching? We typically use a big
> warm vat of NMP that is shared by all users. We can also do a plasma
> etch but I worry about carry over from other folks as none of our
> plasma etchers are dedicated CMOS.
>
> 3) I presume quartz glassware works for my metal (usually aluminum)
> etching? Do you do regular aqua regia cleans on quartz-ware to
> scavenge other metals and potential contaminants?
>
> 4) We gravitate to peek tipped metal tweezers. Are they okay? Do you
> regularly run the tips through a RCA clean?
>
> 5) Oxidation furnace: Before trying to transition to CMOS like devices
> the tube was used with non-RCA cleaned wafers and a pyrex bubbler.
> After moving to a quartz bubbler with DI water we cleaned the 4" tube
> with HF. This is the one I'm really concerned about because I'm
> guessing that ionic contamination that might have been removed from
> the surface will readily diffuse back at 1000C. So should we just
> bite the bullet and buy a new tube? Any vendor suggestions for a 4"
> Blue-M?
>
> 6) Any other suggestions other than buying a dedicated CMOS tool set?
>
> I did find a very nice document from Stanford that has a lot of
> practical suggestions found here
> https://web.stanford.edu/class/ee410/cleaning.pdf
> <https://urldefense.proofpoint.com/v2/url?u=https-3A__web.stanford.edu_class_ee410_cleaning.pdf&d=DwMFAg&c=ODFT-G5SujMiGrKuoJJjVg&r=viXbs6wGaGZ-o2y0LFbqZrWN_jy4Cw47zl8d3Wrr2M4&m=xcsoSqLZ1td4AHsfpW_fG71YxxRin21Y89KQILp8A30&s=lekItA7Hi5mB01_AWgTSdp3AJDQnHLLdzAcqSCbAjWw&e=>
> )
>
> Krishna Saraswa - Stanford University
> <https://urldefense.proofpoint.com/v2/url?u=https-3A__web.stanford.edu_class_ee410_cleaning.pdf&d=DwMFAg&c=ODFT-G5SujMiGrKuoJJjVg&r=viXbs6wGaGZ-o2y0LFbqZrWN_jy4Cw47zl8d3Wrr2M4&m=xcsoSqLZ1td4AHsfpW_fG71YxxRin21Y89KQILp8A30&s=lekItA7Hi5mB01_AWgTSdp3AJDQnHLLdzAcqSCbAjWw&e=>
>
> 6 tanford University araswat 11! Cleaning - Surface Issues Contaminant
> • Organics – Skin oils – Resist – Polymers • Metals
>
> web.stanford.edu
>
> Thank you in advance,
>
> Michael
>
>
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> labnetwork at mtl.mit.edu
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